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US20010053602A1 - Method for manufacturing a copper interconnection in semiconductor memory device - Google Patents

Method for manufacturing a copper interconnection in semiconductor memory device Download PDF

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US20010053602A1
US20010053602A1 US09/740,945 US74094500A US2001053602A1 US 20010053602 A1 US20010053602 A1 US 20010053602A1 US 74094500 A US74094500 A US 74094500A US 2001053602 A1 US2001053602 A1 US 2001053602A1
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layer
forming
recited
barrier layer
aluminum oxide
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Suk-jae Lee
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SK Hynix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation

Definitions

  • the present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a copper interconnection provided with double diffusion barrier layers which are formed before and after a formation of the copper interconnection respectively, thereby preventing the diffusion of copper atoms effectively.
  • a copper interconnection is being applied to the device due to its low electrical resistance property.
  • a damascene process is used because dry-etching process cannot be applied directly to deposit a copper interconnection layer in a damascene pattern.
  • FIGS. 1A to 1 D there are provided cross sectional views setting forth a conventional method for manufacturing the copper interconnection by using a damascene process.
  • the manufacturing steps begin with a preparation of active matrix 110 provided with a substrate 110 , an insulating layer 114 and a contact region 111 .
  • the insulating layer 114 is formed on top of the substrate 110 and then patterned into a predetermined configuration by using a damascene process, thereby obtaining a shallow opening 116 for a metal interconnection and a deep opening for a contact.
  • a diffusion barrier layer 114 is formed on entire surface including the openings 116 , 118 and the insulating layer 112 for preventing a penetration of copper atoms into the insulating layer 114 .
  • the diffusion barrier layer is made of a material such as TiSiN, Ta, TaN, WSiN, WN or the like.
  • a first copper layer 120 is formed on the diffusion barrier layer 114 by using a method such as a physical vapor deposition (PVD) technique at a room temperature.
  • PVD physical vapor deposition
  • a second copper layer is formed on the first copper layer 120 for reflowing the copper atoms into the openings 116 , 118 by using the PVD technique at a high temperature.
  • a copper layer is polished back to a top surface of the insulating layer 112 , thereby obtaining a copper interconnection 124 being remained within the openings 116 , 118 and a diffusion barrier 114 A as shown in FIG. 1D.
  • polishing back of the copper layers 120 , 122 and the diffusion barrier layer 114 is accomplished by a chemical mechanical polishing (CMP) technique.
  • CMP chemical mechanical polishing
  • a single diffusion barrier layer e.g., TiSiN, Ta, WSiN, WN or the like.
  • the copper atoms may diffuse through these defects that a characteristic of the semiconductor device is deteriorated eventually.
  • a method for manufacturing a copper interconnection comprising the steps of: a) preparing an active matrix provided with a substrate, an insulating layer and an opening formed with a predetermined shape through the insulating layer; b) forming a first aluminum oxide layer on surfaces of the opening and the insulating layer; c) forming a first conductive barrier layer on the first aluminum oxide layer; d) forming a copper layer into the opening and on the first conductive barrier layer; e) polishing back the copper layer to a top surface of the insulating layer, thereby obtaining a copper interconnection within the opening and a first double diffusion barrier layer provided with the first aluminum oxide layer and the first conductive barrier layer; and f) forming a second diffusion barrier layer on the copper interconnection and the insulating layer.
  • FIGS. 1A, 1B, 1 C and 1 D are cross sectional views setting forth a conventional method for manufacturing a copper interconnection
  • FIGS. 2A, 2B, 2 C, 2 D, 2 E and 2 F are cross sectional views setting forth a method for manufacturing a copper interconnection in accordance with a preferred embodiment of the present invention.
  • FIGS. 2A to 2 F there are provided cross sectional views setting forth a method for manufacturing a copper interconnection in a semiconductor device in accordance with a preferred embodiment of the present invention.
  • the manufacturing steps begin with a preparation of an active matrix 201 provided with a substrate 210 , a contact region 211 and a first insulating layer 212 formed on the substrate 210 . And then, the first insulating layer 212 is patterned into a predetermined configuration by using a damascene process, thereby obtaining a shallow opening 116 for a metal interconnection and a deep opening for a contact. Thereafter, an aluminum ions (Al 3+ ) 214 are doped into surfaces including the openings 216 , 218 and the first insulating layer to a thickness ranging from approximately 10 ⁇ to approximately 50 ⁇ by accelerating the aluminum ions in an applied electric field.
  • Al 3+ aluminum ions
  • a rapid thermal annealing (RTA) or a thermal treatment in a furnace is carried out at approximately 300° C. to approximately 500° C. for forming a first aluminum oxide layer 220 by reacting the doped aluminum ions and the first insulating layer 212 , wherein the first insulating layer 212 is, for example, made of boron-phosphor silicate glass (BPSG) or the like.
  • the thermal treatment may be performed by heating up a wafer while the aluminum ions are being doped or after the aluminum ions have been completely doped.
  • a first conductive barrier layer 222 e.g., made of TiSiN, Ta, TaN, WSiN or the like, is formed on top of the first aluminum oxide layer 220 for preventing copper atoms to diffuse into the first insulating layer 212 effectively.
  • a subsequent step as shown in FIG. 2D copper is deposited into the openings 216 , 218 and over the insulating layer 212 .
  • the copper deposition is carried out through two steps. That is, a first copper layer (not shown) and a second copper layer (not shown) are deposited subsequently, for improving a gap filling capability, by using the PVD technique.
  • a copper layer 224 is polished back to a top surface of the first insulating layer 212 , thereby forming a copper interconnection 224 A being remained within the openings 216 , 218 and a first double diffusion barrier 220 A, 222 A as shown in FIG. 2E. Polishing back of the copper layer 224 is accomplished by a chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • a second conductive barrier layer 226 , a second aluminum oxide layer 228 and a second insulating layer 230 are formed on the copper interconnection 224 A and the first insulating layer 212 subsequently, as shown in FIG. 2F.
  • an oxide film (not shown) remained on the copper interconnection 224 A may be removed by using a method such as a sputtering technique.
  • the second aluminum oxide layer 228 is formed by depositing aluminum ions on the second conductive barrier layer 226 to a thickness ranging from approximately 20 ⁇ to approximately 100 ⁇ and then, a thermal treatment, e.g., the RTA or the thermal treatment in the furnace, is carried out in order to form the second aluminum oxide layer 228 as same way as that of the first aluminum oxide layer 220 . Therefore, a second double diffusion barrier layer is ontaoned.
  • the second double diffusion barrier layer 226 , 228 is used in the device, but only the second aluminum oxide layer 228 can be substituted for the second double diffusion barrier layer 226 , 228 .
  • the second aluminum oxide layer 228 may be formed by the annealing step after the aluminum ions are doped on the copper interconnection 224 A and the first insulating layer 212 to the thickness ranging from approximately 20 ⁇ to approximately 100 ⁇ .
  • the aluminum oxide layer 228 may be formed by another method.
  • the second aluminum oxide layer 228 can be formed by the annealing step after the aluminum ions are doped on an oxide film (not shown) to the thickness ranging from approximately 20 ⁇ to approximately 100 ⁇ , wherein the oxide film, e.g., made of SiO x or SiON, is formed on the copper interconnection 224 A and the first insulating layer 212 in advance.
  • oxide film e.g., made of SiO x or SiON
  • the double barrier layers i.e., the first and the second double diffusion barrier layers, it is possible to prevent the diffusion of the copper atoms effectively so that the reliability of the device can be improved in comparison with a prior art.

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A method for manufacturing a copper interconnection includes the steps of preparing an active matrix provided with a substrate, an insulating layer and an opening formed with a predetermined shape through the insulating layer, forming a first aluminum oxide layer on surfaces of the opening and the insulating layer, forming a first conductive barrier layer on the first aluminum oxide layer, forming a copper layer into the opening and on the first conductive barrier layer, polishing back the copper layer to a top surface of the insulating layer, thereby obtaining a copper interconnection within the opening and a first double diffusion barrier layer provided with the first aluminum oxide layer and the first conductive barrier layer, and forming a second diffusion barrier layer on the copper interconnection and the insulating layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a copper interconnection provided with double diffusion barrier layers which are formed before and after a formation of the copper interconnection respectively, thereby preventing the diffusion of copper atoms effectively. [0001]
    • DESCRIPTION OF THE PRIOR ART
  • With a high integration of a semiconductor device, a copper interconnection is being applied to the device due to its low electrical resistance property. For employing the copper interconnection in the semiconductor device, a damascene process is used because dry-etching process cannot be applied directly to deposit a copper interconnection layer in a damascene pattern. [0002]
  • Referring to FIGS. 1A to [0003] 1D, there are provided cross sectional views setting forth a conventional method for manufacturing the copper interconnection by using a damascene process.
  • The manufacturing steps begin with a preparation of [0004] active matrix 110 provided with a substrate 110, an insulating layer 114 and a contact region 111. The insulating layer 114 is formed on top of the substrate 110 and then patterned into a predetermined configuration by using a damascene process, thereby obtaining a shallow opening 116 for a metal interconnection and a deep opening for a contact. Thereafter, a diffusion barrier layer 114 is formed on entire surface including the openings 116, 118 and the insulating layer 112 for preventing a penetration of copper atoms into the insulating layer 114. The diffusion barrier layer is made of a material such as TiSiN, Ta, TaN, WSiN, WN or the like.
  • In a next step as shown in FIG. 1B, a [0005] first copper layer 120 is formed on the diffusion barrier layer 114 by using a method such as a physical vapor deposition (PVD) technique at a room temperature.
  • In a subsequent step as shown in FIG. 1C, a second copper layer is formed on the [0006] first copper layer 120 for reflowing the copper atoms into the openings 116, 118 by using the PVD technique at a high temperature.
  • Finally, a copper layer is polished back to a top surface of the [0007] insulating layer 112, thereby obtaining a copper interconnection 124 being remained within the openings 116, 118 and a diffusion barrier 114A as shown in FIG. 1D. Here, polishing back of the copper layers 120, 122 and the diffusion barrier layer 114 is accomplished by a chemical mechanical polishing (CMP) technique.
  • In the conventional method for manufacturing the copper interconnection, a single diffusion barrier layer, e.g., TiSiN, Ta, WSiN, WN or the like, is employed. However, in case that there are defects in the single diffusion barrier layer, the copper atoms may diffuse through these defects that a characteristic of the semiconductor device is deteriorated eventually. [0008]
    • SUMMARY OF THE INVENTION
  • It is, therefore, an object of the present invention to provide a method for manufacturing a copper interconnection provided with a double barrier layer, thereby preventing the diffusion of copper atoms effectively. [0009]
  • In accordance with one aspect of the present invention, there is provided a method for manufacturing a copper interconnection, the method comprising the steps of: a) preparing an active matrix provided with a substrate, an insulating layer and an opening formed with a predetermined shape through the insulating layer; b) forming a first aluminum oxide layer on surfaces of the opening and the insulating layer; c) forming a first conductive barrier layer on the first aluminum oxide layer; d) forming a copper layer into the opening and on the first conductive barrier layer; e) polishing back the copper layer to a top surface of the insulating layer, thereby obtaining a copper interconnection within the opening and a first double diffusion barrier layer provided with the first aluminum oxide layer and the first conductive barrier layer; and f) forming a second diffusion barrier layer on the copper interconnection and the insulating layer.[0010]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiment given in conjunction with the accompanying drawings, in which: [0011]
  • FIGS. 1A, 1B, [0012] 1C and 1D are cross sectional views setting forth a conventional method for manufacturing a copper interconnection; and
  • FIGS. 2A, 2B, [0013] 2C, 2D, 2E and 2F are cross sectional views setting forth a method for manufacturing a copper interconnection in accordance with a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Referring to FIGS. 2A to [0014] 2F, there are provided cross sectional views setting forth a method for manufacturing a copper interconnection in a semiconductor device in accordance with a preferred embodiment of the present invention.
  • The manufacturing steps begin with a preparation of an [0015] active matrix 201 provided with a substrate 210, a contact region 211 and a first insulating layer 212 formed on the substrate 210. And then, the first insulating layer 212 is patterned into a predetermined configuration by using a damascene process, thereby obtaining a shallow opening 116 for a metal interconnection and a deep opening for a contact. Thereafter, an aluminum ions (Al3+) 214 are doped into surfaces including the openings 216, 218 and the first insulating layer to a thickness ranging from approximately 10 Å to approximately 50 Å by accelerating the aluminum ions in an applied electric field.
  • In an ensuing step as shown in FIG. 2B, a rapid thermal annealing (RTA) or a thermal treatment in a furnace is carried out at approximately 300° C. to approximately 500° C. for forming a first [0016] aluminum oxide layer 220 by reacting the doped aluminum ions and the first insulating layer 212, wherein the first insulating layer 212 is, for example, made of boron-phosphor silicate glass (BPSG) or the like. Here, the thermal treatment may be performed by heating up a wafer while the aluminum ions are being doped or after the aluminum ions have been completely doped.
  • In a next step as shown in FIG. 2C, a first [0017] conductive barrier layer 222, e.g., made of TiSiN, Ta, TaN, WSiN or the like, is formed on top of the first aluminum oxide layer 220 for preventing copper atoms to diffuse into the first insulating layer 212 effectively.
  • In a subsequent step as shown in FIG. 2D, copper is deposited into the [0018] openings 216, 218 and over the insulating layer 212. Generally, the copper deposition is carried out through two steps. That is, a first copper layer (not shown) and a second copper layer (not shown) are deposited subsequently, for improving a gap filling capability, by using the PVD technique.
  • Thereafter, a [0019] copper layer 224 is polished back to a top surface of the first insulating layer 212, thereby forming a copper interconnection 224A being remained within the openings 216, 218 and a first double diffusion barrier 220A, 222A as shown in FIG. 2E. Polishing back of the copper layer 224 is accomplished by a chemical mechanical polishing (CMP).
  • Finally, a second [0020] conductive barrier layer 226, a second aluminum oxide layer 228 and a second insulating layer 230 are formed on the copper interconnection 224A and the first insulating layer 212 subsequently, as shown in FIG. 2F. Before forming the second conductive barrier layer 226, an oxide film (not shown) remained on the copper interconnection 224A may be removed by using a method such as a sputtering technique. The second aluminum oxide layer 228 is formed by depositing aluminum ions on the second conductive barrier layer 226 to a thickness ranging from approximately 20 Å to approximately 100 Å and then, a thermal treatment, e.g., the RTA or the thermal treatment in the furnace, is carried out in order to form the second aluminum oxide layer 228 as same way as that of the first aluminum oxide layer 220. Therefore, a second double diffusion barrier layer is ontaoned.
  • In the embodiment of the present invention, the second double [0021] diffusion barrier layer 226, 228 is used in the device, but only the second aluminum oxide layer 228 can be substituted for the second double diffusion barrier layer 226, 228. At this time, the second aluminum oxide layer 228 may be formed by the annealing step after the aluminum ions are doped on the copper interconnection 224A and the first insulating layer 212 to the thickness ranging from approximately 20 Å to approximately 100 Å. In addition, the aluminum oxide layer 228 may be formed by another method. That is, the second aluminum oxide layer 228 can be formed by the annealing step after the aluminum ions are doped on an oxide film (not shown) to the thickness ranging from approximately 20 Å to approximately 100 Å, wherein the oxide film, e.g., made of SiOx or SiON, is formed on the copper interconnection 224A and the first insulating layer 212 in advance.
  • By means of the double barrier layers, i.e., the first and the second double diffusion barrier layers, it is possible to prevent the diffusion of the copper atoms effectively so that the reliability of the device can be improved in comparison with a prior art. [0022]
  • While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims. [0023]

Claims (13)

What is claimed is:
1. A method for forming an interconnection, comprising the steps of:
a) preparing an active matrix having a substrate, an insulating layer over the substrate, and an opening having a predetermined shape in the insulating layer;
b) forming a first aluminum oxide layer over exposed portions of the opening and the insulating layer;
c) forming a first barrier layer over the first aluminum oxide layer;
d) forming a copper layer substantially filling the opening and covering the first barrier layer;
e) polishing the copper layer to expose the insulating layer; and
f) forming a second barrier layer over the copper layer and the exposed insulating layer.
2. The method as recited in
claim 1
, wherein the step of forming a first aluminum oxide layer includes annealing after aluminum ions (Al3+) are doped into the insulating layer and the opening.
3. The method as recited in
claim 2
, the aluminum ions are doped into the insulating layer and the opening to a thickness ranging from approximately 10 Å to approximately 50 Å by accelerating the aluminum ions in an applied electric field.
4. The method as recited in
claim 2
, said annealing includes a rapid thermal annealing (RTA) or thermal annealing in a furnace.
5. The method as recited in
claim 4
, wherein the rapid thermal annealing (RTA) or thermal annealing is carried out at a temperature ranging from approximately 300° C. to approximately 500° C.
6. The method as recited in
claim 1
, wherein the first barrier layer includes a material selected from a group of tantalum (Ta), tantalum nitride (TaN), titanium silicon nitride (TiSiN) and tungsten silicon nitride (WSiN).
7. The method as recited in
claim 1
, wherein the second barrier layer includes a double diffusion barrier layer having an aluminum oxide layer and a conductive barrier layer.
8. The method as recited in
claim 7
, wherein the second barrier layer includes a material selected from a group of Ta, TaN, TiSiN and WSiN.
9. The method as recited in
claim 1
, wherein the second barrier layer includes an aluminum oxide layer.
10. The method as recited in
claim 9
, wherein the step of forming a second barrier layer includes forming the aluminum oxide layer by annealing after aluminum ions doped into the copper layer and the insulating layer to a thickness ranging from approximately 20 Å to approximately 100 Å.
11. The method as recited in
claim 7
, wherein the step of forming a second barrier layer includes forming the aluminum oxide layer by annealing after the aluminum ions are doped into an oxide film on the copper layer and the insulating layer.
12. The method as recited in
claim 10
, wherein the aluminum oxide layer includes a material selected from a group of SiOx and SiON.
13. The method as recited in
claim 12
, wherein the step of forming a second barrier layer includes forming the aluminum oxide layer to a thickness ranging from approximately 20 Å to approximately 100 Å.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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