US20010003033A1 - Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices - Google Patents
Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices Download PDFInfo
- Publication number
- US20010003033A1 US20010003033A1 US09/302,392 US30239299A US2001003033A1 US 20010003033 A1 US20010003033 A1 US 20010003033A1 US 30239299 A US30239299 A US 30239299A US 2001003033 A1 US2001003033 A1 US 2001003033A1
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- United States
- Prior art keywords
- wafer
- area
- edge
- printing
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 230000000694 effects Effects 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000000059 patterning Methods 0.000 claims description 5
- 230000001668 ameliorated effect Effects 0.000 claims description 2
- 239000000047 product Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
- G03F7/70066—Size and form of the illuminated area in the mask plane, e.g. reticle masking blades or blinds
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
Definitions
- This invention relates to the manufacture of integrated circuit devices, and more particularly, to the manner in which patterns are printed on a semiconductive wafer to define how the wafer will eventually be diced to provide the individual chips in which the integrated circuits are formed.
- the shape of the wafer being processed is circular, while the shape of the chips after dicing is essentially square or rectangular. Accordingly the area generally printed in each step generally is either a square or a rectangle. It will be convenient in this description to describe the area printed in each step as a square, although it is to be understood that this term includes rectangular areas. Because the wafer is circular and the areas exposed by each step are square, there will be a width around the periphery (edge) of the wafer that, if printed, would yield incomplete squares that would be useless as chips. Additionally, there is a region around the wafer edge that is also useless because of a high density there of various forms of defects.
- printing equipment now available typically includes provision for controlling the field exposure area of the step pattern or square by providing an exposure tool that controls the size of the area printed movable blades that can be adjusted to set the effective field exposure area of the printing reticle just to that needed for the square being printed. This setting remains fixed during the printing of a wafer.
- the present invention employs a patterning strategy that better copes with the wafer edge problem described by use of the extra exposure area available in such printing equipment.
- the basic strategy of the invention is to use the extra exposure field area generally available in step and repeat printing apparatus to print squares with enlarged patterned areas selectively near the wafer edge that extend into the useless wafer edge region that will not normally yield useful chips.
- an improvement in efficiency is achieved by controlling the blades positioned on the exposure tool of the printer to increase selectively the opening that determines the size of the field area being exposed.
- the exposure tool selectively is opened wider so that a wider area of the reticle is opened and extra fill pattern is also being printed to include normally non-useable wafer edge area.
- the present invention is directed to a method for the step and repeat printing of squares on a circular semiconductive wafer that comprises the step of adjusting the exposure tool used to control the field exposure area of each square printed to add extra exposure field area to the regular field area of the square selectively at squares exposed adjacent to an edge of the wafer, whereby there is ameliorated area non-uniformity effects in later processing steps.
- the invention is a step-and-repeat printing system that uses a printer with an exposure tool whose setting can be adjusted in the course of printing a product pattern on a wafer. This permits printing extra area of a reticle that is appropriately patterned. This extra pattern is printed in areas of the wafer where such printing for later processing can ameliorate the edge effect in later processing.
- FIG. 1 will be helpful in explaining the wafer edge effect that the invention seeks to minimize
- FIG. 2 shows a typical reticle for use in printing a desired exposure product pattern on a wafer
- FIG. 3 shows an example of a reticle including the product pattern and an extra region of fill pattern for use selectively when printing squares on a die area that is close to a wafer edge, to extend the field area exposed into the surplus edge area of the wafer thereby to overcome the edge effect in later processing and to make such squares useful without the need for printing non-functional squares.
- FIG. 1 shows a circular wafer 10 , typically a slice of monocrystalline silicon about 8 inches in diameter, over which are shown printed a series of squares 12 corresponding to the chips to be diced from the wafer 10 .
- a circular wafer 10 typically a slice of monocrystalline silicon about 8 inches in diameter
- squares 12 corresponding to the chips to be diced from the wafer 10 .
- there is a surplus edge region of the wafer 10 that cannot be used for chips represented by that included within the dashed line 14 .
- Squares that extend beyond the dashed line 14 are also not useable.
- the invention involves using the area outside the fully printed squares and within the dashed line 14 to reduce the non-uniformity large area effect
- FIG. 2 shows a typical reticle 20 for use in a conventional step-and-repeat printer used for patterning a standard all-functional square pattern.
- the reticle typically includes a frame 21 that is used to support the patterned mask 22 that typically is of a size to pattern an area corresponding to a single die into which the wafer will be diced after most of the wafer scale processing is done.
- the reticle will be used with an exposure tool that comprises a set of blades that are adjusted to expose as much of the reticle as is needed for the size of the area being pointed. Generally this setting of the blades is kept fixed for the printing of the entire wafer.
- FIG. 3 shows a reticle 30 modified for use in the method of the invention.
- It includes a frame 31 that is used to support a patterned mask that includes a main section 32 and two auxiliary sections 34 A and 34 B that advantageously are spaced from the main section by narrow corridors 35 A and 35 B.
- the main section 32 corresponds to the area of a fully functional square that is to be printed in regions free of any edge effects, and when such squares are being printed, the blades of the exposure tool are set appropriately.
- the extra section is patterned much in the manner of the main section but will be used to print non-functional edge regions.
- the patterned areas of the reticle are shown cross-hatched. When the edges of the wafer are being printed, the setting of the exposure tool is increased to permit printing of these extra areas.
- the narrow unpatterned corridors advantageously are used as guides to facilitate the dicing of the wafer and may sometimes be unnecessary.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Cold Cathode And The Manufacture (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Description
- This invention relates to the manufacture of integrated circuit devices, and more particularly, to the manner in which patterns are printed on a semiconductive wafer to define how the wafer will eventually be diced to provide the individual chips in which the integrated circuits are formed.
- In the manufacture of integrated circuit devices, it is customary to do most of the processing of the devices on a wafer scale in a large wafer, typically many inches in diameter, and after such processing to dice the wafer into individual chips, each typically a square or rectangle in shape and a fraction of an inch on a side, for completion of the final steps of the processing, such as the provision of terminal connections and packaging.
- Basic to the processing, is the use of a step and repeat printer to print, in a layer of photoresist, the appropriate patterns of the various photoresist masks that are used to localize the effect of the many processing steps.
- Generally the shape of the wafer being processed is circular, while the shape of the chips after dicing is essentially square or rectangular. Accordingly the area generally printed in each step generally is either a square or a rectangle. It will be convenient in this description to describe the area printed in each step as a square, although it is to be understood that this term includes rectangular areas. Because the wafer is circular and the areas exposed by each step are square, there will be a width around the periphery (edge) of the wafer that, if printed, would yield incomplete squares that would be useless as chips. Additionally, there is a region around the wafer edge that is also useless because of a high density there of various forms of defects.
- Moreover, presently in the manufacture of state of the art semiconductive devices there are numerous processes, such as electrochemical chemical polishing and some etching, that depend on substantial uniformity over large areas to provide uniform results over the area processed. With such processes, there tends to be a non-uniformity area effect that causes a difference in results with respect to complete squares close to the wafer periphery because of the discontinuity such periphery provides.
- To counter these various edge effects, the step and repeat process is often extended to print squares that extend beyond the area free of such effects, even though it is known that these squares will not provide functional chips. Printing these non-functional squares extends the overall exposure time for printing of a wafer and so decreases the throughput of a given exposure machine. Because of the high cost of the exposure machines, this can be a significant extra expense factor in the manufacture of integrated circuits.
- It is a fact that many integrated circuit devices do not utilize the full exposure field of the equipment available. In particular some scanning equipment, such as deep ultra violet printers, offer large exposure fields for printing chip squares that often cannot be fully used because the final product made has to fit closely the exposure field of tools, used for other processes in the manufacture, that have much smaller exposure fields.
- Because of this, printing equipment now available typically includes provision for controlling the field exposure area of the step pattern or square by providing an exposure tool that controls the size of the area printed movable blades that can be adjusted to set the effective field exposure area of the printing reticle just to that needed for the square being printed. This setting remains fixed during the printing of a wafer.
- The present invention employs a patterning strategy that better copes with the wafer edge problem described by use of the extra exposure area available in such printing equipment.
- The basic strategy of the invention is to use the extra exposure field area generally available in step and repeat printing apparatus to print squares with enlarged patterned areas selectively near the wafer edge that extend into the useless wafer edge region that will not normally yield useful chips. In particular, an improvement in efficiency is achieved by controlling the blades positioned on the exposure tool of the printer to increase selectively the opening that determines the size of the field area being exposed. When there is printed a square in a region of the wafer that normally would be useless because of the edge effects, the exposure tool selectively is opened wider so that a wider area of the reticle is opened and extra fill pattern is also being printed to include normally non-useable wafer edge area. The inclusion of such enlarged patterned area can be expected to reduce the non-uniformity area edge effect in subsequent vulnerable processing steps and improve the yield of useful chips. Squares of the smaller regular product pattern are printed in wafer regions free of the edge effect. As a result, in the case of a printer, although the printing time of such enlarged edge squares is slightly increased because of the extra area being exposed, this extra time should be much less than would have been required to print and process squares that included non-functional edge areas, as has been done in the past, to avoid the non-uniformity edge effect. The extra area included in the enlarged squares along the wafer edge is removed when the wafer is finally diced.
- Viewed from one aspect, the present invention is directed to a method for the step and repeat printing of squares on a circular semiconductive wafer that comprises the step of adjusting the exposure tool used to control the field exposure area of each square printed to add extra exposure field area to the regular field area of the square selectively at squares exposed adjacent to an edge of the wafer, whereby there is ameliorated area non-uniformity effects in later processing steps.
- Viewed from another aspect, the invention is a step-and-repeat printing system that uses a printer with an exposure tool whose setting can be adjusted in the course of printing a product pattern on a wafer. This permits printing extra area of a reticle that is appropriately patterned. This extra pattern is printed in areas of the wafer where such printing for later processing can ameliorate the edge effect in later processing.
- The invention will be better understood from the following more detailed description taken with the drawing.
- FIG. 1 will be helpful in explaining the wafer edge effect that the invention seeks to minimize;
- FIG. 2 shows a typical reticle for use in printing a desired exposure product pattern on a wafer; and
- FIG. 3 shows an example of a reticle including the product pattern and an extra region of fill pattern for use selectively when printing squares on a die area that is close to a wafer edge, to extend the field area exposed into the surplus edge area of the wafer thereby to overcome the edge effect in later processing and to make such squares useful without the need for printing non-functional squares.
- FIG. 1 shows a
circular wafer 10, typically a slice of monocrystalline silicon about 8 inches in diameter, over which are shown printed a series ofsquares 12 corresponding to the chips to be diced from thewafer 10. As seen, there are some incomplete squares that extend beyond the edge of thewafer 10 and so are non-functional. Additionally, there is a surplus edge region of thewafer 10 that cannot be used for chips, represented by that included within thedashed line 14. Squares that extend beyond thedashed line 14 are also not useable. In addition, there are also some squares that are wholly within thedashed line 14 but sufficiently close to the edge that they ordinarily would not be useable because of the non-uniformity area effects discussed above. The invention involves using the area outside the fully printed squares and within thedashed line 14 to reduce the non-uniformity large area effect on such chip. - FIG. 2 shows a
typical reticle 20 for use in a conventional step-and-repeat printer used for patterning a standard all-functional square pattern. The reticle typically includes aframe 21 that is used to support thepatterned mask 22 that typically is of a size to pattern an area corresponding to a single die into which the wafer will be diced after most of the wafer scale processing is done. Generally the reticle will be used with an exposure tool that comprises a set of blades that are adjusted to expose as much of the reticle as is needed for the size of the area being pointed. Generally this setting of the blades is kept fixed for the printing of the entire wafer. - FIG. 3 shows a
reticle 30 modified for use in the method of the invention. - It includes a
frame 31 that is used to support a patterned mask that includes amain section 32 and twoauxiliary sections 34A and 34B that advantageously are spaced from the main section by 35A and 35B. Thenarrow corridors main section 32 corresponds to the area of a fully functional square that is to be printed in regions free of any edge effects, and when such squares are being printed, the blades of the exposure tool are set appropriately. The extra section is patterned much in the manner of the main section but will be used to print non-functional edge regions. The patterned areas of the reticle are shown cross-hatched. When the edges of the wafer are being printed, the setting of the exposure tool is increased to permit printing of these extra areas. The narrow unpatterned corridors advantageously are used as guides to facilitate the dicing of the wafer and may sometimes be unnecessary. - In some instances, it may be advantageous to provide extra fill sections along all four sides rather than two sides as shown. The exposure tool would then need to be modified appropriately. A software program would be used to change the blade settings appropriately.
- It should be noted that there should be distinguished the situation where there may be printed on the periphery of the wafer patterns that are useful for alignment or testing proposes.
- By this expediment, it becomes unnecessary to provide extra unusable squares to pattern non-functional areas to compensate for the non-uniformity area effect described. It is sufficient merely to use selectively larger squares when patterning squares at the wafer edge to overcome the non-uniformity area effect.
- It is to be understood that the specific embodiment described is merely illustrative of the general principles. For example the invention should be useable with wafer shapes that are non circular. Similarly c pattern printed could have various shaped, and so the term “square” to denote the pattern area printed in each step is intended to be independent of the shape of the area being printed in each step.
Claims (6)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/302,392 US6270947B2 (en) | 1999-04-30 | 1999-04-30 | Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices |
| EP00106650A EP1048984A3 (en) | 1999-04-30 | 2000-03-29 | Method and apparatus for reducing non-uniformities in the manufacture of semiconductive devices |
| KR1020000022871A KR20010014845A (en) | 1999-04-30 | 2000-04-28 | Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductive devices |
| TW089108166A TW449801B (en) | 1999-04-30 | 2000-04-28 | Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductive devices |
| CN00108237A CN1280384A (en) | 1999-04-30 | 2000-04-30 | Method and apparatus for reducing non-uniform area effects in semiconductor device fabrication |
| JP2000132555A JP2000353660A (en) | 1999-04-30 | 2000-05-01 | Manufacture of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/302,392 US6270947B2 (en) | 1999-04-30 | 1999-04-30 | Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| US20010003033A1 true US20010003033A1 (en) | 2001-06-07 |
| US6270947B2 US6270947B2 (en) | 2001-08-07 |
Family
ID=23167560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/302,392 Expired - Fee Related US6270947B2 (en) | 1999-04-30 | 1999-04-30 | Method and apparatus for reducing non-uniformity area effects in the manufacture of semiconductor devices |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6270947B2 (en) |
| EP (1) | EP1048984A3 (en) |
| JP (1) | JP2000353660A (en) |
| KR (1) | KR20010014845A (en) |
| CN (1) | CN1280384A (en) |
| TW (1) | TW449801B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046213A1 (en) * | 2004-08-30 | 2006-03-02 | Barber Duane B | Method for optimizing wafer edge patterning |
| US20120162622A1 (en) * | 2010-12-23 | 2012-06-28 | Alejandro Varela | Field extension to reduce non-yielding exposures of wafer |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4481561B2 (en) * | 2002-11-06 | 2010-06-16 | 川崎マイクロエレクトロニクス株式会社 | Mask for semiconductor devices |
| EP1860506B1 (en) * | 2003-10-16 | 2009-04-08 | ASML Netherlands B.V. | Device manufacturing method |
| KR100530499B1 (en) * | 2003-12-26 | 2005-11-22 | 삼성전자주식회사 | Exposure method and reticle, reticle assembly and exposure apparatus for performing the same |
| JP2006278820A (en) * | 2005-03-30 | 2006-10-12 | Nikon Corp | Exposure method and apparatus |
| JP2006310376A (en) * | 2005-04-26 | 2006-11-09 | Renesas Technology Corp | Method of manufacturing semiconductor integrated circuit device |
| JP2009088549A (en) * | 2008-12-01 | 2009-04-23 | Kawasaki Microelectronics Kk | Exposure method |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1583692A (en) * | 1968-02-16 | 1969-11-28 | ||
| JPS55129333A (en) * | 1979-03-28 | 1980-10-07 | Hitachi Ltd | Scale-down projection aligner and mask used for this |
| DE3485022D1 (en) * | 1983-12-26 | 1991-10-10 | Hitachi Ltd | EXPOSURE DEVICE AND METHOD FOR ALIGNING A MASK WITH A WORKPIECE. |
| US5545498A (en) * | 1990-07-26 | 1996-08-13 | Seiko Epson Corporation | Method of producing semiconductor device and photomask therefor |
| US5705299A (en) * | 1992-12-16 | 1998-01-06 | Texas Instruments Incorporated | Large die photolithography |
| EP0709740A1 (en) * | 1994-09-30 | 1996-05-01 | Texas Instruments Incorporated | Integrated circuit and method of making the same |
| JPH0950951A (en) * | 1995-08-04 | 1997-02-18 | Nikon Corp | Lithographic method and lithographic apparatus |
| JP3689949B2 (en) * | 1995-12-19 | 2005-08-31 | 株式会社ニコン | Projection exposure apparatus and pattern forming method using the projection exposure apparatus |
| JPH11354421A (en) * | 1998-06-03 | 1999-12-24 | Nikon Corp | Charged particle beam exposure system |
-
1999
- 1999-04-30 US US09/302,392 patent/US6270947B2/en not_active Expired - Fee Related
-
2000
- 2000-03-29 EP EP00106650A patent/EP1048984A3/en not_active Withdrawn
- 2000-04-28 TW TW089108166A patent/TW449801B/en not_active IP Right Cessation
- 2000-04-28 KR KR1020000022871A patent/KR20010014845A/en not_active Withdrawn
- 2000-04-30 CN CN00108237A patent/CN1280384A/en active Pending
- 2000-05-01 JP JP2000132555A patent/JP2000353660A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060046213A1 (en) * | 2004-08-30 | 2006-03-02 | Barber Duane B | Method for optimizing wafer edge patterning |
| US8685633B2 (en) * | 2004-08-30 | 2014-04-01 | Lsi Corporation | Method for optimizing wafer edge patterning |
| US20120162622A1 (en) * | 2010-12-23 | 2012-06-28 | Alejandro Varela | Field extension to reduce non-yielding exposures of wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1048984A2 (en) | 2000-11-02 |
| US6270947B2 (en) | 2001-08-07 |
| JP2000353660A (en) | 2000-12-19 |
| CN1280384A (en) | 2001-01-17 |
| TW449801B (en) | 2001-08-11 |
| EP1048984A3 (en) | 2004-05-19 |
| KR20010014845A (en) | 2001-02-26 |
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