[go: up one dir, main page]

US10147697B1 - Bond pad structure for semiconductor device packaging - Google Patents

Bond pad structure for semiconductor device packaging Download PDF

Info

Publication number
US10147697B1
US10147697B1 US15/843,615 US201715843615A US10147697B1 US 10147697 B1 US10147697 B1 US 10147697B1 US 201715843615 A US201715843615 A US 201715843615A US 10147697 B1 US10147697 B1 US 10147697B1
Authority
US
United States
Prior art keywords
bond
top surface
copper
layer
leadframe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/843,615
Inventor
Rama I. Hegde
Varughese Mathew
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Priority to US15/843,615 priority Critical patent/US10147697B1/en
Assigned to NXP USA, INC. reassignment NXP USA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEGDE, RAMA I., MATHEW, VARUGHESE
Application granted granted Critical
Publication of US10147697B1 publication Critical patent/US10147697B1/en
Priority to EP18211305.0A priority patent/EP3499565A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10252—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15717—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400 C and less than 950 C
    • H01L2924/15724—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/1576—Iron [Fe] as principal constituent

Definitions

  • This disclosure relates generally to semiconductor devices, and more specifically, to bond pad structure and formation for semiconductor device packaging.
  • Semiconductor devices are often found in a large spectrum of electronic products—from sewing machines to washing machines, from automobiles to cellular telephones, and so on. Such semiconductor devices generally include an integrated circuit die which communicates with the other devices outside of a package by way of bond wires. As technology progresses, semiconductor manufacturing continues to seek ways to reduce costs and improve reliability in these semiconductor devices.
  • FIG. 1 illustrates, in simplified cross-sectional view, an exemplary semiconductor device formed in accordance with an embodiment of the present invention.
  • FIG. 2 illustrates, in simplified cross-sectional view, a more detailed bond pad of exemplary semiconductor device formed in accordance with embodiment of the present invention.
  • FIG. 3 illustrates, in simplified cross-sectional view, a more detailed bond pad of exemplary semiconductor device formed in accordance with another embodiment of the present invention.
  • FIG. 4 illustrates, in simplified cross-sectional view, a more detailed bond terminal of exemplary semiconductor device formed in accordance with embodiment of the present invention.
  • FIG. 5 illustrates, in simplified cross-sectional view, a more detailed bond terminal of exemplary semiconductor device formed in accordance with another embodiment of the present invention.
  • FIG. 6 through FIG. 8 illustrates, in simplified surface schematic views, various grain orientations in accordance with an embodiment of the present invention.
  • a bond pad structure and method of forming the same By forming a top surface layer of copper having a ⁇ 111> grain orientation (Cu ⁇ 111>) on a bond pad, a copper bond wire can be attached without additional processing steps. Copper offers superior conductivity characteristics with modest costs when compared with other choices for pad metals and bond wires.
  • the Cu ⁇ 111> top surface layer may be formed by deposition or plating.
  • the Cu ⁇ 111> top surface layer has minimal oxide growth due to the grain density and allows for direct bonding with a copper bond wire. By directly attaching copper bond wires on Cu ⁇ 111> bond pads, intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
  • FIG. 1 illustrates, in simplified cross-sectional view, an exemplary semiconductor device 100 at a stage of manufacture in accordance with an embodiment of the present invention.
  • exemplary semiconductor device 100 includes a leadframe and a semiconductor die 106 .
  • the leadframe includes a flag 102 suitable for attachment of the semiconductor die 106 , and plurality of bond terminals 104 .
  • the leadframe may be formed of any suitable electrically conductive material, such as aluminum, copper, silver, nickel, or iron, or alloys including one or more of these materials, for example.
  • the conductive metal may be bare, partially plated, or plated with another metal or an alloy such as iron/nickel alloy, silver, gold, copper, or the like.
  • the leadframe is formed from a base metal such as copper and bond terminals 104 include a top surface copper layer formed on the base metal where the top surface copper layer includes copper (Cu) ⁇ 111>.
  • the term Cu ⁇ 111> refers to copper having ⁇ 111> grain orientation.
  • the leadframe may be formed as conductive traces on a printed circuit board or a substrate (e.g., ceramic or silicon).
  • the flag 102 may be any shape, size, or configuration suitable for an attached semiconductor die.
  • the flag 102 may be characterized as a downset flag where the plane of the flag 102 is below the plane of the plurality of bond terminals 104 .
  • the plurality of bond terminals 104 couple electrical signals between locations at the outside of a finished semiconductor device package and locations within the package such as bond pads on the semiconductor die 106 .
  • the semiconductor die 106 is attached to the flag 102 with an adhesive 108 .
  • the adhesive may be a solder alloy, an epoxy, or any suitable die-attach material such as a die-attach film, for example.
  • semiconductor die 106 may be attached to the flag 102 by way of a eutectic bonding process or sintering process.
  • the semiconductor die 106 includes a plurality of bond pads 110 located at the top major surface of the die.
  • the bond pads 110 may be formed during multiple processing steps. For example, bond pads 110 may be formed having a first portion formed from a top interconnect or metallization layer, and a second portion formed from a subsequent metal deposition or plating as a top surface layer suitable for bond wire attachment.
  • the first portion is formed from a copper or copper alloy interconnect layer and the second portion is formed from a copper deposition or plating as a top surface layer of Cu ⁇ 111>.
  • Semiconductor die 106 may be formed from any suitable semiconductor material such as silicon, germanium, gallium arsenide, and the like. Semiconductor die 106 may include any or combination of digital circuits, analog circuits, memory, processor, MEMS, sensors, and the like.
  • Bond wires 112 electrically couple bond pads 110 on the semiconductor die 106 to the plurality of bond terminals 104 of the leadframe.
  • the bond wires 112 may be formed from a metal comprising copper or copper alloys.
  • the bond wires 112 may be attached to the bond pads 110 of the semiconductor die 106 and the leadframe bond terminals 104 with either ball bonds or wedge bonds or a combination of ball bonds and wedge bonds.
  • ball bonds may be used to attach a first end of bond wires 112 to bond pads 110 of the semiconductor die 106 and wedge bonds may be used to attach the opposite ends of bond wires 112 to the bond terminals 104 of the leadframe.
  • FIG. 2 illustrates, in simplified cross-sectional view, a more detailed representation of wire bond region 114 of exemplary semiconductor device 100 formed in accordance with embodiment of the present invention.
  • Wire bond region 114 includes bond wire 112 bonded at a top surface layer 204 of bond pad 110 .
  • Top surface layer 204 is formed on a top interconnect metal layer portion 202 of semiconductor die 106 .
  • the top interconnect layer is characterized as the upper-most, or last interconnect layer of semiconductor die 106 and may generally be connected to other circuitry or other interconnect layers.
  • the top interconnect layer is formed from a copper or copper alloy material.
  • top surface Cu ⁇ 111> is deposited or plated as a top surface layer ( 204 ) on the top interconnect layer portion 202 .
  • top surface Cu ⁇ 111> layer 204 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values.
  • top surface layer 204 is formed to have a concentration of 60% or greater of Cu ⁇ 111>.
  • Bond wire 112 is formed from a copper or copper alloy material. In this embodiment, bond wire 112 is formed to have a concentration of 60% or greater of copper. Because the top surface layer 204 of bond pad 110 is formed from Cu ⁇ 111>, the top surface of layer 204 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire 112 on (copper) bond pad 110 can be accomplished without additional processing steps.
  • a significant advantage having copper bond wires bonded directly on copper bond pads is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
  • FIG. 3 illustrates, in simplified cross-sectional view, a more detailed representation of wire bond region 114 of exemplary semiconductor device 100 formed in accordance with another embodiment of the present invention.
  • wire bond region 114 includes bond wire 112 bonded at a top surface layer 304 of bond pad 110 .
  • a thin seed layer 302 of Cu ⁇ 111> is deposited at the top interconnect layer portion 202 .
  • a subsequent plating process with copper forms top surface layer 304 as a Cu ⁇ 111> layer.
  • top surface Cu ⁇ 111> layer 304 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values.
  • top surface layer 304 is formed to have a concentration of 60% or greater of Cu ⁇ 111>.
  • the top interconnect layer is characterized as the upper-most or last interconnect layer of semiconductor die 106 and may generally be used to interconnect other circuitry.
  • the top interconnect layer is formed from a copper or copper alloy material.
  • bond wire 112 is formed from a copper or copper alloy material, and formed to have a concentration of 60% or greater of copper. Because the top surface layer 304 of bond pad 110 is formed from Cu ⁇ 111>, the top surface of layer 304 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire 112 on (copper) bond pad 110 can be accomplished without additional processing steps.
  • FIG. 4 illustrates, in simplified cross-sectional view, a more detailed representation of a bond terminal 104 of exemplary semiconductor device 100 formed in accordance with embodiment of the present invention.
  • Bond terminal 104 includes a surface layer suitable for attachment of a bond wire.
  • a top surface layer 404 of bond terminal 104 is formed on a base metal layer portion 402 of the leadframe.
  • the base metal layer portion 402 is formed from a copper or copper alloy material. In other embodiments, base metal layer portion 402 may be formed from other metals or alloys.
  • Cu ⁇ 111> is deposited as a top surface layer ( 404 ) on the top base metal layer portion 402 .
  • top surface Cu ⁇ 111> layer 404 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values. In this embodiment, top surface layer 404 is formed to have a concentration of 60% or greater of Cu ⁇ 111>. Because the top surface layer 404 of bond terminal 104 is formed from Cu ⁇ 111>, the top surface of layer 404 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire on (copper) bond terminal 104 can be accomplished without additional processing steps. A significant advantage having copper bond wires bonded directly on copper bond terminals is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
  • FIG. 5 illustrates, in simplified cross-sectional view, a more detailed representation of a bond terminal 104 of exemplary semiconductor device 100 formed in accordance with another embodiment of the present invention.
  • Bond terminal 104 includes a surface layer suitable for attachment of a bond wire.
  • a thin seed layer 502 of Cu ⁇ 111> is deposited on the base metal layer portion 402 of the leadframe.
  • a subsequent plating process with copper forms top surface layer 504 as a Cu ⁇ 111> layer.
  • top surface Cu ⁇ 111> layer 504 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values.
  • top surface layer 504 is formed to have a concentration of 60% or greater of Cu ⁇ 111>.
  • top surface layer 504 of bond terminal 104 is formed from Cu ⁇ 111>, the top surface of layer 504 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire on (copper) bond terminal 104 can be accomplished without additional processing steps.
  • FIG. 6 through FIG. 8 illustrates, in simplified surface schematic views, various grain orientations in accordance with an embodiment of the present invention.
  • FIG. 6 through FIG. 8 shows surface diagrams for copper having ⁇ 110>, ⁇ 100>, and ⁇ 111> grain orientations, respectively.
  • FIG. 6 illustrates, in simplified surface schematic view, a diagram of copper having ⁇ 110> grain orientation (Cu ⁇ 110>) in accordance with an embodiment of the present invention.
  • Cu ⁇ 110> as depicted in FIG. 6 includes the circular shapes 602 are representative of crystal or crystalline grains in the ⁇ 110> orientation.
  • Cu ⁇ 110> has the lowest density of a surface plane of copper as shown by the large void area 604 between grains.
  • Cu ⁇ 110> is deemed least stable and would generally form a significant amount of oxide when subjected to subsequent heat cycles.
  • FIG. 7 illustrates, in simplified surface schematic view, a diagram of copper having ⁇ 100> grain orientation (Cu ⁇ 100>) in accordance with an embodiment of the present invention.
  • Cu ⁇ 100> as depicted in FIG. 7 includes circular shapes 702 representative of crystalline grains formed in the ⁇ 100> orientation.
  • Cu ⁇ 110> has the next lowest density of a surface plane of copper as shown by the medium void area 704 between grains.
  • Cu ⁇ 100> is deemed more stable than Cu ⁇ 110> depicted in FIG. 6 , and would generally form a less significant amount of oxide when subjected to subsequent heat cycles.
  • FIG. 8 illustrates, in simplified surface schematic view, a diagram of copper having ⁇ 111> grain orientation (Cu ⁇ 111>) in accordance with an embodiment of the present invention.
  • Cu ⁇ 111> as depicted in FIG. 8 includes circular shapes 802 representative of crystalline grains formed in the ⁇ 111> orientation.
  • Cu ⁇ 111> has the highest density of a surface plane of copper as shown by the minimal void area 804 between grains.
  • Cu ⁇ 111> is deemed more stable than Cu ⁇ 100> depicted in FIG. 7 , and would generally form a very small or negligible amount of oxide when subjected to subsequent heat cycles.
  • Cu ⁇ 111> when formed on bonding surfaces provides a superior surface for attaching copper bond wires.
  • Another advantage having copper bond wires bonded directly on Cu ⁇ 111> surfaces is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
  • a device including a leadframe having a flag and a plurality of bond terminals; a semiconductor die attached to the leadframe at the flag; a bond pad formed on the semiconductor die, the bond pad having a top surface layer comprising copper having ⁇ 111> grain orientation (Cu ⁇ 111>); and a bond wire having a first end and a second end, the bond wire attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end.
  • the bond wire may include a 60% or higher concentration of copper.
  • the top surface layer including Cu ⁇ 111> may be formed on a top interconnect layer of the semiconductor die, the top interconnect layer including copper.
  • the top surface layer including Cu ⁇ 111> may be formed by depositing a Cu ⁇ 111> seed layer and electroplating with copper.
  • the top surface layer including Cu ⁇ 111> may have a thickness in a range of 0.2 microns to 0.6 microns.
  • the top surface layer including Cu ⁇ 111> may include a concentration of at least 60% Cu ⁇ 111>.
  • a top bonding surface of the one of the bond terminals in the plurality may include Cu ⁇ 111>, the top bonding surface formed on a base metal of the leadframe.
  • the top bonding surface of the one of the bond terminals in the plurality may be formed by depositing a Cu ⁇ 111> seed layer and electroplating with copper.
  • the top bonding surface of the one of the bond terminals in the plurality may include a concentration of at least 60% Cu ⁇ 111>.
  • a device including a leadframe comprising a flag and a bond terminal, a top surface of the bond terminal comprising copper having ⁇ 111> grain orientation (Cu ⁇ 111>); a semiconductor die attached to the leadframe at the flag; a bond pad formed on the semiconductor die, a top surface of the bond pad comprising Cu ⁇ 111>; and a bond wire comprising copper having a first end and a second end, the bond wire attached directly to the top surface of the bond pad with a ball bond at the first end and attached to the top surface of the bond terminal at the second end.
  • the bond wire may include a 60% or higher concentration of copper.
  • the top surface of the bond pad including Cu ⁇ 111> may be formed on a top interconnect layer of the semiconductor die, the top interconnect layer comprising copper.
  • the top surface of the bond pad including Cu ⁇ 111> may have a thickness in a range of 0.2 microns to 0.6 microns.
  • the top surface of the bond pad Cu ⁇ 111> may include a concentration of at least 60% Cu ⁇ 111>.
  • the top surface of the bond terminal including Cu ⁇ 111> may be formed on a base metal of the leadframe, the base metal comprising copper.
  • the top surface of the bond terminal including Cu ⁇ 111> may include a concentration of at least 60% Cu ⁇ 111>.
  • a method including forming an interconnect layer on a semiconductor die; depositing copper having ⁇ 111> grain orientation (Cu ⁇ 111>) on at least a portion of the interconnect layer to form a top surface of a bond pad; attaching the semiconductor die to a flag of a leadframe; attaching a first end of a bond wire comprising copper to the top surface of the bond pad; and attaching a second end of the bond wire to a bond terminal of the leadframe.
  • the top surface of the bond pad including Cu ⁇ 111> may have a thickness in a range of 0.2 microns to 0.6 microns.
  • the bond terminal may include forming a top surface layer of Cu ⁇ 111> on a base metal of the leadframe, the base metal comprising copper.
  • the top surface of the bond pad and the top surface layer of the bond terminal each may include a concentration of at least 60% Cu ⁇ 111>.
  • a bond pad structure and method of forming the same By forming a top surface layer of copper having a ⁇ 111> grain orientation (Cu ⁇ 111>) on a bond pad, a copper bond wire can be attached without additional processing steps. Copper offers superior conductivity characteristics with modest costs when compared with other choices for pad metals and bond wires.
  • the Cu ⁇ 111> top surface layer may be formed by deposition or plating.
  • the Cu ⁇ 111> top surface layer has minimal oxide growth due to the grain density and allows for direct bonding with a copper bond wire. By directly attaching copper bond wires on Cu ⁇ 111> bond pads, intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

A semiconductor device includes a leadframe having a flag and a plurality of bond terminals. A semiconductor die is attached to the leadframe at the flag. A bond pad is formed on the semiconductor die. A top surface layer of the bond pad includes copper having a predetermined grain orientation. A bond wire includes a first end and a second end. The bond wire is attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end.

Description

BACKGROUND Field
This disclosure relates generally to semiconductor devices, and more specifically, to bond pad structure and formation for semiconductor device packaging.
Related Art
Semiconductor devices are often found in a large spectrum of electronic products—from sewing machines to washing machines, from automobiles to cellular telephones, and so on. Such semiconductor devices generally include an integrated circuit die which communicates with the other devices outside of a package by way of bond wires. As technology progresses, semiconductor manufacturing continues to seek ways to reduce costs and improve reliability in these semiconductor devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
FIG. 1 illustrates, in simplified cross-sectional view, an exemplary semiconductor device formed in accordance with an embodiment of the present invention.
FIG. 2 illustrates, in simplified cross-sectional view, a more detailed bond pad of exemplary semiconductor device formed in accordance with embodiment of the present invention.
FIG. 3 illustrates, in simplified cross-sectional view, a more detailed bond pad of exemplary semiconductor device formed in accordance with another embodiment of the present invention.
FIG. 4 illustrates, in simplified cross-sectional view, a more detailed bond terminal of exemplary semiconductor device formed in accordance with embodiment of the present invention.
FIG. 5 illustrates, in simplified cross-sectional view, a more detailed bond terminal of exemplary semiconductor device formed in accordance with another embodiment of the present invention.
FIG. 6 through FIG. 8 illustrates, in simplified surface schematic views, various grain orientations in accordance with an embodiment of the present invention.
 DETAILED DESCRIPTION
Generally, there is provided, a bond pad structure and method of forming the same. By forming a top surface layer of copper having a <111> grain orientation (Cu <111>) on a bond pad, a copper bond wire can be attached without additional processing steps. Copper offers superior conductivity characteristics with modest costs when compared with other choices for pad metals and bond wires. The Cu <111> top surface layer may be formed by deposition or plating. The Cu <111> top surface layer has minimal oxide growth due to the grain density and allows for direct bonding with a copper bond wire. By directly attaching copper bond wires on Cu <111> bond pads, intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
FIG. 1 illustrates, in simplified cross-sectional view, an exemplary semiconductor device 100 at a stage of manufacture in accordance with an embodiment of the present invention. At this stage, exemplary semiconductor device 100 includes a leadframe and a semiconductor die 106. The leadframe includes a flag 102 suitable for attachment of the semiconductor die 106, and plurality of bond terminals 104. The leadframe may be formed of any suitable electrically conductive material, such as aluminum, copper, silver, nickel, or iron, or alloys including one or more of these materials, for example. The conductive metal may be bare, partially plated, or plated with another metal or an alloy such as iron/nickel alloy, silver, gold, copper, or the like. In this embodiment, the leadframe is formed from a base metal such as copper and bond terminals 104 include a top surface copper layer formed on the base metal where the top surface copper layer includes copper (Cu) <111>. As used herein, the term Cu <111> refers to copper having <111> grain orientation. In some embodiments, the leadframe may be formed as conductive traces on a printed circuit board or a substrate (e.g., ceramic or silicon).
The flag 102 may be any shape, size, or configuration suitable for an attached semiconductor die. In some embodiments, the flag 102 may be characterized as a downset flag where the plane of the flag 102 is below the plane of the plurality of bond terminals 104. The plurality of bond terminals 104 couple electrical signals between locations at the outside of a finished semiconductor device package and locations within the package such as bond pads on the semiconductor die 106.
The semiconductor die 106 is attached to the flag 102 with an adhesive 108. The adhesive may be a solder alloy, an epoxy, or any suitable die-attach material such as a die-attach film, for example. In some embodiments, semiconductor die 106 may be attached to the flag 102 by way of a eutectic bonding process or sintering process. The semiconductor die 106 includes a plurality of bond pads 110 located at the top major surface of the die. The bond pads 110 may be formed during multiple processing steps. For example, bond pads 110 may be formed having a first portion formed from a top interconnect or metallization layer, and a second portion formed from a subsequent metal deposition or plating as a top surface layer suitable for bond wire attachment. In this embodiment, the first portion is formed from a copper or copper alloy interconnect layer and the second portion is formed from a copper deposition or plating as a top surface layer of Cu <111>. Semiconductor die 106 may be formed from any suitable semiconductor material such as silicon, germanium, gallium arsenide, and the like. Semiconductor die 106 may include any or combination of digital circuits, analog circuits, memory, processor, MEMS, sensors, and the like.
Bond wires 112 electrically couple bond pads 110 on the semiconductor die 106 to the plurality of bond terminals 104 of the leadframe. The bond wires 112 may be formed from a metal comprising copper or copper alloys. The bond wires 112 may be attached to the bond pads 110 of the semiconductor die 106 and the leadframe bond terminals 104 with either ball bonds or wedge bonds or a combination of ball bonds and wedge bonds. For example, ball bonds may be used to attach a first end of bond wires 112 to bond pads 110 of the semiconductor die 106 and wedge bonds may be used to attach the opposite ends of bond wires 112 to the bond terminals 104 of the leadframe.
FIG. 2 illustrates, in simplified cross-sectional view, a more detailed representation of wire bond region 114 of exemplary semiconductor device 100 formed in accordance with embodiment of the present invention. Wire bond region 114 includes bond wire 112 bonded at a top surface layer 204 of bond pad 110. Top surface layer 204 is formed on a top interconnect metal layer portion 202 of semiconductor die 106. In this embodiment, the top interconnect layer is characterized as the upper-most, or last interconnect layer of semiconductor die 106 and may generally be connected to other circuitry or other interconnect layers. The top interconnect layer is formed from a copper or copper alloy material. To form bond pad 110, Cu <111> is deposited or plated as a top surface layer (204) on the top interconnect layer portion 202. In this embodiment, top surface Cu <111> layer 204 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values. In this embodiment, top surface layer 204 is formed to have a concentration of 60% or greater of Cu <111>. Bond wire 112 is formed from a copper or copper alloy material. In this embodiment, bond wire 112 is formed to have a concentration of 60% or greater of copper. Because the top surface layer 204 of bond pad 110 is formed from Cu <111>, the top surface of layer 204 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire 112 on (copper) bond pad 110 can be accomplished without additional processing steps. A significant advantage having copper bond wires bonded directly on copper bond pads is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
FIG. 3 illustrates, in simplified cross-sectional view, a more detailed representation of wire bond region 114 of exemplary semiconductor device 100 formed in accordance with another embodiment of the present invention. In this embodiment, wire bond region 114 includes bond wire 112 bonded at a top surface layer 304 of bond pad 110. Here, a thin seed layer 302 of Cu <111> is deposited at the top interconnect layer portion 202. A subsequent plating process with copper forms top surface layer 304 as a Cu <111> layer. In this embodiment, top surface Cu <111> layer 304 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values. In this embodiment, top surface layer 304 is formed to have a concentration of 60% or greater of Cu <111>. In this embodiment, the top interconnect layer is characterized as the upper-most or last interconnect layer of semiconductor die 106 and may generally be used to interconnect other circuitry. The top interconnect layer is formed from a copper or copper alloy material. In this embodiment, bond wire 112 is formed from a copper or copper alloy material, and formed to have a concentration of 60% or greater of copper. Because the top surface layer 304 of bond pad 110 is formed from Cu <111>, the top surface of layer 304 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire 112 on (copper) bond pad 110 can be accomplished without additional processing steps.
FIG. 4 illustrates, in simplified cross-sectional view, a more detailed representation of a bond terminal 104 of exemplary semiconductor device 100 formed in accordance with embodiment of the present invention. Bond terminal 104 includes a surface layer suitable for attachment of a bond wire. In this embodiment, a top surface layer 404 of bond terminal 104 is formed on a base metal layer portion 402 of the leadframe. The base metal layer portion 402 is formed from a copper or copper alloy material. In other embodiments, base metal layer portion 402 may be formed from other metals or alloys. To form bond terminal 104, Cu <111> is deposited as a top surface layer (404) on the top base metal layer portion 402. In this embodiment, top surface Cu <111> layer 404 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values. In this embodiment, top surface layer 404 is formed to have a concentration of 60% or greater of Cu <111>. Because the top surface layer 404 of bond terminal 104 is formed from Cu <111>, the top surface of layer 404 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire on (copper) bond terminal 104 can be accomplished without additional processing steps. A significant advantage having copper bond wires bonded directly on copper bond terminals is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
FIG. 5 illustrates, in simplified cross-sectional view, a more detailed representation of a bond terminal 104 of exemplary semiconductor device 100 formed in accordance with another embodiment of the present invention. Bond terminal 104 includes a surface layer suitable for attachment of a bond wire. In this embodiment, a thin seed layer 502 of Cu <111> is deposited on the base metal layer portion 402 of the leadframe. A subsequent plating process with copper forms top surface layer 504 as a Cu <111> layer. In this embodiment, top surface Cu <111> layer 504 is formed to have a thickness value in the range of 0.2 to 0.6 microns. Other embodiments may have other thickness values. In this embodiment, top surface layer 504 is formed to have a concentration of 60% or greater of Cu <111>. Because the top surface layer 504 of bond terminal 104 is formed from Cu <111>, the top surface of layer 504 is less susceptible to oxidation. Accordingly, direct bonding of (copper) bond wire on (copper) bond terminal 104 can be accomplished without additional processing steps.
FIG. 6 through FIG. 8 illustrates, in simplified surface schematic views, various grain orientations in accordance with an embodiment of the present invention. FIG. 6 through FIG. 8 shows surface diagrams for copper having <110>, <100>, and <111> grain orientations, respectively.
FIG. 6 illustrates, in simplified surface schematic view, a diagram of copper having <110> grain orientation (Cu <110>) in accordance with an embodiment of the present invention. Cu <110> as depicted in FIG. 6, includes the circular shapes 602 are representative of crystal or crystalline grains in the <110> orientation. Among the grain orientations depicted in FIG. 6 through FIG. 8, Cu <110> has the lowest density of a surface plane of copper as shown by the large void area 604 between grains. Cu <110> is deemed least stable and would generally form a significant amount of oxide when subjected to subsequent heat cycles.
FIG. 7 illustrates, in simplified surface schematic view, a diagram of copper having <100> grain orientation (Cu <100>) in accordance with an embodiment of the present invention. Cu <100> as depicted in FIG. 7, includes circular shapes 702 representative of crystalline grains formed in the <100> orientation. Among the grain orientations depicted in FIG. 6 through FIG. 8, Cu <110> has the next lowest density of a surface plane of copper as shown by the medium void area 704 between grains. Cu <100> is deemed more stable than Cu <110> depicted in FIG. 6, and would generally form a less significant amount of oxide when subjected to subsequent heat cycles.
FIG. 8 illustrates, in simplified surface schematic view, a diagram of copper having <111> grain orientation (Cu <111>) in accordance with an embodiment of the present invention. Cu <111> as depicted in FIG. 8, includes circular shapes 802 representative of crystalline grains formed in the <111> orientation. Among the grain orientations depicted in FIG. 6 through FIG. 8, Cu <111> has the highest density of a surface plane of copper as shown by the minimal void area 804 between grains. Cu <111> is deemed more stable than Cu <100> depicted in FIG. 7, and would generally form a very small or negligible amount of oxide when subjected to subsequent heat cycles. As such, Cu <111> when formed on bonding surfaces, provides a superior surface for attaching copper bond wires. Another advantage having copper bond wires bonded directly on Cu <111> surfaces is that intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
Generally, there is provided, a device including a leadframe having a flag and a plurality of bond terminals; a semiconductor die attached to the leadframe at the flag; a bond pad formed on the semiconductor die, the bond pad having a top surface layer comprising copper having <111> grain orientation (Cu <111>); and a bond wire having a first end and a second end, the bond wire attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end. The bond wire may include a 60% or higher concentration of copper. The top surface layer including Cu <111> may be formed on a top interconnect layer of the semiconductor die, the top interconnect layer including copper. The top surface layer including Cu <111> may be formed by depositing a Cu <111> seed layer and electroplating with copper. The top surface layer including Cu <111> may have a thickness in a range of 0.2 microns to 0.6 microns. The top surface layer including Cu <111> may include a concentration of at least 60% Cu <111>. A top bonding surface of the one of the bond terminals in the plurality may include Cu <111>, the top bonding surface formed on a base metal of the leadframe. The top bonding surface of the one of the bond terminals in the plurality may be formed by depositing a Cu <111> seed layer and electroplating with copper. The top bonding surface of the one of the bond terminals in the plurality may include a concentration of at least 60% Cu <111>.
In another embodiment, there is provided, a device including a leadframe comprising a flag and a bond terminal, a top surface of the bond terminal comprising copper having <111> grain orientation (Cu <111>); a semiconductor die attached to the leadframe at the flag; a bond pad formed on the semiconductor die, a top surface of the bond pad comprising Cu <111>; and a bond wire comprising copper having a first end and a second end, the bond wire attached directly to the top surface of the bond pad with a ball bond at the first end and attached to the top surface of the bond terminal at the second end. The bond wire may include a 60% or higher concentration of copper. The top surface of the bond pad including Cu <111> may be formed on a top interconnect layer of the semiconductor die, the top interconnect layer comprising copper. The top surface of the bond pad including Cu <111> may have a thickness in a range of 0.2 microns to 0.6 microns. The top surface of the bond pad Cu <111> may include a concentration of at least 60% Cu <111>. The top surface of the bond terminal including Cu <111> may be formed on a base metal of the leadframe, the base metal comprising copper. The top surface of the bond terminal including Cu <111> may include a concentration of at least 60% Cu <111>.
In yet another embodiment, there is provided, a method including forming an interconnect layer on a semiconductor die; depositing copper having <111> grain orientation (Cu <111>) on at least a portion of the interconnect layer to form a top surface of a bond pad; attaching the semiconductor die to a flag of a leadframe; attaching a first end of a bond wire comprising copper to the top surface of the bond pad; and attaching a second end of the bond wire to a bond terminal of the leadframe. The top surface of the bond pad including Cu <111> may have a thickness in a range of 0.2 microns to 0.6 microns. The bond terminal may include forming a top surface layer of Cu <111> on a base metal of the leadframe, the base metal comprising copper. The top surface of the bond pad and the top surface layer of the bond terminal each may include a concentration of at least 60% Cu <111>.
By now it should be appreciated that there has been provided, a bond pad structure and method of forming the same. By forming a top surface layer of copper having a <111> grain orientation (Cu <111>) on a bond pad, a copper bond wire can be attached without additional processing steps. Copper offers superior conductivity characteristics with modest costs when compared with other choices for pad metals and bond wires. The Cu <111> top surface layer may be formed by deposition or plating. The Cu <111> top surface layer has minimal oxide growth due to the grain density and allows for direct bonding with a copper bond wire. By directly attaching copper bond wires on Cu <111> bond pads, intermetallic compound formation and associated corrosion susceptibility are virtually eliminated.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims (20)

The invention claimed is:
1. A device comprising:
a leadframe having a flag and a plurality of bond terminals;
a semiconductor die attached to the leadframe at the flag;
a bond pad formed on the semiconductor die, the bond pad having a top surface layer comprising copper having <111> grain orientation (Cu <111>); and
a bond wire having a first end and a second end, the bond wire attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end.
2. The device of claim 1, wherein the bond wire comprises a 60% or higher concentration of copper.
3. The device of claim 1, wherein the top surface layer comprising Cu <111> is formed on a top interconnect layer of the semiconductor die, the top interconnect layer comprising copper.
4. The device of claim 3, wherein the top surface layer comprising Cu <111> is formed by depositing a Cu <111> seed layer and electroplating with copper.
5. The device of claim 1, wherein the top surface layer comprising Cu <111> has a thickness in a range of 0.2 microns to 0.6 microns.
6. The device of claim 1, wherein the top surface layer comprising Cu <111> comprises a concentration of at least 60% Cu <111>.
7. The device of claim 1, wherein a top bonding surface of the one of the bond terminals in the plurality comprises Cu <111>, the top bonding surface formed on a base metal of the leadframe.
8. The device of claim 7, wherein the top bonding surface of the one of the bond terminals in the plurality is formed by depositing a Cu <111> seed layer and electroplating with copper.
9. The device of claim 7, wherein the top bonding surface of the one of the bond terminals in the plurality comprises a concentration of at least 60% Cu <111>.
10. A device comprising:
a leadframe comprising a flag and a bond terminal, a top surface of the bond terminal comprising copper having <111> grain orientation (Cu <111>);
a semiconductor die attached to the leadframe at the flag;
a bond pad formed on the semiconductor die, a top surface of the bond pad comprising Cu <111>; and
a bond wire comprising copper having a first end and a second end, the bond wire attached directly to the top surface of the bond pad with a ball bond at the first end and attached to the top surface of the bond terminal at the second end.
11. The device of claim 10, wherein the bond wire comprises a 60% or higher concentration of copper.
12. The device of claim 10, wherein the top surface of the bond pad comprising Cu <111> is formed on a top interconnect layer of the semiconductor die, the top interconnect layer comprising copper.
13. The device of claim 10, wherein the top surface of the bond pad comprising Cu <111> has a thickness in a range of 0.2 microns to 0.6 microns.
14. The device of claim 10, wherein the top surface of the bond pad Cu <111> comprises a concentration of at least 60% Cu <111>.
15. The device of claim 10, wherein the top surface of the bond terminal comprising Cu <111> is formed on a base metal of the leadframe, the base metal comprising copper.
16. The device of claim 10, wherein the top surface of the bond terminal comprising Cu <111> comprises a concentration of at least 60% Cu <111 >.
17. A method comprising:
forming an interconnect layer on a semiconductor die;
depositing copper having <111> grain orientation (Cu <111>) on at least a portion of the interconnect layer to form a top surface of a bond pad;
attaching the semiconductor die to a flag of a leadframe;
attaching a first end of a bond wire comprising copper to the top surface of the bond pad; and
attaching a second end of the bond wire to a bond terminal of the leadframe.
18. The method of claim 17, wherein the top surface of the bond pad comprising Cu <111> has a thickness in a range of 0.2 microns to 0.6 microns.
19. The method of claim 17, wherein the bond terminal comprises forming a top surface layer of Cu <111> on a base metal of the leadframe, the base metal comprising copper.
20. The method of claim 18, wherein the top surface of the bond pad and the top surface layer of the bond terminal each comprise a concentration of at least 60% Cu <111>.
US15/843,615 2017-12-15 2017-12-15 Bond pad structure for semiconductor device packaging Active US10147697B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/843,615 US10147697B1 (en) 2017-12-15 2017-12-15 Bond pad structure for semiconductor device packaging
EP18211305.0A EP3499565A1 (en) 2017-12-15 2018-12-10 Bond pad structure for semiconductor device packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/843,615 US10147697B1 (en) 2017-12-15 2017-12-15 Bond pad structure for semiconductor device packaging

Publications (1)

Publication Number Publication Date
US10147697B1 true US10147697B1 (en) 2018-12-04

Family

ID=64452172

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/843,615 Active US10147697B1 (en) 2017-12-15 2017-12-15 Bond pad structure for semiconductor device packaging

Country Status (2)

Country Link
US (1) US10147697B1 (en)
EP (1) EP3499565A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725171A (en) * 2019-03-22 2020-09-29 大口电材株式会社 lead frame
WO2025199109A1 (en) * 2024-03-21 2025-09-25 Wolfspeed, Inc. Power devices with multiple metal layer thicknesses

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316802A (en) 1992-02-20 1994-05-31 Nissin Electric Co., Ltd. Method of forming copper film on substrate
US6593643B1 (en) * 1999-04-08 2003-07-15 Shinko Electric Industries Co., Ltd. Semiconductor device lead frame
US7695605B2 (en) 2003-05-12 2010-04-13 Rohm And Haas Electronic Materials Llc Tin plating method
US20100139822A1 (en) 2008-12-08 2010-06-10 Weilin Gao Cu-Ti-based copper alloy sheet material and method of manufacturing same
EP2045344B1 (en) 2006-07-21 2012-05-23 Kabushiki Kaisha Kobe Seiko Sho Process for producing copper alloy sheets for electrical/electronic part
US8203221B2 (en) * 2008-09-01 2012-06-19 Hitachi, Ltd. Semiconductor device and method for manufacturing the same, and semiconductor sealing resin
US8319330B2 (en) * 2010-07-16 2012-11-27 Renesas Electronics Corporation Semiconductor package having exterior plating films formed over surfaces of outer leads
US20160351487A1 (en) * 2015-05-25 2016-12-01 Fuji Electronic Co., Ltd Semiconductor device and production method therefor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8432024B2 (en) * 2010-04-27 2013-04-30 Infineon Technologies Ag Integrated circuit including bond wire directly bonded to pad
US9468986B2 (en) * 2013-07-30 2016-10-18 GlobalFoundries, Inc. Methods of forming articles including metal structures having maximized bond adhesion and bond reliability

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5316802A (en) 1992-02-20 1994-05-31 Nissin Electric Co., Ltd. Method of forming copper film on substrate
US6593643B1 (en) * 1999-04-08 2003-07-15 Shinko Electric Industries Co., Ltd. Semiconductor device lead frame
US7695605B2 (en) 2003-05-12 2010-04-13 Rohm And Haas Electronic Materials Llc Tin plating method
EP2045344B1 (en) 2006-07-21 2012-05-23 Kabushiki Kaisha Kobe Seiko Sho Process for producing copper alloy sheets for electrical/electronic part
US8203221B2 (en) * 2008-09-01 2012-06-19 Hitachi, Ltd. Semiconductor device and method for manufacturing the same, and semiconductor sealing resin
US20100139822A1 (en) 2008-12-08 2010-06-10 Weilin Gao Cu-Ti-based copper alloy sheet material and method of manufacturing same
US8319330B2 (en) * 2010-07-16 2012-11-27 Renesas Electronics Corporation Semiconductor package having exterior plating films formed over surfaces of outer leads
US20160351487A1 (en) * 2015-05-25 2016-12-01 Fuji Electronic Co., Ltd Semiconductor device and production method therefor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Boo, J., "High-Rate deposition of copper thin films using newly designed high-power magnetron sputtering source"; Surface Coatings Technology 188-189 (2004) 721-727, Aug. 2004.
Kim, J., "Self-annealing effect of electrolessly deposited copper thin films based on Co(II)-ethylenediamine as a reducing agent"; http://www.electrochem.org/dl/ma/202/pdfs/0420.pdf; downloaded Dec. 5, 2017.
Mao, J., "The Influence of Pre-heat Treatment on Peeling Resistance of Oxide Film of Copper Alloy Lead Frames"; 2008 International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP 2008). IEEE 2008.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725171A (en) * 2019-03-22 2020-09-29 大口电材株式会社 lead frame
WO2025199109A1 (en) * 2024-03-21 2025-09-25 Wolfspeed, Inc. Power devices with multiple metal layer thicknesses

Also Published As

Publication number Publication date
EP3499565A1 (en) 2019-06-19

Similar Documents

Publication Publication Date Title
US10325876B2 (en) Surface finish for wirebonding
US6781243B1 (en) Leadless leadframe package substitute and stack package
US8188579B1 (en) Semiconductor device including leadframe having power bars and increased I/O
US9059185B2 (en) Copper leadframe finish for copper wire bonding
US7268415B2 (en) Semiconductor device having post-mold nickel/palladium/gold plated leads
US10763195B2 (en) Leadframe package using selectively pre-plated leadframe
KR101026586B1 (en) Semiconductor device comprising leadframe for improved moisture reliability and improved solderability of semiconductor device and manufacturing method thereof
CN101536183B (en) Lead frame strip, semiconductor device and method for manufacturing the lead frame
US10741415B2 (en) Thermosonically bonded connection for flip chip packages
US10147697B1 (en) Bond pad structure for semiconductor device packaging
US8703544B2 (en) Electronic component employing a layered frame
EP4086952A1 (en) Semiconductor device packaging leadframe assembly and method therefor
WO2007022399A2 (en) Semiconductor assembly and packaging for high current and low inductance
US20240105579A1 (en) Extendable inner lead for leaded package
CN1770440B (en) Semiconductor lead frame and electroplating method, semiconductor package with semiconductor lead frame
US20140367859A1 (en) Tin-based wirebond structures
US20120326304A1 (en) Externally Wire Bondable Chip Scale Package in a System-in-Package Module
KR102222146B1 (en) Low-Cost Semiconductor package with metal structure
US10366946B2 (en) Connection member with bulk body and electrically and thermally conductive coating
US20140231977A1 (en) Semiconductor packages with low stand-off interconnections between chips
US20240429137A1 (en) Dual leadframe semiconductor device and method therefor
US20250239462A1 (en) Immersion plating process for an integrated circuit
JP3346458B2 (en) Wiring board having semiconductor chip bonding leads and semiconductor device
JPS6129139A (en) Semiconductor device
JPH02174253A (en) Electronic parts package with rhenium layer at metal part

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4