TWM675356U - Electrical connection structure of chip package - Google Patents

Abstract

An electrical connection structure for a chip package includes a non-conductive dielectric substrate, a conductive layer, a transmitting chip, a receiving chip, and an isolation unit. The non-conductive dielectric substrate has a first surface and a second surface, and the conductive layer includes a first conductive line and a second conductive line isolated from each other. The transmitting chip and the receiving chip are respectively used to transmit and receive a signal and are coupled to the first conductive line and the second conductive line, respectively. The isolation unit includes a first electrode disposed on the first surface and coupled to the transmitting chip via the first conductive line, and a second electrode disposed on the second surface and coupled to the receiving chip via the second conductive line. The first electrode and the second electrode are disposed on the non-conductive dielectric substrate in a corresponding manner in a normal direction.

Description

Electrical connection structure of chip package

The present invention relates to an electrical connection structure for a semiconductor element, and in particular to an electrical connection structure for a chip package.

In power conversion systems and industrial control applications, to protect low-voltage control chips (such as microcontrollers, MCUs) from damage caused by high-voltage voltage or current surges, signal transmission devices with electrical isolation, called isolators, are often required. Common isolator types include optical, inductive, and capacitive isolators, which utilize the coupling effects of optical, magnetic, or electric fields, respectively, to achieve signal transmission in the absence of conduction.

Traditionally, most isolator components are manufactured using silicon-based processes and then packaged and integrated onto silicon-based interposers. However, these structures are not only bulky but also require additional processing for through-silicon vias (TSVs) and multiple redistribution layers (RDLs), making the overall process complex and costly. Furthermore, silicon-based interposers have limitations: silicon's high conductivity easily generates electromagnetic coupling and signal crosstalk, compromising signal integrity. Furthermore, the TSV process is complex, requiring steps such as insulation layer deposition and wafer thinning, contributing to the high overall cost.

Therefore, there is an urgent need for an isolator electrical connection structure that can simultaneously provide high electrical isolation capability, compact size, simplified manufacturing process, and reduced cost to meet the needs of modern power and control systems.

The main purpose of this novel is to solve the problems of the conventional isolator's electrical connection structure, which is complex, costly, and prone to signal crosstalk.

To achieve the aforementioned objectives, the present invention discloses an electrical connection structure for a chip package, comprising a non-conductive dielectric substrate, a conductive layer, a transmitter chip, a receiver chip, and an isolation unit. The non-conductive dielectric substrate has a first surface and a second surface located on opposite sides. The conductive layer is disposed on the non-conductive dielectric substrate and includes a first conductive line and a second conductive line isolated from each other. The transmitter chip and the receiver chip are respectively used to transmit and receive a signal and are coupled to the first conductive line and the second conductive line, respectively. The isolation unit includes a first electrode disposed on the first surface and coupled to the transmitter chip via the first conductive line, and a second electrode disposed on the second surface and coupled to the receiver chip via the second conductive line. The first electrode and the second electrode are disposed on the non-conductive dielectric substrate in a corresponding direction in a normal direction. The non-conductive dielectric substrate electrically isolates the first electrode and the second electrode from each other (Galvanic isolation), thereby transmitting the signal without conductive coupling.

The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. Unless the context indicates otherwise, the singular forms "a", "an" and "the" used herein may also include plural forms.

Directional terms used herein, such as up, down, left, right, front, back, and their derivatives or synonyms, refer to the orientation of elements in the drawings and are not intended to limit the present invention unless the context clearly indicates otherwise.

This invention discloses an electrical connection structure for a package. Specifically, the electrical connection structure relates to an integrated circuit package structure for signal transmission with isolation functionality. More specifically, the structure integrates a transmitter chip and a receiver chip on a non-conductive medium (such as glass) substrate, and implements non-conductive signal transmission via capacitive or inductive coupling.

1 , which shows an electrical connection structure 100 according to a first embodiment of the present invention, including a non-conductive dielectric substrate 110 , a conductive layer 120 , an isolation unit 130 , a transmitter chip 140 , and a receiver chip 150 .

In the present invention, the manufacturing material of the non-conductive dielectric substrate 110 is selected from glass and is used as a glass substrate. In one example, a thickness t1 of the non-conductive dielectric substrate 110 is between 10μm and 30μm, preferably 20μm, and the non-conductive dielectric substrate 110 can withstand a voltage of 6000 volts. The glass substrate is selected from SiO2.

The non-conductive dielectric substrate 110 includes a first surface 111 and a second surface 112. The first surface 111 and the second surface 112 are disposed opposite each other. In one example, the first surface 111 can serve as the top surface of the non-conductive dielectric substrate 110, and the second surface 112 can serve as the bottom surface of the non-conductive dielectric substrate 110. In other examples, the first surface 111 and the second surface 112 can be configured in the opposite manner, with the first surface 111 serving as the bottom surface of the non-conductive dielectric substrate 110 and the second surface 112 serving as the top surface of the non-conductive dielectric substrate 110.

The non-conductive dielectric substrate 110 can be formed, but is not limited to, through laser or wet etching to form micro-holes, thinning, conductive structures, and other necessary features for package integration, such as chip placement areas, wiring configuration areas, and through-holes. In one example, the first surface 111 and the second surface 112 of the non-conductive dielectric substrate 110 are configured to form structures for arranging the wiring layer 120, the isolation unit 130, the transmitter chip 140, and the receiver chip 150.

The conductor layer 120 is configured to be arranged on the non-conductive medium substrate 110. The conductor layer 120 includes a first conductor 121 and a second conductor 122. The first conductor 121 and the second conductor 122 are arranged to be isolated from each other. In this example, the first conductor 121 has multiple electrical connection portions 121a, 121b, and 121c, and the electrical connection portions 121a, 121b, and 121c are coupled to the transmitting end chip 140. The second conductor 122 has multiple electrical connection portions 122a, 122b, and 122c, and the electrical connection portions 122a, 122b, and 122c are coupled to the receiving end chip 150. In one example, the conductor layer 120 is a redistribution layer (RDL), a metal layer, a through glass via (TGV), a solder ball, a copper pillar, a copper bump, or any combination thereof. For example, the electrical connection portions 121a, 121b, 121c of the first conductor 121 and the electrical connection portions 122a, 122b, 122c of the second conductor 122 can be a combination of copper pillars, copper bumps, and solder balls, respectively, and the electrical connection portions 121a, 121b, 121c, 122a, 122b, 122c are connected to the redistribution layer via the metal layer, through glass via, and redistribution layer disposed on the non-conductive dielectric substrate 110 to transmit different signals.

In the wire layer 120, the first wire 121 and the second wire 122 can independently carry different signals, power, ground, clock, etc. In other examples, the conductor layer 120 is not limited to having only the first conductor 121 and the second conductor 122. Other conductors may also be arranged in the metal layer or the redistribution layer, and the first conductor 121 and the second conductor 122 may form independent lines on the non-conductive medium substrate 110 based on a combination of the redistribution layer, the metal layer, the glass through-hole, the solder ball, the copper pillar, and the copper bump to perform power or signal transmission. The first conductor 121 and the second conductor 122 may independently execute or carry different signals, power, ground, clock, etc. on the same or different surfaces (such as the first surface 111 and the second surface 112) through the non-conductive property of the non-conductive medium substrate 110.

The isolation unit 130 is configured to have two isolated portions, one disposed on the first surface 111 and the other on the second surface 112 of the non-conductive dielectric substrate 110, and electrically isolated from each other by the non-conductive dielectric substrate 110 (Galvanic isolation). The isolation unit 130 includes a first electrode 131 and a second electrode 132. The first electrode 131 and the second electrode 132 are disposed on the first surface 111 and the second surface 112, respectively. The first electrode 131 and the second electrode 132 have opposing projected positions on the first surface 111 and the second surface 112. That is, in the figure, the first electrode 131 and the second electrode 132 are disposed on the non-conductive dielectric substrate 110 in a corresponding direction in a normal direction. The first electrode 131 is coupled to the electrical connection portion 121 a of the first wire 121 of the wire layer 120 , and the second electrode 132 is coupled to the electrical connection portion 122 a of the second wire 122 of the wire layer 120 .

The transmitter chip 140 is coupled to the first conductor 121 and connected to other circuits of the semiconductor device or external circuits via the electrical connections 121b and 121c. The receiver chip 150 is coupled to the second conductor 122 and connected to other circuits of the semiconductor device or external circuits via the electrical connections 122b and 122c. The first and second conductors 121 and 122 can be connected to external circuits via power supply pins, signal pins, clock pins, and ground pins, thereby implementing input and output functions such as signals, power, clocks, and ground. In one example, the electrical connections 121b, 121c, 122b, and 122c can be configured to connect to the same or different external circuits.

The transmitting chip 140 transmits a signal to the first electrode 131 via the electrical connection portion 121a of the first conductive line 121. The first electrode 131 and the second electrode 132 are electrically isolated from each other by the non-conductive dielectric substrate 110, enabling non-conductive coupling signal transmission. This allows the signal to be transmitted from the first electrode 131 to the second electrode 132 without causing signal crosstalk. The receiving chip 150 couples to the electrical connection portion 122a of the second conductive line 122 and receives the signal from the second electrode 132.

In this embodiment, the isolation unit 130 is a capacitive isolation unit. The first electrode 131 and the second electrode 132 are capacitors, respectively. An electric field coupling is generated between the first electrode 131 and the second electrode 132 to perform non-conductive coupling signal transmission or exchange. The electric field coupling is an AC coupling.

The transmitter chip 140 and the receiver chip 150 can be disposed together on either the first surface 111 or the second surface 112. In the first embodiment, the transmitter chip 140 and the receiver chip 150 are both disposed on the first surface 111 (as shown in FIG1 ). The first wire 121 is configured to couple the first electrode 131 to the transmitter chip 140 on the first surface 111. The second wire 122 is disposed as one or more electrical connection portions 122a (a combination of through-glass vias, copper pillars, copper bumps, and/or solder balls) penetrating between the first surface 111 and the second surface 112, thereby coupling the receiver chip 150 located on the first surface 111 with the second electrode 132 located on the second surface 112. It is understandable that the first wire 121 and the second wire 122 are not limited to being arranged on the first surface 111 or the second surface 112, but can be arranged on the entire structure of the non-conductive dielectric substrate 110 through three-dimensional packaging technology (such as redistribution wiring, through-glass vias, etc.).

FIG2 shows the electrical connection structure 100 according to the second embodiment of the present invention. The isolation unit 130 of the electrical connection structure 100 is also a capacitive isolation unit.

The non-conductive dielectric substrate 110 disclosed in the second embodiment may further include at least one supporting structure 113 extending outward from either the first surface 111 or the second surface 112. The supporting structure 113 has a thickness t2 ranging from 200 μm to 500 μm. The thickness of the non-conductive dielectric substrate 110 is preferably 300 μm. The thin region of the non-conductive dielectric substrate 110 (the region outside the support structure 113) serves as the application region of the isolation unit 130, while the thick region of the non-conductive dielectric substrate 110 (the support structure 113) serves as the region for routing and bearing the mechanical stress of the circuit. The support structure 113 is formed by subtractively processing an unprocessed substrate, such as laser lithography, etching, and thinning, to form the non-conductive dielectric substrate 110 with different thicknesses (such as thickness t1 and thickness t2). In this example, the support structure 113 extends downward from two sides of the second surface 112 that are relatively far from the isolation unit 130 . The support structure 113 has different configurations based on the design of the electrical connection structure 100 .

Referring to FIG. 3 , which illustrates a third embodiment of the present invention, the isolation unit 130 of the electrical connection structure 100 is also a capacitive isolation unit. In this embodiment, the transmitter chip 140 is disposed on the first surface 111 of the non-conductive dielectric substrate 110, and the receiver chip 150 is disposed on the second surface 112 of the non-conductive dielectric substrate 110. The first wire 121 is configured to couple to the transmitter chip 140 and the first electrode 131 on the first surface 111, and the second wire 122 is configured to couple to the receiver chip 150 and the second electrode 132 on the second surface 112.

4 , 5 , and 6 , which illustrate the electrical connection structure 100 according to the fourth, fifth, and sixth embodiments of the present invention, the isolation unit 130 is an inductive isolation unit in the fourth, fifth, and sixth embodiments.

The first electrode 131 and the second electrode 132 of the isolation unit 130 are each a spiral coil structure. The first wire 121 further includes an electrical connection portion 121d. That is, the first wire 121 has multiple electrical connection portions 121a, 121b, 121c, and 121d. The electrical connection portions 121a, 121b, 121c, and 121d are coupled to the transmitting end chip 140. The second wire 122 further includes an electrical connection portion 122d. That is, the second wire 122 has multiple electrical connection portions 122a, 122b, 122c, and 122d. The electrical connection portions 122a, 122b, 122c, and 122d are coupled to the receiving end chip 150. The electrical connections 121a and 121d are respectively coupled to a first end 131a and a second end 131b of the coil structure to form a first magnetic loop path. The electrical connections 122a and 122d are respectively coupled to a first end 132a and a second end 132b of the coil structure to form a second magnetic loop path. Magnetic field coupling is generated through the first and second magnetic loop paths to perform non-conductive coupling signal transmission or exchange.

FIG4 shows that the transmitter chip 140 and the receiver chip 150 are both disposed on the first surface 111 of the non-conductive dielectric substrate 110. The first conductive lines 121 and the second conductive lines 122 are copper pillars, copper bumps, solder balls, through-glass vias, redistribution wiring layers, or a combination thereof. The electrical connections 121 a, 121 b, 121 c, and 121 d couple the transmitter chip 140 to the first electrode 131, and the electrical connections 122 a, 122 b, 122 c, and 122 d couple the receiver chip 150 to the second electrode 132, thereby transmitting signals.

FIG5 shows an embodiment of the fourth embodiment with the support structure 113 added as an area for routing and bearing the mechanical stress of the circuit.

FIG6 shows that the transmitter chip 140 and the receiver chip 150 are disposed on the first surface 111 and the second surface 112, respectively, and are coupled to the first electrode 131 and the second electrode 132, respectively, through the first wire 121 and the second wire 122, which are copper pillars, copper bumps, solder balls, through-glass vias, redistribution wiring layers, or a combination thereof, to transmit signals.

Referring to FIG. 7 , during a packaging process, the electrical connection structure 100 may further be completely packaged by depositing packaging layers 200 and 300 on the first surface 111 and the second surface 112 of the non-conductive dielectric substrate 110, respectively, to protect the overall stability of the electrical connection structure 100. In one example, polyimide (PI) or other non-conductors may be used as the material for depositing the packaging layers 200 and 300. FIG. 7 illustrates the packaging layers 200 and 300 being deposited on the non-conductive dielectric substrate 110 of the second embodiment. However, the present invention is not limited thereto. The packaging layers 200 and 300 may similarly be deposited on the non-conductive dielectric substrate 110 disclosed in other embodiments.

In summary, the present invention uses the non-conductive dielectric substrate as the substrate of the electrical connection package structure to electrically isolate the first electrode and the second electrode of the isolation unit, thereby avoiding signal crosstalk during signal transmission and reducing production costs.

100: Electrical connection structure 110: Non-conductive dielectric substrate 111: First surface 112: Second surface 113: Support structure 120: Conductive layer 121: First conductor 121a, 121b, 121c, 121d: Electrical connection portion 122: Second conductor 122a, 122b, 122c, 122d: Electrical connection portion 130: Isolation unit 131: First electrode 131a: First end 131b: Second end 132: Second electrode 132a: First end 132b: Second end 140: Transmitter chip 150: Receiver chip 200, 300: Package layer t1, t2: Thickness

Figure 1 is a schematic diagram of the first embodiment of the present invention. Figure 2 is a schematic diagram of the second embodiment of the present invention. Figure 3 is a schematic diagram of the third embodiment of the present invention. Figure 4 is a schematic diagram of the fourth embodiment of the present invention. Figure 5 is a schematic diagram of the fifth embodiment of the present invention. Figure 6 is a schematic diagram of the sixth embodiment of the present invention. Figure 7 is a schematic diagram of the deposited packaging layer of the present invention.

100: Electrical connection structure

110: Non-conductive dielectric substrate

111: First Surface

112: Second Surface

120: Conductor layer

121: First Conductor

121a, 121b, 121c: Electrical connection parts

122: Second wire

122a, 122b, 122c: Electrical connection parts

130: Isolation Unit

131: First electrode

132: Second electrode

140: Transmitter chip

150: Receiver chip

t1: thickness

Claims (10)

An electrical connection structure of a chip package includes: a non-conductive dielectric substrate having a first surface and a second surface located on opposite sides; a conductive layer disposed on the non-conductive dielectric substrate and including a first conductive line and a second conductive line isolated from each other; a transmitting end chip and a receiving end chip, respectively used for transmitting and receiving a signal and coupled to the first conductive line and the second conductive line; and an isolation unit, including a conductive layer disposed on the non-conductive dielectric substrate and including a first conductive line and a second conductive line isolated from each other. A first electrode is disposed on the first surface and coupled to the transmitting chip via the first wire, and a second electrode is disposed on the second surface and coupled to the receiving chip via the second wire. The first electrode and the second electrode are disposed on the non-conductive dielectric substrate in a corresponding direction in a normal direction. The first electrode and the second electrode are electrically isolated from each other (Galvanic isolation) by the non-conductive dielectric substrate, and the signal is transmitted without conductive coupling. The electrical connection structure as described in claim 1, wherein the transmitting end chip and the receiving end chip are respectively arranged on the first surface and the second surface of the non-conductive medium substrate. The electrical connection structure as described in claim 1, wherein the transmitting end chip and the receiving end chip are arranged on either the first surface or the second surface of the non-conductive medium substrate. The electrical connection structure as described in claim 1, wherein the non-conductive dielectric substrate is a glass substrate with a thickness of 20 μm, and a withstand voltage of the glass substrate is 6000 volts. The electrical connection structure as described in claim 1, wherein the isolation unit is a capacitive isolation unit, and an electric field coupling is generated between the first electrode and the second electrode. The electrical connection structure as described in claim 5, wherein the electric field coupling is an AC coupling. The electrical connection structure as described in claim 1, wherein the isolation unit is an inductive isolation unit, and a magnetic field coupling is generated between the first electrode and the second electrode. The electrical connection structure as described in claim 7, wherein the first electrode and the second electrode of the inductive isolation unit each include a spiral coil structure. The electrical connection structure as described in claim 1, wherein the conductive layer is a redistribution layer. The electrical connection structure as described in claim 1, wherein the non-conductive dielectric substrate further includes at least one supporting structure extending outward from either the first surface or the second surface.