TWM645520U - Storage device - Google Patents

Abstract

This invention proposes a storage device, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby activation circuit (4), and a plurality of high voltage level control circuits (5 ) and a plurality of write drive circuits (6). The memory array is composed of a plurality of column memory cells and a plurality of row memory cells. Each column memory cell is provided with a control circuit (2) and a high-level memory cell. Voltage level control circuit (5), and each row of memory cells is provided with a precharge circuit (3) and a write drive circuit (6), whereby when writing logic 0, the plurality of write Enter the driver circuit (6) to effectively increase the speed of writing logic 0. Furthermore, the memory unit cell of the present invention is provided with a coupling element (CE) connected between the storage node (A) and the corresponding word line (WL). The coupling element responds to the corresponding word line (WL). The logic state and the storage logic state of the storage node (A) provide different coupling capacitances between the corresponding word line (WL) and the storage node (A), where when the corresponding word line (WL) is The maximum coupling capacitance is provided when logic 1 and the logic state stored in the storage node (A) is logic 0. This can increase the initial voltage level of the storage node (A) in the early stage of writing logic 1, thereby effectively improving the write speed. Enter logic 1 speed.

Description

storage device

This invention relates to a Static Random Access Memory (SRAM) storage device, especially a device that can effectively improve the standby performance of SRAM, and can effectively increase the reading speed and writing speed, and can effectively reduce the SRAM that reduces leakage current, reduces half-selected cell interference during reading, and avoids unnecessary power consumption.

The commonly known 6T static random access memory (SRAM) is shown in Figure 1a. It mainly includes a memory array (memory array), which is composed of a plurality of memory blocks (memory blocks, MB ₁ , MB _2, etc.), each memory block is composed of a plurality of rows of memory cells and a plurality of columns of memory cells. A column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (WL ₁ , WL _2, etc.), and each word line corresponds to a plurality of columns of memory. A column in the unit cell; and a plurality of bit line pairs (BL ₁ , BLB ₁ ...BL _m , BLB _m , etc.), each bit line pair corresponding to a plurality of rows of memory unit cells. One row, and each bit line pair is composed of a bit line (BL ₁ ...BL _m ) and a complementary bit line (BLB ₁ ...BLB _m ).

Figure 1b shows the circuit diagram of a 6T static random access memory (SRAM) unit cell. Among them, PMOS transistors (P1) and (P2) are called load transistors, and NMOS transistors (M1 ) and (M2) are called driving transistors, NMOS transistors (M3) and (M4) are called access transistors, WL is the word line, and BL and BLB They are bit line and complementary bit line respectively. Since the port SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation, instant) the other driving transistor is turned on, and the read initial instantaneous voltage (V _AR ) of node A must satisfy equation (1): V _AR =V _DD ×(R _M1 )/(R _M1 +R _M3 )<V _TM2 ( 1)

Among them, V _AR represents the read initial instantaneous voltage of node A, R _M1 and R _M3 represent the on-resistance of the NMOS transistor (M1) and the NMOS transistor (M3) respectively, and V _DD and V _TM2 represent the power supply respectively. voltage and the critical voltage of the NMOS transistor (M2), which results in the current driving capability ratio between the driving transistor and the access transistor (i.e., cell ratio) usually set between 2.2 and 3.5.

Figure 1b shows the HSPICE transient analysis simulation results of the 6T static random access memory cell during write operation, as shown in Figure 2, which was simulated using TSMC 90nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in Figure 3. Figure 3 shows a circuit schematic diagram of a 5T static random access memory cell (which is a memory device cell) with only a single bit line, compared with the 6T static random access memory cell in Figure 1b , this 5T static random access memory unit cell has one less transistor and one less bit line than the 6T static random access memory unit cell, but the 5T static random access memory unit cell does not change the PMOS transistor There is a problem that it is very difficult to write logic 1 when the channel width to length ratio of P1 and P2 and NMOS transistors M1, M2 and M3 (that is, the same transistor channel width to length ratio as the 6T SRAM cell) is maintained. Consider the situation where node A on the left side of the memory cell originally stores logic 0. Since the charge of node A is only transferred from the bit line (BL) alone, the previously written logic 0 in node A is overwritten with a logic 1. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW =V _DD ×(R _M1 )/(R _M1 +R _M3 ) (2)

Among them, V _AW represents the initial writing instant voltage of node A, R _M1 and R _M3 represent the on-resistance of NMOS transistor (M1) and NMOS transistor (M3) respectively. Comparing equation (1) and equation (2), we can know that, The initial writing instant voltage (V _AW ) is less than the critical voltage (V _TM2 ) of the NMOS transistor (M2), so the writing operation of logic 1 cannot be completed. Figure 3 shows the HSPICE transient analysis simulation results of the 5T static random access memory unit cell during the write operation, as shown in Figure 4. It was simulated using TSMC 90nm CMOS process parameters, as shown in Figure 3. The simulation results can confirm that the 5T static random access memory unit cell with a single bit line has a very difficult problem of writing logic 1.

So far, many methods have been proposed to solve the difficulty of writing logic 1 to the 5T static random access memory unit cell shown in Figure 4, such as the "5T local port static random access memory" proposed in the patent document (TW I716214B, Granted to Shuhei University of Science and Technology on January 11, 2010), however, the patent document still has a shortcoming that it is not fast enough when writing logic 1, so there is still room for improvement.

The main purpose of this invention is to propose a memory device in which a coupling element is provided in the memory cell to connect between the storage node (A) and the corresponding word line (WL). The coupling element responds to the corresponding word line. The logic state of the line (WL) and the storage logic state of the storage node (A) provide different coupling capacitances between the corresponding word line (WL) and the storage node (A), where when the corresponding word The maximum coupling capacitance is provided when the line (WL) is logic 1 and the stored logic state of the storage node (A) is logic 0, thereby increasing the initial voltage level of the storage node (A) during the early stages of writing logic 1 , thereby effectively improving the speed of writing logic 1.

This invention proposes a storage device, which mainly includes a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby activation circuit (4), and a plurality of high voltage level control circuits (5 ) and a plurality of write drive circuits (6). The memory array is composed of a plurality of column memory cells and a plurality of row memory cells. Each column memory cell is provided with a control circuit (2) and a high-level memory cell. Voltage level control circuit (5), and each row of memory cells is provided with a precharge circuit (3) and a write drive circuit (6), whereby when writing logic 0, the plurality of write Enter the driver circuit (6) to effectively increase the speed of writing logic 0. Furthermore, the memory unit cell of the present invention is provided with a coupling element connected between the storage node (A) and the corresponding word line (WL). The coupling element responds to the logic state of the corresponding word line (WL) and The storage logic state of the storage node (A) provides different coupling capacitances between the corresponding word line (WL) and the storage node (A), wherein when the corresponding word line (WL) is logic 1 and When the logic state stored in the storage node (A) is logic 0, it provides the maximum coupling capacitance. This can increase the initial voltage level of the storage node (A) in the early stage of writing logic 1, thereby effectively increasing the level of writing logic 1. the speed.

1:SRAM unit cell

2:Control circuit

3: Precharge circuit

4: Standby start circuit

5: High voltage level control circuit

6:Write driver circuit

P11: The first PMOS transistor

CE: coupling element

P12: The second PMOS transistor

M11: The first NMOS transistor

M12: Second NMOS transistor

M13: The third NMOS transistor

A:Storage node

B: Inverted storage node

BL: bit line

V _DD : power supply voltage

VH: high voltage node

VL1: the first low voltage node

VL2: The second low voltage node

S: Standby mode control signal

/S: Inverted standby mode control signal

WC: write control signal

/WC: Invert write control signal

M21: The fourth NMOS transistor

M22: The fifth NMOS transistor

M23: The sixth NMOS transistor

M24: The seventh NMOS transistor

M25: The eighth NMOS transistor

M26: Ninth NMOS transistor

M27: The tenth NMOS transistor

M28: The eleventh NMOS transistor

RC: Read control signal

RGND: accelerated reading voltage

INV: third inverter

D1: first delay circuit

P31: The third PMOS transistor

P: precharge signal

M41: Twelfth NMOS transistor

P41: The fourth PMOS transistor

C:node

D2: Second delay circuit

WL: word line

R: read signal

P51: The fifth PMOS transistor

P52: The sixth PMOS transistor

I53: The fourth inverter

V _DDH1 : the first high power supply voltage

V _DDH2 : The second highest power supply voltage

P61: The seventh PMOS transistor

M61: Thirteenth NMOS transistor

M62: The fourteenth NMOS transistor

M63: The fifteenth NMOS transistor

I61: fifth inverter

I62: Sixth inverter

Cap: capacitor

Din: Enter data

D3: The third delay circuit

D4: The fourth delay circuit

Y: row decoder output signal

BLB ₁ …BLB _m : complementary bit lines

BLB: complementary bit line

MB ₁ …MB _k : memory block

WL ₁ …WL _n : word lines

BL ₁ …BL _m : bit line

I ₁ , I ₂ , I ₃ : Leakage current

M1…M4: NMOS transistor

P1…P2:PMOS transistor

Figure 1a shows a conventional static random access memory; Figure 1b shows a circuit schematic diagram of a conventional 6T static random access memory unit cell; Figure 2 shows a conventional 6T static random access memory unit cell The writing operation timing diagram; Figure 3 is a schematic circuit diagram showing a conventional 5T static random access memory unit cell; Figure 4 is a writing operation timing diagram showing a conventional 5T static random access memory unit cell; Figure 5 shows the schematic circuit diagram of the preferred embodiment of the present invention; Figure 6 shows the simplified circuit diagram of the preferred embodiment of the present invention in Figure 5 during the writing of logic 0; Figure 7 shows the simplified circuit diagram of the preferred embodiment of the present invention in Figure 5 The simplified circuit diagram of the preferred embodiment of the present invention during reading; Figure 8 shows the simplified circuit diagram of the preferred embodiment of the present invention in Figure 5 during the standby period.

According to the above purpose, this invention proposes a memory device, which mainly includes a memory array. The memory array is composed of a plurality of rows of memory unit cells and a plurality of rows of memory unit cells. Each column of memory unit cells is connected to each row of memory unit cells. Each row of memory cells includes a plurality of memory cells (1); a plurality of control circuits (2), one control circuit (2) is provided for each column of memory cells; a plurality of precharge circuits (3), each row The memory cell is provided with a precharge circuit (3); a standby start-up circuit (4). The standby start-up circuit (4) prompts the SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM; a plurality of high voltage level controls Circuit (5), each column of memory cells is provided with a high voltage level control circuit (5); and a plurality of write drive circuits (6), each row of memory cells is provided with a write drive circuit (6).

For ease of explanation, the memory device shown in Figure 5 only consists of one memory cell (1), one word line (WL), one bit line (BL), one control circuit (2), and one preset A charging circuit (3), a standby activation circuit (4), a high voltage level control circuit (5) and a write drive circuit (6) are described as embodiments. The memory unit cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (composed of a second PMOS transistor M11) Crystal P12 and a second NMOS transistor M12), a third NMOS transistor (M13) and a coupling element (CE), wherein the first inverter and the second inverter are interactively coupled connection, that is, the first inverter The output of the second inverter (i.e., the storage node (A)) is connected to the input of the second inverter, and the output of the second inverter (i.e., the inverting storage node (B)) is connected to the input of the first inverter. , and the output of the first inverter (storage node (A)) is used to store the data of the SRAM unit cell, and the output of the second inverter (inverting storage node (B)) is used to store the SRAM The reverse phase data of the unit cell. It is worth noting here that the first NMOS transistor (M11) and the second NMOS transistor (M12) have the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS transistor (P12) also has the same channel width-to-length ratio. . Furthermore, the coupling element (CE) is composed of an NMOS transistor. The gate of the NMOS transistor is connected to the corresponding word line (WL). The source and drain of the NMOS transistor are connected together and connected. to the storage node (A).

Please refer to Figure 5 again. The control circuit (2) is composed of a fourth NMOS transistor (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), and a seventh NMOS transistor. Crystal (M24), an eighth NMOS transistor (M25), a ninth NMOS transistor (M26), a tenth NMOS transistor (M27), a third PMOS transistor (P21), and a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerating read voltage (RGND), an inverted write control signal (/WC), a standby mode control signal ( S) and an inverted standby mode control signal (/S). The source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/S) and a second low voltage node (VL2); the fifth The source, gate and drain of the NMOS transistor (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (M24) , the gate electrode and the drain electrode are respectively connected to the drain electrode of the eighth NMOS transistor (M25), and the read control signal (RC) and the first low voltage node (VL1); the source, gate and drain of the eighth NMOS transistor (M25) are respectively connected to the accelerated read voltage (RGND), the first delay The output of the circuit (D1) and the source of the seventh NMOS transistor (M24); the first delay circuit (D1) is connected between the output of the third inverter (INV) and the eighth NMOS transistor (M24). between the gates of M25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the ninth The source, gate and drain of the NMOS transistor (M26) are respectively connected to the ground voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the tenth NMOS transistor (M27) is connected to the ground voltage. The source, gate and drain of the crystal (M27) are respectively connected to the ground voltage, the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); and the eleventh NMOS transistor The source, gate and drain of the crystal (M28) are respectively connected to the inverting write control signal (/WC), the inverting standby mode control signal (/S) and the ninth NMOS transistor (M26) The gate. Wherein, the inverted standby mode control signal (/S) is obtained from the standby mode control signal (S) through an inverter, and the inverted write control signal (/WC) is obtained from a write control signal (WC) is obtained through another inverter.

Among them, the drain electrode of the eleventh NMOS transistor (M28), the drain electrode of the tenth NMOS transistor (M27) and the gate electrode of the ninth NMOS transistor (M26) are connected together and form a node ( C), when the standby mode control signal (S) is a logic low level, the voltage level of the node (C) is the logic level of the inverted write control signal (/WC), and when the standby mode control When the signal (S) is a logic high level, the voltage level of the node (C) is the ground voltage, thereby enabling a stable standby mode (because the voltage level of the node C is always the ground voltage during the write operation); and then Furthermore, the logic high level of the node (C) is the voltage level of the power supply voltage (VDD) minus a critical voltage (V _TM28 ) of the eleventh NMOS transistor (M28). Therefore, when the 5T static When the random access memory is in non-write mode (at this time, the corresponding inverted write control signal (/WC) is at a logic high level), the node (C) is the power supply voltage (VDD) minus the The voltage level of the critical voltage (V _TM28 ) of the eleventh NMOS transistor (M28) is not the voltage level of the power supply voltage (VDD), so it can have lower power consumption; and subsequently enters writing When entering the mode (the corresponding inverted write control signal (/WC) is at a logic low level at this time), the charge stored in the node (C) can be quickly passed through the eleventh NMOS transistor (M28) The discharge is enough to turn off the ninth NMOS transistor (M26) with the node (C) as the gate, so that the writing mode can be entered relatively quickly.

The control circuit (2) is designed to control the voltage levels of the first low voltage node (VL1) and the second low voltage node (VL2) in response to different operating modes. In the write mode, the selected unit cell The source voltage (i.e., the first low voltage node VL1) of the driving transistor (i.e., the first NMOS transistor M11) closer to the bit line (BL) is set to a predetermined voltage higher than the ground voltage (i.e., The gate-source voltage V _{GS (M23} ) of the sixth NMOS transistor (M23) will select the source voltage of the other driving transistor (i.e., the second NMOS transistor M12) in the unit cell (i.e., the second The low voltage node VL2) is set to the ground voltage to prevent the difficulty of writing logic 1.

In the first stage of the read mode, the source voltage of the driving transistor (that is, the first NMOS transistor M11) closer to the bit line (BL) in the unit cell (that is, the first low voltage node VL1 ) is set to an accelerating read voltage (RGND) that is lower than the ground voltage. The accelerating read voltage (RGND) that is lower than the ground voltage can effectively increase the reading speed. In the second stage of the read mode When , the source voltage of the driving transistor closer to the bit line (BL) in the selected unit cell (ie, the first NMOS transistor M11 ) is set back to the ground voltage in order to reduce unnecessary power consumption, in which the read mode The time between the second stage and the first stage is equal to The time from when the read control signal (RC) changes from a logic low level to a logic high level until the gate voltage of the eighth NMOS transistor (M25) is enough to turn off the eighth NMOS transistor (M25). The value can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In standby mode, the source voltage of the driving transistors in all memory cells is set to a predetermined voltage higher than the ground voltage in order to reduce leakage current; while in retention mode, the driving transistors in the memory cells are set to a predetermined voltage higher than the ground voltage. The source voltage of the crystal is set to the ground voltage in order to maintain the original retention characteristics. The detailed operating voltage level is shown in Table 1.

The write control signal (WC) in Table 1 is an AND gate operation result of a write signal (W) and the word line (WL) signal. At this time, only the write signal (W) When the signal and the word line (WL) signal are both at a logic high level, the write control signal (WC) is at a logic high level. The write control signal (WC) is inverted and becomes the inverted write control signal ( /WC); the read control signal (RC) is an AND operation result of a read signal (R) and the word line (WL) signal. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent the seventh NMOS Leakage current of transistor (M24).

Please refer to Figure 5. The precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P). The source and gate of the third PMOS transistor (P31) and drain are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so that during the precharge period, the precharge signal (P) at a logic low level ) to precharge the bit line (BL) to the level of the power supply voltage (V _DD ).

Please refer to Figure 5 again. The standby startup circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (M41), a second delay circuit (D2) and the inverting standby It is composed of mode control signal (/S). The source, gate and drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (VDD), the inverting standby mode control signal (/S) and the twelfth NMOS transistor ( The drain of M41); the source, gate and drain of the twelfth NMOS transistor (M41) are respectively connected to the first low voltage node (VL1), the output of the second delay circuit (D2) and The drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inverting standby mode control signal (/S), and the output of the second delay circuit (D2) is connected to to the gate of the twelfth NMOS transistor (M41).

Please refer to Figure 5 again. The high voltage level control circuit (5) is composed of a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), a fourth inverter (I53), the reading It is composed of a control signal (RC) and a first high power supply voltage (V _DDH1 ), in which the source, gate and drain of the fifth PMOS transistor (P51) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and a high voltage node (VH), the source, gate and drain of the sixth PMOS transistor (P52) are respectively connected to the first high power supply voltage ( V _DDH1 ), the output of the fourth inverter (I53) and the high voltage node (VH), and the input of the fourth inverter (I53) is used to receive the read control signal (RC) and output Then it is connected to the gate of the sixth PMOS transistor (P52). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected between the high voltage node node (VH) and the second low voltage node (VL2).

Please refer to Figure 5 again. The write drive circuit (6) is composed of a seventh PMOS transistor (P61), a thirteenth NMOS transistor (M61), a fourteenth NMOS transistor (M62), a A fifteenth NMOS transistor (M63), a fifth inverter (I61), a sixth inverter (I62), a capacitor (Cap), an input data (Din), and a row of decoder output signals (Y ), a third delay circuit (D3), a fourth delay circuit (D4) and a second high power supply voltage (V _DDH2 ), in which the source and gate of the seventh PMOS transistor (P61) The drain electrode is respectively connected to the second high power supply voltage (V _DDH2 ), the output of the fifth inverter (I61) and the drain electrode of the thirteenth NMOS transistor (M61). The thirteenth NMOS The source, gate and drain of the transistor (M61) are respectively connected to the drain of the fifteenth NMOS transistor (M63), the output of the fifth inverter (I61) and the seventh PMOS transistor. (P61), the source, gate and drain of the fourteenth NMOS transistor (M62) are respectively connected to the ground voltage, the output of the third delay circuit (D3) and the seventh PMOS circuit. The drain of the crystal (P61), the source, gate and drain of the fifteenth NMOS transistor (M63) are respectively connected to the ground voltage, the output of the sixth inverter (I62) and the tenth The source of the three NMOS transistors (M61), the input of the fifth inverter (I61) is for receiving the input data (Din), and the output is connected to the gate of the seventh PMOS transistor (P61), The gate of the thirteenth NMOS transistor (M61), the input of the third delay circuit (D3), and the input of the sixth inverter (I62) are for receiving the row decoder output signal (Y), and The output is connected to the input of the fourth delay circuit (D4) and the gate of the fifteenth NMOS transistor (M63). One end of the capacitor (Cap) is connected to the output of the fourth delay circuit (D4). The other end of the capacitor (Cap) is connected to the source of the thirteenth NMOS transistor (M61) and the drain of the fifteenth NMOS transistor (M63), where the seventh PMOS transistor (P61 ), the drain of the thirteenth NMOS transistor (M61) and the drain of the fourteenth NMOS transistor (M62) are commonly connected to the bit line (BL), and the bit line (BL ) is designed to be lower than the voltage level of the ground voltage in the first stage of writing logic 0 to speed up writing logic 0, and is designed to be higher than the power supply voltage when writing logic 1 ( The level of the second highest power supply voltage (V _DDH2 ) of V _DD ) is to accelerate the speed of writing logic 1.

Whether the write drive circuit (6) is enabled or not is determined by the logic level of the row decoder output signal (Y). When the row decoder output signal (Y) is a logic low level, the write drive circuit (6) 6) is in a non-enabled state, and when the row decoder output signal (Y) is a logic high level, the write drive circuit (6) is in an enabled state. When the row decoder output signal (Y) is at a logic low level, the output of the sixth inverter (I62) is at a logic high level, which on the one hand turns on the fifteenth NMOS transistor (M63), and on the other hand passes through the After the delay time provided by the fourth delay circuit (D4), one end of the capacitor (Cap) is charged. Due to the conduction of the fifteenth NMOS transistor (M63), the other end of the capacitor (Cap) is at the ground voltage. , and one end of the capacitor (Cap) will maintain the voltage level of the power supply voltage (V _DD ) due to the charging of the capacitor (Cap).

The write drive circuit (6) adopts a two-stage operation when writing to the enable state of logic 0. In the first stage of enablement of the write drive circuit (6), the row decoder output signal with a logic high level (Y), so that the output of the sixth inverter (I62) is at a logic low level, on the one hand, the fifteenth NMOS transistor (M63) is in the cut-off (OFF) state, and on the other hand, through the fourth delay circuit (D4) After the delay time provided, one end of the capacitor (Cap) is quickly discharged to the ground voltage. Since the input data (Din) is at a logic low level at this time, the output of the fifth inverter (I61) is a logic high level, so the thirteenth NMOS transistor (M61) is turned on, and the seventh PMOS transistor (P61) is in an OFF state, so the voltage level of the bit line (BL) is at the When writing the first stage of logic 0 in the write drive circuit (6), it satisfies equation (3): V _BL1 =-V _DD ×Cap/(Cap+C _BL ) (3)

Among them, V _BL1 represents the voltage level of the bit line (BL) in the first stage of writing logic 0. The absolute value of V _BL1 is designed to be smaller than the critical voltage of the third NMOS transistor (M13). For example, it can be designed is -100mV, -150mV or -200mV, V _DD is the voltage level of the power supply voltage (V _DD ), and Cap and C _BL respectively represent the capacitance value of the capacitor (Cap) and the bit line (BL) the parasitic capacitance value.

When the input data (Din) at the logic low level passes through the delay time provided by the fifth inverter (I61) and the third delay circuit (D3), the write drive circuit (6) enters the enabled third state. In the second stage, at this time, because the fourteenth NMOS transistor (M62) is in a conductive state, the voltage level of the bit line (BL) is at the second stage when the write driver circuit (6) writes logic 0. Satisfies equation (4): V _BL2 =0 (4)

Among them, V _BL2 represents the voltage level of the bit line (BL) in the second stage of writing logic 0.

Based on the working mode of the port SRAM, the working principle of the preferred embodiment of the present invention in Figure 5 is described as follows:

(I)write mode (write mode)

Before the write operation starts, the standby mode control signal (S) is at a logic low level, causing the eleventh NMOS transistor (M28) to be turned on (ON), and causing the tenth NMOS transistor to (M27) is turned OFF. Since the inverted write control signal (/WC) is at a logic high level at this time, the drain of the eleventh NMOS transistor (M28) is at a logic high level. The logic high level The drain of the eleventh NMOS transistor (M28) turns on the ninth NMOS transistor (M26), and causes the first low voltage node (VL1) to be at the ground voltage.

During the write operation, the inverted write control signal (/WC) is at a logic low level, causing the drain of the eleventh NMOS transistor (M28) to be at a logic low level, and the logic low level of the first The drain of the eleventh NMOS transistor (M28) will turn off the ninth NMOS transistor (M26) and make the first low voltage node (VL1) equal to the gate-source voltage of the sixth NMOS transistor (M23). V _{GS (M26)} , thereby effectively preventing the difficulty of writing logic 1.

Next, based on the four writing states of the local SRAM, how to complete the writing operation in the preferred embodiment of the present invention in Figure 5 will be described.

(1) The storage node (A) originally stored logic 0, but now wants to write logic 0: before the writing operation occurs (the word line WL is the ground voltage), the first NMOS transistor (M11) is turned on ( ON). Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line (WL) changes from Low (ground voltage) to High (the power supply voltage V _DD ). When the voltage of the word line (WL) is greater than the critical voltage of the third NMOS transistor (M13) (ie, the access transistor), the third NMOS transistor (M13) changes from OFF to ON ( ON), at this time, because the first NMOS transistor (M11) is turned on, the voltage level of the storage node (A) in the first stage of writing logic 0, although it will be lower than ground due to equation (3) The voltage level of the voltage, during the second stage of writing logic 0, will cause the storage node (A) to return to the original ground voltage due to equation (4) until the end of the writing cycle.

(2) The storage node (A) originally stored logic 0, but now wants to write logic 1: Before the writing operation occurs (the word line WL is the ground voltage), the first NMOS transistor (M11) is turned on ( ON). Because the first NMOS transistor (M11) is ON, when the writing operation starts, the word line (WL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the storage node (A ) will rise following the voltage of the word line (WL).

When the voltage of the word line (WL) is greater than the critical voltage of the third NMOS transistor (M13), the third NMOS transistor (M13) changes from OFF to ON. At this time, because the The bit line (BL) is at the voltage level of the second highest power supply voltage (V _DDH2 ), and because the first NMOS transistor (M11) is still ON and the inverting storage node (B) is at the voltage level is an initial state close to the voltage level of the power supply voltage (V _DD ), so the first PMOS transistor (P11) is still off (OFF), and the writing initial instant voltage of the storage node (A) is ( V _AWI1 ) satisfies equation (5): V _AWI1 =V _DDH2 ×(R _M11 +R _M23 )/(R _M13 +R _M11 +R _M23 )>V _TM12 (5)

Among them, V _AWI1 represents the writing initial instant voltage of storage node (A) from logic 0 to logic 1, R _M11 , R _M13 and R _M23 respectively represent the first NMOS transistor (M11) and the third NMOS transistor. (M13) and the on-resistance of the sixth NMOS transistor (M23), and V _DDH2 and V _TM12 respectively represent the second highest power supply voltage (V _DDH2 ) and the critical voltage of the second NMOS transistor (M12), Since the voltage level of the second high power supply voltage (V _DDH2 ) is designed to be higher than the voltage level of the power supply voltage (V _DD ), and a voltage level equal to the voltage level is provided at the first low voltage node (VL1) The voltage level of the gate-source voltage V _{GS (M23) of the sixth NMOS transistor (M23)} , so the voltage level of the storage node (A) can be easily set to be higher than the conventional 5T static random in Figure 4 The voltage level of the storage node (A) that accesses the memory cell is much higher. The much higher divided voltage level is sufficient to turn on the second NMOS transistor (M12), thus causing the inverting storage node (B) to discharge to a lower voltage level. The inverting storage node (B) The lower voltage level will cause the on-resistance (RM11) of the first NMOS transistor ( _M11 ) to exhibit a higher resistance value, and the higher resistance value of the first NMOS transistor (M11) will occur at the The storage node (A) obtains a higher voltage level, and the higher voltage level of the storage node (A) passes through the second inverter (composed of the second PMOS transistor P12 and the second NMOS transistor M12 ), causing the inverting storage node (B) to exhibit a lower voltage level, and the lower voltage level of the inverting storage node (B) will pass through the first inverter (by the first PMOS transistor P11 and the first NMOS transistor M11), so that the storage node (A) obtains a higher voltage level, and in this cycle, the storage node (A) can be charged to the power supply voltage (V _DD ), And complete the writing action of logic 1.

It is worth noting here that the memory unit cell (1) of the present invention is provided with a coupling element (CE) connected between the storage node (A) and the corresponding word line (WL). The coupling element (CE ) provides different coupling capacitances between the corresponding word line (WL) and the storage node (A) in response to the corresponding logic state of the word line (WL) and the storage logic state of the storage node (A), When the corresponding word line (WL) is logic 1 and the logic state stored in the storage node (A) is logic 0, the maximum coupling capacitance is provided, thereby further increasing the storage node in the early stage of writing logic 1. The writing initial instant voltage of (A) effectively further increases the speed of writing logic 1.

Among them, the first low-voltage node (VL1) originally stores logic 0 in the storage node (A), and during the period when logic 1 is written, it has a gate-source voltage V _{GS ( M23)} , and after writing logic 1, it will have a ground voltage level due to discharge through the ninth NMOS transistor (M26).

(3) The storage node (A) originally stored logic 1, but now wants to write logic 1: before the writing operation occurs (the word line WL is the ground voltage), the first PMOS transistor (P11) is turned on (ON) ). When the word line (WL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), because the storage node (A) is the voltage level of the power supply voltage (V _DD ), and the bit Line (BL) is the voltage level of the second high power supply voltage (V _DDH2 ), so the third NMOS transistor (M13) will continue to remain in the OFF state; at this time, because the first PMOS transistor (P11) is still ON, although the voltage level of the storage node (A) will be slightly greater than the voltage level of the power supply voltage (V _DD ) due to the voltage level of the second highest power supply voltage (V _DDH2 ) However, after the writing is completed, the storage node (A) will return to the original voltage level of the power supply voltage (V _DD ).

(4) The storage node (A) originally stored logic 1, but now wants to write logic 0: before the writing operation occurs (the word line WL is the ground voltage), the first PMOS transistor (P11) is turned on ( ON). When the word line (WL) changes from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the critical voltage of the third NMOS transistor (M13), The third NMOS transistor (M13) changes from OFF to ON. At this time, because the voltage level of the bit line (BL) is the voltage level (V _BL1 ) that satisfies equation (3), It is less than 0V, and because the first PMOS transistor (P11) is still ON and the inverting storage node (B) is in an initial state with a voltage level close to the ground voltage, the first NMOS The transistor (M11) is still off, and the initial instantaneous writing voltage (V _AWI0 ) of the storage node (A) satisfies equation (6): V _AWI0 =V _BL1 ×R _P11 /(R _M13 +R _P11 )+V _DD ×R _M13 /(R _M13 +R _P11 ) (6)

Among them, V _AWI0 represents the writing initial instant voltage of the storage node (A) from logic 1 to logic 0, R _M13 and R _P11 represent the third NMOS transistor (M13) and the first PMOS transistor (P11) respectively. The on-resistance, and V _BL1 and V _DD respectively represent the voltage level of the bit line (BL) in the first stage of writing logic 0 and the voltage level of the power supply voltage (V _DD ). Since the logic 1 When writing logic 0, the third NMOS transistor (M13) operates in the saturation region, and the current in the saturation region is the square of the voltage level of its gate-source voltage V _{GS (M13)} minus its critical voltage. Proportional, so through the design method that the voltage level (V _BL1 ) of the bit line (BL) in the first stage of writing logic 0 is less than 0V, the speed of writing logic 0 from logic 1 can be effectively accelerated, among which the speed of writing logic 0 from logic 1 can be effectively accelerated. Figure 6 is a simplified circuit diagram during the writing of logic 0 in Figure 5 of the preferred embodiment of this invention, and is specified.

(II)Read mode (read mode)

Before the read operation starts, the standby mode control signal (S) is at a logic low level, and the inverted write control signal (/WC) and the inverted standby mode control signal (/S) are both at a logic high level, The eleventh NMOS transistor (M28) is turned on, and the tenth NMOS transistor (M27) is turned off, so the node C is at a logic high level. The node C at the logic high level will turn on the ninth NMOS transistor (M27). M26), and make the first low voltage node (VL1) be at the ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (M24) is turned off (OFF), and the eighth NMOS transistor (M25) is turned on (ON).

It is worth noting here that during the precharge period before the read operation starts, the precharge signal (P) is at a logic low level, thereby precharging the corresponding bit line (BL) to the power supply. The level of the voltage (V _DD ), however, because for example, the operating voltage of the process technology below 10 nanometers will drop below 0.9 volts, which will cause the reading speed to be reduced and unable to meet the specification. Therefore, this invention proposes a two-stage reading Control is taken to increase reading speed and meet specifications while also avoiding unnecessary power consumption.

The preferred embodiment of this invention shown in Figure 5 uses two-stage read control to increase the read speed while also avoiding unnecessary power consumption. In the first stage of the read operation, the read The control signal (RC) is at a logic high level, causing the seventh NMOS transistor (M24) is turned on, because the eighth NMOS transistor (M25) is still turned on at this time, so the first low voltage node (VL1) is approximately the accelerating read voltage (RGND) which is lower than the ground voltage, which is lower than the ground voltage. The accelerated reading voltage (RGND) can effectively increase the reading speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, so that the seventh NMOS transistor (M24) is still turned on, because at this time the eighth NMOS transistor (M25) is turned off, so the first low-voltage node (VL1) will be at the ground voltage through the turned-on ninth NMOS transistor (M26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the time between the second phase of the read operation and the first phase is equal to the time when the read control signal (RC) changes from a logic low level to a logic high level, and ends when the read control signal (RC) changes from a logic low level to a logic high level. The time until the gate voltage of the eight NMOS transistor (M25) is enough to turn off the eighth NMOS transistor (M25), its value can be determined by the falling delay time of the third inverter (INV) and the first delay circuit (D1) to adjust the delay time provided. Furthermore, no matter in the first phase or the second phase of the read operation, the ninth NMOS transistor (M26) is in a conductive state (because the gate of the ninth NMOS transistor (M26) is at a logic high level. ). Figure 7 shows a simplified circuit diagram of the preferred embodiment of the invention in Figure 5 during reading.

(III) Standby mode

First, explain how the standby startup circuit (4) in Figure 5 prompts the local SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: First, before entering the standby mode, the inverted standby mode control signal (/S) Is logic High, the inverted standby mode control signal (/S) of the logic High causes the fourth PMOS transistor (P41) to turn off (OFF), and causes the twelfth NMOS transistor (M41) to turn on (ON); Then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) to be turned on (ON). ), only during the initial period of the standby mode (the initial period is equal to when the inverting standby mode control signal (/S) changes from logic High to logic Low to the gate of the twelfth NMOS transistor (M41) The time until the voltage is sufficient to turn off the twelfth NMOS transistor (M41), which can be adjusted by a delay time provided by the second delay circuit (D2)), the twelfth NMOS transistor (M41) is still Then, the first low voltage node (VL1) can be quickly charged to the voltage level of the critical voltage (V _TM23 ) of the sixth NMOS transistor (M23), that is, the SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of standby mode, the twelfth NMOS transistor (M41) turns off and stops supplying current.

Please refer to Figure 5. In standby mode, the standby mode control signal (S) is at a logic high level, and the inverting standby mode control signal (/S) is at a logic low level. The inverted standby signal at the logic low level is The mode control signal (/S) can cause the fourth NMOS transistor (M21) in the control circuit (2) to turn off (OFF), and the standby mode control signal (S) at the logic high level can cause the fifth The NMOS transistor (M22) is turned on (ON). At this time, the fifth NMOS transistor (M22) is used as an equalizer. Therefore, the fifth NMOS transistor (M22) in the on-state can be used to Make the voltage level of the first low voltage node (VL1) equal to the voltage level of the second low voltage node (VL2), and these voltage levels will be equal to the critical value of the sixth NMOS transistor (M23) voltage level (V _TM23 ). Figure 8 shows a simplified circuit diagram of the preferred embodiment of the invention in Figure 5 during standby.

Figure 8 (because the transistor as the coupling element CE is off, so it is omitted and not drawn) describes the leakage currents (subthreshold leakage current) I ₁ , I ₂ , and I ₃ generated by the embodiment of the present invention in the standby mode. It is assumed that the output of the first inverter in the SRAM cell (i.e., the storage node (A)) is logic Low (it is worth noting here that due to the voltage level of the second low voltage node (VL2) in the standby mode The standard is maintained at the voltage level of the threshold voltage (V _TM23 ) of the sixth NMOS transistor (M23), so the voltage level of the storage node (A) being logic Low is also maintained at the voltage level of V _TM23 ), The output of the second inverter (ie, the inverting storage node (B)) is logic High (power supply voltage V _DD ). Since the leakage currents I ₁ , I ₂ , and I ₃ of this creative embodiment are smaller than those of the prior art in Figure 1b, the discussion is common knowledge and will not be repeated here.

(IV) retention mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to the ground voltage, their working principle is the same as that of the traditional 5T SRAM cell with a single bit line in Figure 3. No more details will be given here.

1:SRAM unit cell

2:Control circuit

3: Precharge circuit

4: Standby start circuit

5: High voltage level control circuit

6:Write driver circuit

P11: The first PMOS transistor

CE: coupling element

P12: The second PMOS transistor

M11: The first NMOS transistor

M12: Second NMOS transistor

M13: The third NMOS transistor

A:Storage node

B: Inverted storage node

BL: bit line

V _DD : power supply voltage

VH: high voltage node

VL1: the first low voltage node

VL2: The second low voltage node

S: Standby mode control signal

/S: Invert standby mode control signal

/WC: Invert write control signal

M21: The fourth NMOS transistor

M22: The fifth NMOS transistor

M23: The sixth NMOS transistor

M24: The seventh NMOS transistor

M25: The eighth NMOS transistor

M26: Ninth NMOS transistor

M27: The tenth NMOS transistor

M28: The eleventh NMOS transistor

RC: Read control signal

RGND: accelerated reading voltage

INV: third inverter

D1: first delay circuit

P31: The third PMOS transistor

P: precharge signal

M41: Twelfth NMOS transistor

P41: The fourth PMOS transistor

C:node

D2: Second delay circuit

WL: word line

R: read signal

P51: The fifth PMOS transistor

P52: The sixth PMOS transistor

I53: The fourth inverter

V _DDH1 : the first high power supply voltage

V _DDH2 : The second highest power supply voltage

P61: The seventh PMOS transistor

M61: Thirteenth NMOS transistor

M62: The fourteenth NMOS transistor

M63: The fifteenth NMOS transistor

I61: fifth inverter

I62: Sixth inverter

Cap: capacitor

Din: Enter data

D3: The third delay circuit

D4: The fourth delay circuit

Y: row decoder output signal

Claims (4)

A storage device, including: a memory array, the memory array is composed of a plurality of columns of memory unit cells and a plurality of rows of memory unit cells, each column of memory unit cells and each row of memory unit cells include a plurality of memory unit cells (1); a plurality of control circuits (2), one control circuit (2) is set for each column of memory unit cells; a plurality of precharge circuits (3), one precharge is set for each row of memory unit cells Circuit (3); a standby activation circuit (4), which prompts the storage device to quickly enter the standby mode to effectively improve the standby performance of the storage device; a plurality of high voltage level control circuits (5 ), each column of memory cells is provided with a high voltage level control circuit (5) to increase the reading speed when reading logic 0; and a plurality of write drive circuits (6), each row of memory cells is provided with one The writing drive circuit (6) is used to increase the writing speed during the writing operation; wherein each memory unit cell (1) further includes: a first inverter, which is composed of a first PMOS transistor (P11 ) and a first NMOS transistor (M11), the first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); a second inverter , is composed of a second PMOS transistor (P12) and a second NMOS transistor (M12). The second inverter is connected to a high voltage node (VH) and a second low voltage node (VL2 ); a storage node (A) is formed by the output terminal of the first inverter; an inverting storage node (B) is formed by the output terminal of the second inverter; a first Three NMOS transistors (M13) are connected between the storage node (A) and the bit line (BL), and the gate is connected to a word line (WL); and a coupling element (CE), the The coupling element (CE) is composed of an NMOS transistor. The gate of the NMOS transistor is connected to the word line (WL). The source and drain of the NMOS transistor are connected together and connected to the storage node ( A); wherein, the first inverter and the second inverter are cross-coupled, that is, the output end of the first inverter (i.e., the storage node A) is connected to the second inverter The input terminal of the inverter, and the output terminal of the second inverter (ie, the inverting storage node B) is connected to the input terminal of the first inverter; and each control circuit (2) further includes: a first Four NMOS transistors (M21), a fifth NMOS transistor (M22), a sixth NMOS transistor (M23), a seventh NMOS transistor (M24), an eighth NMOS transistor (M25), and a seventh NMOS transistor (M25). Nine NMOS transistors (M26), a tenth NMOS transistor (M27), an eleventh NMOS transistor (M28), a read control signal (RC), a third inverter (INV), a first A delay circuit (D1), an accelerated read voltage (RGND), an inverted write control signal (/WC), a standby mode control signal (S) and an inverted standby mode control signal (/S); wherein , the source, gate and drain of the fourth NMOS transistor (M21) are respectively connected to the ground voltage, the inverting standby mode control signal (/S) and the second low voltage node (VL2); The source, gate and drain of the five NMOS transistors (M22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); The source of the sixth NMOS transistor (M23) is connected to the ground voltage, and the gate and drain are connected together and connected to the first low voltage node (VL1); the seventh NMOS transistor (M24) The source, gate and drain are respectively connected to the drain of the eighth NMOS transistor (M25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor The source, gate and drain of (M25) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1) and the source of the seventh NMOS transistor (M24); The first delay circuit (D1) is connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (M25); the input of the third inverter (INV) is for The read control signal (RC) is received, and the output is connected to the input of the first delay circuit (D1); the source, gate and drain of the ninth NMOS transistor (M26) are connected to the ground respectively. voltage, the drain of the tenth NMOS transistor (M27) and the first low voltage node (VL1); the source, gate and drain of the tenth NMOS transistor (M27) are respectively connected to the ground voltage , the standby mode control signal (S) and the gate of the ninth NMOS transistor (M26); the source, gate and drain of the eleventh NMOS transistor (M28) are respectively connected to the inverting write input control signal (/WC), the inverting standby mode control signal (/S) and the gate of the ninth NMOS transistor (M26); wherein, the drain of the eleventh NMOS transistor (M28), the The drain of the tenth NMOS transistor (M27) and the gate of the ninth NMOS transistor (M26) are connected together and form a node (C). When the standby mode control signal (S) is at a logic low level, The voltage level of the node (C) is the logic level of the inverted write control signal (/WC), and when the standby mode control signal (S) is the logic high level, the voltage level of the node (C) The voltage level of the node (C) is the ground voltage, thereby allowing a stable standby mode (since the voltage level of the node (C) is always the ground voltage during the write operation); furthermore, the logic high level of the node (C) is the ground voltage. The voltage level of the power supply voltage (VDD) minus a critical voltage (V _TM28 ) of the eleventh NMOS transistor (M28). Therefore, when the memory device is in the non-writing mode (this corresponds to the reverse When the phase write control signal (/WC) is at a logic high level), the node (C) is the power supply voltage (VDD) minus the critical voltage (V _TM28 ) of the eleventh NMOS transistor (M28) The voltage level of the power supply voltage (VDD) is not the voltage level of the power supply voltage (VDD), so it can have lower power consumption; and subsequently enters the write mode (at this time, the corresponding inverted write control signal (/WC ) is a logic low level), because the charge stored in the node (C) can be quickly discharged through the eleventh NMOS transistor (M28) to enough to turn off the ninth transistor with the node (C) as the gate. NMOS transistor (M26), so it can enter the write mode more quickly; among them, the read control signal (RC) during the non-read mode is set to the level of the accelerating read voltage (RGND), In order to prevent the leakage current of the seventh NMOS transistor (M24) during the non-read mode; in addition, the standby startup circuit (4) is designed to activate the first low voltage node during an initial period of entering the standby mode. The parasitic capacitance at (VL1) is quickly charged to the voltage level of the critical voltage (V _TM23 ) of the sixth NMOS transistor (M23). As for the memory device described in item 1 of the patent application, each high voltage level control circuit (5) further includes: a fifth PMOS transistor (P51), a sixth PMOS transistor (P52), and a first PMOS transistor (P52). Four inverters (I53), the read control signal (RC) and a first high power supply voltage (V _DDH1 ), in which the source, gate and drain of the fifth PMOS transistor (P51) are respectively Connected to the power supply voltage (V _DD ), the read control signal (RC) and the high voltage node (VH), the source, gate and drain of the sixth PMOS transistor (P52) are connected to The first high supply voltage (V _DDH1 ), the output of the fourth inverter (I53) and the high voltage node (VH), and the input of the fourth inverter (I53) is for receiving the read control signal (RC), and the output is connected to the gate of the sixth PMOS transistor (P52). As for the memory device described in claim 1 of the patent application, each write drive circuit (6) further includes: a seventh PMOS transistor (P61), a thirteenth NMOS transistor (M61), a third Fourteen NMOS transistors (M62), a fifteenth NMOS transistor (M63), a fifth inverter (I61), a sixth inverter (I62), a capacitor (Cap), an input data ( Din), a row decoder output signal (Y), a third delay circuit (D3), a fourth delay circuit (D4) and a second high power supply voltage (V _DDH2 ); wherein, the seventh PMOS transistor The source, gate and drain of (P61) are respectively connected to the second highest power supply voltage (V _DDH2 ), the output of the fifth inverter (I61) and the thirteenth NMOS transistor (M61) The drain electrode of the thirteenth NMOS transistor (M61) is connected to the drain electrode of the fifteenth NMOS transistor (M63) and the fifth inverter (I61) respectively. The output and the drain of the seventh PMOS transistor (P61); the source, gate and drain of the fourteenth NMOS transistor (M62) are respectively connected to the ground voltage and the third delay circuit (D3 ) and the drain of the seventh PMOS transistor (P61); the source, gate and drain of the fifteenth NMOS transistor (M63) are respectively connected to the ground voltage and the sixth inverter. The output of (I62) is connected to the source of the thirteenth NMOS transistor (M61); the input of the fifth inverter (I61) is for receiving the input data (Din), and the output is connected to the seventh PMOS The gate of the transistor (P61), the gate of the thirteenth NMOS transistor (M61) and the input of the third delay circuit (D3); the input of the sixth inverter (I62) is for receiving the line The decoder outputs a signal (Y), and the output is connected to the input of the fourth delay circuit (D4) and the gate of the fifteenth NMOS transistor (M63); one end of the capacitor (Cap) is connected to the The output of the four-delay circuit (D4), and the other end of the capacitor (Cap) is connected to the source of the thirteenth NMOS transistor (M61) and the drain of the fifteenth NMOS transistor (M63). The storage device as described in item 1 of the patent application, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P); wherein, the third The source, gate and drain of the PMOS transistor (P31) are respectively connected to the power supply voltage (V _DD ), the precharge signal (P) and the corresponding bit line (BL) to facilitate a precharge During this period, the precharge signal (P) at a logic low level is used to precharge the corresponding bit line (BL) to the level of the power supply voltage (V _DD ).

Images