TWI906121B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a contact layer, a bottom electrode layer, a top electrode layer and an insulation layer. The contact layer includes a contact plug. The bottom electrode layer is electrically connected to the contact plug, and which a first sidewall of the bottom electrode layer has a staircase profile. The top electrode layer is over the bottom electrode layer. The insulation layer is between the bottom electrode layer and the top electrode layer, and is along the first sidewall.

Description

semiconductor devices

Some of the embodiments disclosed herein relate to semiconductor devices.

Capacitor structures are commonly used in memory structures. During memory operation, a charge is distributed across the surface of the capacitor's electrode layers. Therefore, the shape and contour of the capacitor's electrode layers determine the amount of charge distributed across their surface. The more complete the shape of the capacitor's electrode layers, the greater the amount of charge distributed across their surface, thus achieving a higher capacitance.

Some embodiments of this disclosure provide a semiconductor device comprising a contact layer, a lower electrode layer, an upper electrode layer, and an insulating layer. The contact layer includes contact plugs. The lower electrode layer is electrically connected to the contact plugs, wherein a first sidewall of the lower electrode layer has a stepped profile. The upper electrode layer is located above the lower electrode layer. The insulating layer is located between the lower electrode layer and the upper electrode layer, and runs along the first sidewall.

In some embodiments, the lower electrode layer comprises a first portion and a second portion, the second portion being on top of the first portion and narrower than the first portion.

In some embodiments, the semiconductor device further includes a first support layer and a second support layer. The first support layer contacts a first portion of the lower electrode layer. The second support layer is on the first support layer and contacts a second portion of the lower electrode layer, with a top portion of the lower electrode layer flush with the top portion of the second portion of the second support layer.

In some embodiments, the top of the first part of the lower electrode layer is flush with the bottom of the second support layer.

In some embodiments, the top of the first portion of the lower electrode layer is lower than the bottom of the second support layer.

In some embodiments, the semiconductor device further includes a third support layer and a fourth support layer. The third support layer is below the first support layer and contacts a first portion of the lower electrode layer. The fourth support layer is below the third support layer and contacts a first portion of the lower electrode layer.

In some embodiments, the lower electrode layer has a second sidewall relative to the first sidewall, the second sidewall being substantially perpendicular to the normal direction of the contact layer.

In some embodiments, the first support layer and the second support layer contact the second sidewall of the lower electrode layer.

In some embodiments, the insulating layer extends from the first sidewall of the lower electrode layer to the top of the second portion of the lower electrode layer.

In some embodiments, the insulation layer extends from the top of the second portion of the lower electrode layer to the top of the second support layer.

In some embodiments disclosed herein, the lower electrode layer of the capacitor structure is less susceptible to etching. As a result, the capacitor structure disclosed herein can accommodate more charge and therefore contain a larger capacitance.

The following diagrams disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, these practical details are not necessary in some embodiments of this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the diagrams in a simplified manner.

In some embodiments disclosed herein, the lower electrode layer of the capacitor structure is less susceptible to etching. As a result, the capacitor structure disclosed herein can accommodate more charge and therefore contain a larger capacitance.

Figures 1 through 13A illustrate cross-sectional views of the fabrication process of a semiconductor device 100 according to some embodiments of the present disclosure. Referring to Figure 1, a contact layer 110 is provided, wherein the contact layer 110 includes a plurality of contact plugs 112 and a dielectric layer 114. The contact plugs 112 are arranged in the dielectric layer 114. The contact plugs 112 are made of conductors, and the dielectric layer 114 is made of a dielectric material. In some embodiments, the contact plugs 112 are made of a metal, such as tungsten, and the dielectric layer 114 is made of a nitride. The contact layer 110 may include an array area R1 and a peripheral area R2, and the contact plugs 112 are arranged only in the array area R1 of the contact layer 110.

Referring to Figure 2, a multi-layer structure 120 is formed on the contact layer 110. The multi-layer structure 120 includes a support layer 122, a first sacrificial material layer 124, a support layer 126, a second sacrificial material layer 128, a support layer 132, a third sacrificial material layer 134, and a support layer 136 stacked from bottom to top. Specifically, support layers 122, 126, 132, and 136 serve as support materials for the subsequently formed lower electrode layer, and are formed of nitrides. The first sacrifice material layer 124, second sacrifice material layer 128, and third sacrifice material layer 134 are formed of oxides. In some embodiments, the second sacrifice material layer 128 and third sacrifice material layer 134 are formed of tetraethoxysilane (TEOS), while the first sacrifice material layer 124 is formed of borosilicate glass (BPSG).

Referring to Figure 3, a plurality of first grooves T1 are formed in the multilayer structure 120, wherein the bottom of the first groove T1 exposes the contact layer 110. Specifically, a hard mask layer can be formed on the multilayer structure 120 first, and then the hard mask layer can be patterned using a photolithography process. The multilayer structure 120 can then be etched using the hard mask layer as a mask to form the first grooves T1 in the multilayer structure 120. After the first grooves T1 are formed, the hard mask layer can be removed. The bottom of the first groove T1 is located directly above the contact plugs 112 of the contact layer 110.

Referring to Figure 4, a lower electrode material layer 142 is formed on the multilayer structure 120 and in the first groove T1. The lower electrode material layer 142 may completely cover the multilayer structure 120 and fill the first groove T1. Specifically, the lower electrode material layer 142 may be formed by any suitable method, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar methods. Since the lower electrode material layer 142 fills the first groove T1, a portion of the lower electrode material layer 142 is also located directly above the contact plugs 112 of the contact layer 110. In some embodiments, the lower electrode material layer 142 is titanium silicon nitride (TiSiN), but the material of the lower electrode material layer 142 is not limited to this.

Referring to Figure 5, a hard mask layer 150 is formed on the lower electrode material layer 142. The hard mask layer 150 completely covers the lower electrode material layer 142. The thickness W1 of the hard mask layer 150 is 3 to 12 times the thickness W2 of the support layer 132. When the hard mask layer 150 is within the exposed area, multiple support layers (e.g., support layer 126, support layer 132, and support layer 136) can be patterned using the same hard mask layer 150 in subsequent processes. This reduces the number of photolithography processes required to form the semiconductor device 100, thereby reducing process costs.

Referring to Figure 6, a photoresist layer PR is formed on the hard mask layer 150. Specifically, a photoresist material layer can be formed on the hard mask layer 150 first, and then the photoresist material layer can be exposed and developed to form the photoresist layer PR on the hard mask layer 150. The photoresist layer PR has an opening O1, and the width of the opening O1 is wider than the patterned support layer 136 below. That is, the opening O1 of the photoresist layer PR partially overlaps with the lower electrode material layer 142 in the first trench T1.

Referring to Figure 7, a second trench T2 is formed in the multilayer structure 120 using a hard mask layer 150 as an etch mask to partially etch the electrode material layer 142, and the bottom of the second trench T2 is higher than the support layer 132. In some embodiments, the bottom of the second trench T2 is lower than the bottom of the support layer 136. Specifically, a photoresist layer PR can be used as a mask to pattern the hard mask layer 150 to form an opening in the hard mask layer 150. Then, the second trench T2 is formed in the multilayer structure 120 using the hard mask layer 150 as an etch mask, and the second trench T2 corresponds to the opening O1 (see Figure 6). Since the opening O1 of the photoresist layer PR partially overlaps with the lower electrode material layer 142 in the first trench T1, the lower electrode material layer 142 in the first trench T1 will also be etched when the second trench T2 is formed. Therefore, in subsequent processes, the wet etching solution used to remove the sacrifice material layer can flow more easily between the lower electrode material layers 142. If the lower electrode material layer 142 in the first trench T1 is not etched when the second trench T2 is formed, it may be impossible to confirm whether the uppermost lower electrode material layer 142 (the lower electrode material layer 142 directly below the opening O1 in Figure 6) has been etched through, making it difficult for the wet etching solution to flow in. In some embodiments, the second trench T2 is wider than either of the first trench T1. Since the bottom of the second trench T2 is higher than the support layer 132, the loss of the lower electrode material layer 142 is minimal. In the final semiconductor device 100, the lower electrode layer formed by the lower electrode material layer 142 has sufficient volume to accommodate a greater amount of charge, resulting in greater capacitance in the semiconductor device 100. Since the thickness W1 of the hard mask layer 150 (see Figure 5) is 3 to 12 times the thickness W2 of the support layer 132 (see Figure 5), the lower electrode material layer 142 of the capacitor structure can be patterned using the hard mask layer 150 and the lower electrode material layer 142 can be patterned into the required shape. Then, the other material layers are etched back using the hard mask layer. In this way, the loss of the lower electrode layer during patterning can be reduced, thereby increasing the capacitance content of the lower electrode layer.

Referring to Figure 8, the third sacrificial material layer 134 is removed. Specifically, the third sacrificial material layer 134 can be completely removed using a directional etching process such as wet etching. In some embodiments, dilute hydrofluoric acid can be used to remove the third sacrificial material layer 134, but this is not a limitation. Since the hard mask layer 150, support layer 136, and support layer 132 have sufficient etching resistance to this wet etching process, the hard mask layer 150, support layer 136, and support layer 132 will not be removed. Support layer 132 can serve as an etching stop layer, and after the third sacrificial material layer 134 is removed, support layer 132 is exposed.

Referring to Figure 9, a hard mask layer 150 and a lower electrode material layer 142 are used as the etching mask, and the support layer 132 is etched back. Specifically, anisotropic etching processes such as dry etching can be used to etch back the support layer 132. During the etch back of the support layer 132, the support layer 132 exposed by the second groove T2 will be etched, while the support layer 132 directly below the hard mask layer 150 remains in place. During the etch back of the support layer 132, since the hard mask layer 150 and the support layer 132 are made of the same or similar materials, the hard mask layer 150 will also be partially removed. However, as disclosed above, the thickness of the hard mask layer 150 is such that even if it is partially etched, the hard mask layer 150 can still have a certain thickness and serve as a mask in subsequent processes. In addition, since the lower electrode material layer 142 and the support layer 132 are made of different materials, the lower electrode material layer 142 can also serve as a mask layer for the etch-back support layer 132.

Referring to Figure 10, the second sacrifice material layer 128 is removed. Specifically, the second sacrifice material layer 128 can be completely removed using a directional etching process such as wet etching. In some embodiments, dilute hydrofluoric acid can be used to remove the second sacrifice material layer 128, but this is not a limitation. Since the hard mask layer 150, support layer 136, support layer 132, and support layer 126 have sufficient etching resistance to this wet etching process, the hard mask layer 150, support layer 136, support layer 132, and support layer 126 will not be removed. The support layer 126 can serve as an etch stop layer, and is exposed after the second sacrificial material layer 128 is removed.

Referring to Figure 11, a hard mask layer 150 (see Figure 10) and a lower electrode material layer 142 are used as the etching mask, and the support layer 126 is etched back. Specifically, anisotropic etching processes such as dry etching can be used to etch back the support layer 126. During the etch back of the support layer 126, the support layer 126 exposed by the second groove T2 will be etched, while the support layer 126 directly below the hard mask layer 150 remains in place. During the etch back of the support layer 126, since the hard mask layer 150 and the support layer 126 are made of the same or similar materials, the hard mask layer 150 will also be completely removed. Furthermore, since the lower electrode material layer 142 and the support layer 126 are made of different materials, the lower electrode material layer 142 can also serve as the material layer for the etch-back support layer 126. After the etch-back support layer 126 is completed, the lower electrode material layer 142 on the support layer 136 can be removed to expose the support layer 136. In this way, the lower electrode material layer 142 is etched into the lower electrode layer 140, and the top of the lower electrode layer 140 is connected to the support layer 136.

Referring to Figure 12, the first sacrifice material layer 124 is removed. Specifically, the first sacrifice material layer 124 can be completely removed using a directional etching process such as wet etching. In some embodiments, dilute hydrofluoric acid can be used to remove the first sacrifice material layer 124, but this is not a limitation. Since the support layers 136, 132, 126, and 122 have sufficient etching resistance to this wet etching process, they will not be removed. The support layer 122 can serve as an etch stop layer, and is exposed after the first sacrificial material layer 124 is removed.

Referring to Figures 13A and 13B, where Figure 13B is an enlarged view of region M in Figure 13A, an insulating layer 160, an upper electrode layer 170, and a conductor layer 180 are sequentially formed on the lower electrode layer 140, support layer 122, support layer 126, support layer 132, and support layer 136. The insulating layer 160 may cover the lower electrode layer 140, support layer 122, support layer 126, support layer 132, and support layer 136. The upper electrode layer 170 covers the insulation layer 160, and the conductor layer 180 covers the upper electrode layer 170. In this way, the insulation layer 160, the upper electrode layer 170, and the conductor layer 180 can fill the gaps between the lower electrode layer 140, the support layer 122, the support layer 126, the support layer 132, and the support layer 136 to form a semiconductor device 100, and the semiconductor device 100 is a capacitor structure. In some embodiments, the insulating layer 160 is a high-dielectric-constant material layer, such as zirconium oxide ( _ZrO₂x ), the upper electrode layer 170 is titanium nitride (TiN), and the conductor layer 180 is polycrystalline silicon. However, the materials of the insulating layer 160, the upper electrode layer 170, and the conductor layer 180 are not limited to these. Furthermore, although only the conductor layer 180 covering the upper electrode layer 170 is shown here, there may be more layers covering the upper electrode layer 170 and the conductor layer 180.

Specifically, semiconductor device 100 may include a contact layer 110, a support layer 122, and a plurality of lower electrode layers 140, support layers 126, support layers 132, and support layers 136. Contact layer 110 includes contact plugs 112. Support layer 122 is on contact layer 110. Lower electrode layer 140 is on support layer 122 and is directly above the contact plugs 112 of contact layer 110. Each of the lower electrode layers 140 includes a first portion 144 and a second portion 146, the second portion 146 being on the first portion 144 and narrower than the first portion 144. A support layer 126 is located between two adjacent lower electrode layers 140, and the support layer 126 contacts a first portion 144 of either lower electrode layer 140. A support layer 132 is located on the support layer 126 and contacts a first portion 144 of either lower electrode layer 140. A support layer 132 is located between two adjacent lower electrode layers 140. A support layer 136 is located on the support layer 132 and contacts a second portion 146 of either lower electrode layer 140. The support layer 136 is located between two adjacent lower electrode layers 140, and the top of the lower electrode layer 140 is flush with the top of the support layer 136.

The top of the first portion 144 of any of the lower electrode layers 140 is higher than the support layer 132. In some embodiments, the top of the first portion 144 of any of the lower electrode layers 140 is lower than the support layer 136. Because the lower electrode layer 140 is not significantly lost during its formation, it can accommodate more charge, thus increasing the capacitance contained in the lower electrode layer 140.

Figure 14 illustrates a cross-sectional view of a semiconductor device 100 in some other embodiments, in which the top of the first portion 144 of any of the lower electrode layers 140 is flush with the bottom of the support layer 136. Other relevant details are the same as in Figure 13A and will not be repeated.

Although some embodiments disclosed herein only illustrate semiconductor device 100 having support layers 122, 126, 132, and 136, semiconductor device 100 may also have more support layers, which may be located below support layer 132. Specifically, a thicker hard mask layer 150 may be formed during the process shown in Figure 5, and then semiconductor device 100 may be formed using the processes shown in Figure 6 and thereafter, or multiple support layers may be etched back and forth using the electrode material layer 142 as an etch mask after the hard mask layer 150 has been removed. In this way, the hard mask layer can have sufficient thickness and strength to etch back multiple support layers to form a semiconductor device 100 with more support layers.

In summary, in some embodiments disclosed herein, a hard mask layer can be formed on the support layer 136 used to form the capacitor structure, and the thickness of the hard mask layer is 3 to 12 times that of the support layer 132. Therefore, when the lower electrode layer, etch-back support layer 132, and support layer 126 of the capacitor structure are patterned using the same hard mask layer, the photolithography process in the capacitor structure fabrication process can be reduced, thereby reducing alignment problems caused by different photolithography processes. Since the capacitor structure forming some embodiments of this disclosure does not have an alignment problem, the lower electrode layer can be patterned first using a hard masking layer, and then the support layer 132 can be etched back using the hard masking layer. In this way, the loss of the lower electrode layer during patterning can be reduced, thereby increasing the charge that the lower electrode layer can accommodate and increasing the capacitance.

Although this disclosure has been made in practice as described above, it is not intended to limit this disclosure. Anyone skilled in this art may make various modifications and alterations without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the attached patent application.

100: Semiconductor Device 110: Contact Layer 112: Contact Plug 114: Dielectric Layer 120: Multilayer Structure 122, 126, 132, 136: Support Layers 124: First Sacrifice Material Layer 128: Second Sacrifice Material Layer 134: Third Sacrifice Material Layer 140: Lower Electrode Layer 142: Lower Electrode Material Layer 144: First Section 146: Second Section 150: Hard Mask Layer 160: Insulation Layer 170: Upper Electrode Layer 180: Conductor Layer O1: Opening M: Region PR: Photoresist Layer R1: Array area R2: Peripheral area T1: First groove T2: Second groove W1: Thickness W2: Thickness

Figures 1 through 13A illustrate cross-sectional views of the fabrication process of semiconductor devices according to some embodiments of the present disclosure. Figure 13B is an enlarged view of region M in Figure 13A. Figure 14 illustrates cross-sectional views of semiconductor devices according to other embodiments of the present disclosure.

Domestic Storage Information (Please record in order of storage institution, date, and number) None International Storage Information (Please record in order of storage country, institution, date, and number) None

100: Semiconductor Devices

110: Touch Layer

112: Contact embolism

114: Dielectric layer

122, 126, 132, 136: Support layers

140: Lower electrode layer

144: Part One

146: Part Two

180: Conductor layer

M: Region

R1: Array Area

R2: Surrounding Area

Claims (5)

A semiconductor device includes: a contact layer, wherein the contact layer includes a contact plug; a first support layer on the contact layer; a lower electrode layer electrically connected to the contact plug, wherein the lower electrode layer includes a first portion and a second portion, the second portion being on the first portion and narrower than the first portion; an insulating layer covering the lower electrode layer; and an upper electrode layer located above the lower electrode layer. The semiconductor device as claimed in claim 1 further comprises: a second support layer that contacts the first portion of the lower electrode layer; a third support layer that is on the second support layer and contacts the first portion of the lower electrode layer, wherein a top of the first portion of the lower electrode layer is higher than the third support layer; and a fourth support layer that is on the third support layer and contacts the second portion of the lower electrode layer, wherein a top of the lower electrode layer is flush with a top of the second portion of the fourth support layer. The semiconductor device as described in claim 2, wherein the top of the first portion of the lower electrode layer is flush with a bottom of the fourth support layer. The semiconductor device as described in claim 2, wherein the top of the first portion of the lower electrode layer is lower than a bottom of the fourth support layer. The semiconductor device as described in claim 2, wherein the lower electrode layer is directly above the contact plug of the contact layer.