TWI903437B - Inter-integrated circuit interface circuit and electronic module - Google Patents

Abstract

An Inter-Integrated Circuit, I2C, interface circuit comprises a clock input (SCLIN) for receiving a serial clock signal (scl), a clock output (SCLPAD) coupled to the clock input (SCLIN) by a first detection circuit (DET1), a data input (SDAIN) for receiving a serial data signal (sda), a data output (SDAPAD) coupled to the data input (SDAIN) by a second detection circuit (DET2) and a pulse generator (PGEN) configured to generate a clock pulse event at a symbol clock output (SYMCLK) in response to a trigger event. The first detection circuit (DET1) is configured to latch the serial clock signal (scl), to detect when a signal state at an input of the first detection circuit (DET1) becomes different to a signal state at the clock output (SCLPAD), and to effect the trigger event in response to such detection. The second detection circuit (DET2) is configured to latch the serial data signal (sda), to detect when a signal state at an input of the second detection circuit (DET2) becomes different to a signal state at the data output (SDAPAD), and to effect the trigger event in response to such detection while the latched serial clock signal is in a predefined signal state, e.g. in a high state.

Description

Internal integrated circuit interface circuit and electronic module

This disclosure relates to an internal integrated circuit "I2C" interface circuit. This disclosure further relates to electronic modules employing this I2C interface circuit. [Related Applications]

This patent application claims priority to U.S. Provisional Patent Application 63/493,102, the disclosure of which is incorporated herein by reference.

I2C is a two-wire bus. These two wires are typically referred to as SDA and SCL, which stand for Serial Data Line (SDA) and Serial Clock Line (SCL). One of the difficult states of this I2C protocol is that an event can be generated from the edge by either SDA or SCL.

This is one of the problems in structured digital design, which tends to rely heavily on events that trigger a single "clock" signal. In traditional systems, signals on the SDA and SCL lines are evaluated, for example, sampled at a clock rate higher than the changes in the signal state on these lines. Therefore, the edges used to determine an event can be identified. However, this approach is not feasible in low-power environments.

One of the objectives is to provide an improved interface concept that allows for reliable detection of changes in the signal state on the I2C bus.

This objective is achieved through a separate topic. Implementations and developments are derived from subsidiary items.

The improved interface concept is based on the idea that instead of directly evaluating edge or state transitions on the serial clock and data lines of the I2C bus, it provides an interface circuit with a pulse generator. This pulse generator generates an additional clock signal with clock pulse events based on the detection of changes in the signal state of the serial clock and data signals received from the I2C bus. This allows evaluation of the signal state on the serial data and clock lines, rather than the signal state changes when a clock pulse event is detected. Therefore, for evaluation purposes that allow for low-power applications, an oscillator with a higher timing clock signal is not required. Furthermore, it is possible to reliably detect signal events on the I2C bus.

In an example embodiment of an I2C interface circuit based on an improved interface concept, the interface circuit includes a clock input for receiving clock signals, such as the SCL line connected to an I2C bus. A clock output is coupled to the clock input via a first detection circuit. The interface circuit further includes a data input for receiving serial data signals, such as the SDA line coupled to an I2C bus. A data output is coupled to the data input via a second detection circuit. A pulse generator is configured to generate a clock pulse event at the symbolic clock output in response to a trigger event. The first detection circuit is configured to lock the serial clock signal to detect when the signal state at the input of the first detection circuit becomes different from the signal state at the clock output, and to trigger an event in response to this detection. The second detection circuit is configured to lock the serial data signal to detect when the signal state at the input of the second detection circuit becomes different from the signal state at the data output, and to trigger an event in response to this detection. Simultaneously, this locked serial clock signal is in a predetermined signal state, such as a high-energy state.

For example, the first and second detection circuits introduce delays with latching functionality. Therefore, the signal state at the input of the detection circuit can become different from the latching state at the corresponding output, for example, if the signal state on the corresponding line of the I2C bus changes. This change can be detected and trigger an event, thereby triggering the generation of a pulse event in the pulse generator.

Due to the I2C protocol specifications, if the signal state on the serial clock line has a predefined signal state, typically a higher energy state, then changes in the signal state on the serial data line only correspond to the predefined event. Therefore, under this condition of the latched serial clock signal state, the trigger event is only implemented by the second detection circuit.

In some embodiments, the second detection circuit is coupled to the data input via a delay element having a delay time selectable from a first delay and a second delay, wherein the first delay is shorter than the second delay, and the first delay is applied if the latched serial clock signal is not in the predetermined signal state defined above. According to the I2C protocol specifications, there are different requirements for the signal state change on the SDA line when the serial clock signal is high versus when the serial clock signal is low. Therefore, different delay times depending on the signal state of the latched serial clock signal take these requirements into account and introduce a safety margin required for each case.

In some embodiments of I2C interface circuits, a pulse generator is configured to generate a pulse event in a first intermediate signal at a first predetermined time period after a trigger event, a pulse event in a second intermediate signal at a second predetermined time period after the pulse event in the first intermediate signal, and a pulse event at the sign clock output at a third predetermined time period after the pulse event in the second intermediate signal. Thus, for example, by applying a series of delay elements, a pulse train having the first and second intermediate signals and the signal at the sign clock output can be generated. This not only allows the generation of clock pulse events at the symbol clock output, but also allows the use of intermediate signals to control the locking of signals at the clock input and data input.

For example, the first detection circuit includes a first pulse latching element and a second pulse latching element. The first pulse latching element has a first signal input coupled to an input of the first detection circuit and is configured to transfer a signal state at the first signal input in response to a pulse event in a first intermediate signal. The second pulse latching element has a second signal input coupled to a signal output of the first pulse latching element, a signal output coupled to a pulse output, and is configured to transfer a signal state at the second signal input in response to a pulse event in a second intermediate signal. Therefore, the signal state at the input of the first detection circuit is locked to its output in two steps controlled by the first and second intermediate signals and their respective pulse events.

The first detection circuit further includes an exclusive OR (XOR) gate, having a first input coupled to a first signal input of a first clock latching element, a second input coupled to a signal output of a second clock latching element, and an output for providing a logical output signal, which forms the basis for triggering the event. Therefore, if the signal state at the input of the first clock latching element or the first detection circuit differs from the signal state at the output of the first detection circuit or the clock output, only the logical value of the logical output signal can be high.

In some specific embodiments, the I2C interface circuit may include an enable input for receiving an enable signal, such as enabling and disabling at least one of a first detection circuit, a second detection circuit, and a pulse generator.

For example, the first and second clock latching elements of the first detection circuit are configured to output a low signal state at their respective signal outputs when the enable signal is in a low state. Therefore, when the enable signal is in a low state, latching of their respective signal states is not performed. In an alternative embodiment, the first and second clock latching elements are configured to output a high signal state at their respective signal outputs when the enable signal is in a low state.

In some embodiments, the second detection circuit includes first and second data latching elements. The first data latching element has a first signal input coupled to the input of the second detection circuit and is configured to relay a signal state at the first signal input in response to a pulse event in the first intermediate signal. The second data latching element has a second signal input coupled to the signal output of the first data latching element, a signal output coupled to the data output, and is configured to relay a signal state at the second signal input in response to a pulse event in the second intermediate signal. Therefore, similar to examples already described for the first detection circuit, the respective signal states are latched and relayed by pulse events in the first and second intermediate signals.

The second detection circuit may further include a mutex gate, having a first input coupled to a first signal input of the first data latching element, a second input coupled to a signal output of the second data latching element, and an output for providing a logic output signal that forms the basis for implementing the trigger event. As described above, if the inputs of the XOR gate have different signal states, the logic output signal can only have the higher energy state.

For example, the second detection circuit further includes an AND gate, having a first input coupled to the output of the XOR gate of the second detection circuit, a second input coupled to the signal output of the second clock latching element (or coupled to the clock output), and an output for providing a further logical output signal, which forms the basis for triggering the event. Therefore, if both the signal state provided by the XOR gate and the signal state of the clock output are high, only a trigger event will be generated.

In some embodiments, the first and second data latching elements are configured to output a high signal state at their respective signal outputs, while the enable signal is in a lower energy state if provided via an enable input.

In some embodiments, the pulse generator includes: a first delay element having a delay time corresponding to a first predetermined time period and configured to provide a first intermediate signal; and a second delay element having a delay time corresponding to a second predetermined time period, connected downstream of the first delay element and configured to provide a second intermediate signal. The pulse generator further includes a third delay element having a delay time corresponding to a third predetermined time period and connected between the second delay element and the symbol clock output. The OR gate has a first input for receiving a trigger event and a second input coupled to a connection between the first and second delay elements. The AND gate has a first input connected to the output of the OR gate, a second input for receiving an inverted version of the signal state at the output of the third delay element, and an output coupled to the first delay element.

For example, if the OR gate of the pulse generator receives a trigger event at its first input, its output will go high. As long as the output of the third delay element is in a lower energy state, the AND gate will transfer a higher energy state to the first delay element, initiating a pulse event in the pulse train, which ultimately appears at the output of the third delay element. Therefore, the higher energy state at the output of the third delay element results in the AND gate output corresponding to a lower energy state at the end of the pulse event in the pulse train. Furthermore, the end of the pulse event is ultimately delayed until the output of the third delay element or the sign pulse output.

In an embodiment of an I2C interface circuit including an enable input for receiving an enable signal, the delay time of the third delay element can be selected from a first delay and a second delay different from the first delay, depending on the signal state in the enable signal. For example, the first delay applied when the enable signal is in a lower energy state is shorter than the second delay. This improves the time used for stabilizing the signal at the symbol clock output, thereby reducing the minimum reset time required in the system.

In some embodiments of the I2C interface circuit, the first detection circuit is coupled to the clock input via a first pulse interference filter. Alternatively, the detection circuit is coupled to the data input via a second pulse interference filter. Optional pulse interference filters allow for the avoidance of pulse interference events on the I2C bus signal lines during evaluation.

In some embodiments, the I2C interface circuit further includes evaluation circuitry coupled to the clock output, data output, and symbolic clock output. The evaluation circuitry is configured to store the signal state at the clock output as the previous clock state when a clock pulse event is detected at the symbolic clock output. For example, the previous clock state supports the evaluation of signal state changes at both the clock output and data output.

For example, an evaluation circuit is configured to determine the event type when detecting a pulse event at the symbolic clock output, depending on the previous clock state and the signal state at the clock and data outputs.

For example, the event type is defined as follows: - START event: If the previous clock state was in a higher energy state, then the clock output is in a higher energy state, and the data output is in a lower energy state; - STOP event: If the previous clock state was in a higher energy state, then the clock output is in a higher energy state, and the data output is in a higher energy state; - DATA0 event: If the previous clock state was in a lower energy state, then the clock output is in a higher energy state, and the data output is in a lower energy state; and - For the DATA1 event, if the previous clock state was in a lower energy state, then the clock output and data output will both be in a higher energy state.

For example, if the previous clock state was in a higher energy state and the clock output was in a lower energy state, especially if it is unrelated to the data output state, the event type can also be identified as an SCLFE event.

The improved interface concept can be adopted in electronic modules that include an I2C interface according to one of the above embodiments. For example, the electronic module is a sensor module, such as for medical and/or health sensors.

These electronic modules can be used, for example, in mobile or wearable devices such as mobile phones or smartwatches.

The improved interface concept addresses the challenges of structured digital design, which strongly favors events that trigger a single "clock" signal, while comfortably achieving timed shutdown without requiring additional, higher-speed clocks. It can also be scaled to higher I2C bus rates, is highly modular, and can be easily designed for use with other products and technologies.

By developing a timing model for the pulse generator, the improved interface concept can demonstrate the timing shutdown of the entire I2C path, resulting in significant improvements to the interface and simplified timing shutdown. This solution also meets I2C high-speed specifications with very low standby power.

Figure 1 shows an example signal diagram of the serial data lines and serial clock lines of an I2C bus. As mentioned above, events can be generated by the edges or changes in the signal states on both lines. For example, when the serial clock line is in a higher energy state, the START event can be represented by a transition from a higher energy state to a lower energy state on the serial data line. Similarly, when the serial clock line is in a higher energy state, the STOP event can be represented by a signal transition from a lower energy state to a higher energy state on the serial data line.

A data event can be identified by the transition from a lower energy state to a higher energy state on a serial clock line. For example, if the serial data line is in a lower energy state during this transition, it represents a DATA0 event, or if the serial data line is in a higher energy state, it represents a DATA1 event. These events are defined, for example, in the I2C specification.

The transition from a higher energy state to a lower energy state on a serial clock line is usually negligible. However, according to this disclosure, a special event SCLFE can be represented corresponding to the negligible event.

The timing relationship between the serial data lines and serial clock lines on the I2C bus is crucial for determining their respective events. To avoid higher clock signals provided, for example by an oscillator, this disclosure provides an improved interface concept that provides a symbolic clock signal corresponding to a pulse event that changes the signal state on the serial data lines and serial clock lines.

For example, Figure 2 shows an exemplary embodiment of an I2C interface circuit according to an improved interface concept, including a clock input SCLIN for receiving the serial clock signal scl, which is coupled to the clock output SCLPAD via a first detection circuit DET1. A data input SDAIN for receiving the serial data signal sda is coupled to the data output SDAPAD via a second detection circuit DET2. A pulse generator PGEN is configured to generate a clock pulse event at the symbolic clock output SYMCLK in response to a trigger event in the trigger signal syken. The first detection circuit DET1 is configured to latch the serial clock signal scl from its input to its output, for example, depending on the intermediate signal syph. This means that the signal status at the input of the first detection circuit DET1 is only displayed at its output after the first detection circuit DET1 is triggered by the intermediate signal syph.

Similarly, the second detection circuit DET2 is configured to latch the serial data signal sda from its input to its output, for example, also based on the intermediate signal syph. Since both detection circuits DET1 and DET2 are triggered by the same signal syph, their latching occurs in a time-synchronized manner.

The first detection circuit DET1 is further configured to detect when the signal state at its input changes from the signal state at its output or clock output SCLPAD, and to trigger an event in response to this detection. Similarly, the second detection circuit DET2 is further configured to detect when the signal state at its input changes from the signal state at its output or data output SDAPAD, and to trigger an event in response to this detection. For example, the trigger event is only triggered when the latched serial clock signal at the output of the first detection circuit DET1 is in a predetermined signal state, such as a higher energy state. For this purpose, the second detection circuit DET2 is coupled to the output of the first detection circuit DET1.

The corresponding detections of different signal states in the first and second detection circuits DET1 and DET2 are transferred to the OR gate OR1 to trigger an event in the trigger signal syken output by the OR gate OR1.

Figure 3 shows an example pulse generator PGEN that can be used in the I2C interface circuit of Figure 2. The pulse generator PGEN includes a first delay element DG1, which has a delay time corresponding to a first predetermined time period and is configured to provide a first intermediate signal syph1, which may be part of the signal syph described in conjunction with Figure 2. The pulse generator further includes a second delay element DG2, which is connected downstream of the first delay element DG1 and configured to provide a second intermediate signal syph2, which may also be part of the signal syph. The second delay element has a delay time corresponding to a second predetermined time period. The first and second predetermined time periods may be equal.

The third delay element DG3 is connected downstream of the second delay element DG2 and provides its output to the symbol clock output SYMCLK.

The pulse generator PGEN further includes an OR gate OR2, which has a first input for receiving a trigger signal syken with a trigger event, and a second input coupled to the connection between the first delay element DG1 and the second delay element DG2. The AND gate AND1 has a first input connected to the output of the OR gate OR2, a second input for receiving the signal or an inverted version of the signal state at the pulse output SYMCLK when the third delay element DG3 is output or a sign, and an output coupled to the input of the first delay element DG1. The detailed function of the pulse generator PGEN in Figure 3 will be explained through example signal diagrams of the respective signals used in the pulse generator PGEN.

For example, once the signal state of the trigger signal syken changes to a higher energy state, the output of OR gate OR2 also goes high, regardless of the signal state at the output of the first delay element DG1 or the first intermediate signal syph1. Assuming the sign clock signal at the sign clock output SYMCLK is in a lower energy state, the output of AND gate AND1 also goes high. In this example, after a first predetermined time interval, denoted as D15, the first intermediate signal syph1 goes high at the output of the first delay element DG1. Similarly, after a second predetermined time interval, also denoted as D15, the second intermediate signal syph2 goes high at the output of the second delay element DG2. Therefore, in this example implementation, the first and second predetermined time periods are chosen to be equal. However, this example does not exclude different delay times.

Finally, after the third predetermined time interval, represented as D100 in this example, the output of the third delay element DG3 goes high. Therefore, the output of the AND gate AND1 goes low, and after the first predetermined time interval, the first intermediate signal syph1 also goes low. The lower energy state propagates through the second delay element DG2 and the third delay element DG3.

As can be seen from Figure 4, the trigger event in response to the trigger signal syken is used to activate the pulse train by passing the first and second intermediate signals syph1 and syph2 and the sign clock output SYMCLK. The length of the pulse event is determined by the sum of the first, second and third predetermined time intervals.

Referring back to Figure 2, the signal states of the serial data signal sda and the serial clock signal scl are transmitted to the clock output SCLPAD and the data output SDAPAD in a time-synchronized manner. Similarly, a pulse event is generated at the symbol clock output SYMCLK in a synchronous manner, with only a third predetermined time delay in this example. This allows for reliable detection of the signal states of the latched serial clock signal and the latched serial data signal based on pulse events.

Referring now to Figure 5, a more detailed example embodiment of the I2C interface circuit is described, based on the embodiment of Figure 2 in conjunction with Figure 3. Therefore, only configurations not previously described will be discussed in more detail here. For example, the first detection circuit DET1 and the second detection circuit DET2 are coupled to the clock input SCLIN and the data input SDAIN respectively via their respective pulse interference filters GL1 and GL2, which are configured, for example, to suppress pulse interference effects on their respective signal lines. Furthermore, a generally optional fourth delay element DG4 is coupled between the second pulse interference filter GL2 and the second detection circuit DET2. The fourth delay element DG4 has a delay time selectable from a first delay and a second delay, wherein the first delay is shorter than the second delay, and this delay time is applied if the latched serial clock signal at the clock output SCLPAD is not in a predetermined signal state, such as in a higher energy state. For example, the first delay D5 is 20 times shorter than the second delay D100. When the serial clock line is high, the delay element DG4 can increase the reliability after signal state evaluation due to the different requirements of the I2C protocol on the serial data lines when the serial clock line is low.

Furthermore, in this example embodiment, an optional enable input RSIN is included to provide an enable signal rstn, which is in a higher energy state when the interface circuit should be enabled and in a lower energy state when the interface circuit should be disabled. If the optional enable input is omitted, the signal state of the enable signal rstn is simply assumed to be in a higher energy state regardless of where it is applied.

Therefore, in this example, the output of AND gate AND2 has an input connected to the enable input RSIN and an input connected to the clock output SCLPAD. The selection of the delay time in the fourth delay element DG4 depends not only on the signal state at the clock output SCLPAD, but also on the enable signal rstn.

Further referring to the embodiment of the pulse generator PGEN described in Figure 3, the pulse generator PGEN includes an input for receiving a selectable enable signal rstn, which is provided as a third input for selecting the delay time to the AND gate AND1 and the third delay element DG3. Therefore, if the enable signal rstn is in a lower energy state, the output of the AND gate AND1 will never go high. The selection method of the delay time of the third delay element DG3 corresponds to the selection in the delay element DG4, although the third delay element DG3 can be implemented differently and/or with different delay times compared to the delay element DG4.

The first detection circuit DET1 includes a first clock latching element FFC1 and a second clock latching element FFC2, both of which can be implemented as gate latches or flip-flops. The first clock latching element FFC1 couples its signal input to the clock input SCLIN and its output to the signal input of the second clock latching element FFC2. The signal output of the second clock latching element FFC2 is sequentially connected to the clock output SCLPAD. The first clock latching element FFC1 is triggered or gated by a first intermediate signal syph1, while the second clock latching element FFC2 is triggered or gated by a second intermediate signal syph2. Therefore, the signal state at the input of the first detection circuit DET1 is transferred to its output in two steps. This allows the first XOR gate XOR1 to detect when the signal state at the input of the first detection circuit DET1 becomes different from the signal state at the clock output SCLPAD, and only in this case will a higher energy state be output by the signal SCLKEN as the basis for the trigger event in the trigger signal syken.

Similarly, the second detection circuit DET2 includes a first data latching element FFD1 and a second data latching element FFD2, which can also be implemented as a gate latch or a flip-flop. The first data latching element FFD1, which transmits the signal state at the output of the delay element DG4, is triggered by a first intermediate signal syph1, and the second data latching element FFD2, which transmits the signal state at the output of the first data latching element FFD1 to the data output SDAPAD, is triggered by a second intermediate signal syph2.

The second XOR gate, XOR2, makes the signal state between the input and output of the second detection element, DET2, different. The output of XOR gate XOR2 is coupled to AND gate AND3, which in turn couples the second input of AND gate AND3 to the clock output SCLPAD. Therefore, if the clock output SCLPAD is in a higher energy state, only the basis for triggering the event is transferred in the signal SDAKEN. This is because, referring to Figure 1, signal conversion on the serial data lines is only relevant in this case. The output of AND gate AND3 is coupled to OR gate OR1.

To initialize the signal states at the clock output SCLPAD and data output SDAPAD when the interface circuit is enabled, latching elements FFC1, FFC2, FFD1, and FFD2 each include an initialization input with an enable signal rstn or an inverted version of this enable signal rstn. Therefore, as long as the enable signal rstn is in a lower energy state, corresponding to the deactivation of the interface circuit, a fixed output state is imposed on the latching element. If the enable signal rstn transitions to a higher energy state, the imposed signal state remains until the first or second intermediate signals syph1 and syph2 trigger potential changes.

In the exemplary embodiment shown in Figure 5, the first and second clock latching elements FFC1 and FFC2 have a preselection with a low signal state, while the first and second data latching elements FFD1 and FFD2 have a preselection with a higher energy state.

Referring now to Figure 6, an alternative to the embodiment shown in Figure 5 is described. However, the only difference lies in the type of preselection implemented in the first clock latching element FFC1 and the second clock latching element FFC2. Instead of the lower-energy state preselection implemented as in Figure 5, the I2C interface circuit of Figure 6 features higher-energy state preselection characteristics for these latching elements FFC1 and FFC2.

Figure 7 shows an example block diagram of an evaluation circuit that may be part of an I2C interface circuit according to one of the above embodiments. The evaluation circuit EVAL has a first block EV1 connected to the clock output SCLPAD and triggered by a pulse event occurring on the symbolic clock output SYMCLK. Therefore, the evaluation circuit EVAL is configured to store the signal state at the clock output SCLPAD as the previous clock state prevscl when a clock pulse event is detected at the symbolic clock output SYMCLK. The second block EV2 in the evaluation circuit EVAL is configured to determine the event type when a clock pulse event is detected at the symbol clock output SYMCLK, depending on the previous clock state prevscl and the signal states at the clock output SCLPAD and data output SDAPAD. For example, the event type is determined according to the scheme in the table below. prevscl SCLPAD SDAPAD Event Type 0 1 0 Data 0 0 1 1 Data 1 1 1 0 Start 1 1 1 stop 1 0 X SCLFE

Here, 0 indicates a lower energy state, 1 indicates a higher energy state, and X indicates that the state is not evaluated. It should be noted that after simultaneous triggering of blocks EV1 and EV2, the changes in the stored previous clock state prevscl only become valid with the next pulse event on the symbolic clock output SYMCLK. The output of the evaluation circuit EVAL can be further processed to combine with data bytes sent via the I2C bus for further processing. Various embodiments for this subsequent processing are well known in the art.

Figure 8 shows an electronic module 800 including an I2C interface 200 according to one of the above embodiments. For example, the electronic module 800 is a sensor module, such as a medical sensor module and/or a health sensor module.

These electronic modules can be implemented in various electronic devices, especially in mobile devices or wearable devices, such as mobile phones or smartwatches.

For the purpose of familiarizing the reader with the novelty of embodiments of this improved concept, embodiments of the improved interface concept disclosed herein have been discussed. Although preferred embodiments have been shown and described, those skilled in the art can make many changes, modifications, equivalents, and substitutions to the disclosed concepts without departing from the scope of the claim.

In particular, embodiments of the improved interface concept are not limited to the disclosed embodiments, and many possible alternatives to the features included in the embodiments under discussion are given. However, it is intended that any modifications, equivalents, and substitutions of the disclosed concept be included within the scope of the appended claims.

Features listed in separate subordinate items can be advantageously combined. Furthermore, reference symbols used in a request are not limited to those interpreted as restricting the scope of the request.

Furthermore, as used herein, the word "comprising" does not exclude other elements. Additionally, as used herein, the article "one" is intended to include more than one part or element, and is not limited to being interpreted as meaning only one.

START, STOP: Events DATA0, DATA1: Events sda: Serial data signal scl: Serial clock signal SDAIN, SCLIN, RSIN: Inputs SDAPAD, SCLPAD, SYMCLK: Outputs DET1, DET2: Detection circuits PGEN: Pulse generator syph, syph1, syph2: Intermediate signals syken: Trigger event signal OR1, OR2: OR gate AND1, AND2, AND3: AND gate DG1, DG2, DG3, DG4: Delay components XOR1, XOR2: XOR gate FFC1, FFC2, FFD1, FFD2: Latching components GL1, GL2: Pulse interference filters rstn: Enable signal EVAL: Evaluation circuit prevscl: Previous clock state 200: I2C interface 800: Electronic module

The improved interface concept will be explained in more detail below with the help of the accompanying drawings. Throughout these drawings, components and function blocks with the same or similar functions use the same reference numbers. Therefore, their descriptions need not be repeated in the drawings below.

In the accompanying figures: Figure 1 shows an example signal diagram of a signal on an I2C bus; Figure 2 shows an example embodiment of an I2C interface circuit; Figure 3 shows an example pulse generator for an I2C interface circuit; Figure 4 shows an example timing diagram of a signal used in the pulse generator of Figure 3; Figure 5 shows a further example embodiment of an I2C interface circuit; Figure 6 shows a further example embodiment of an I2C interface circuit; Figure 7 shows an example block diagram of an evaluation circuit for an I2C interface circuit; and Figure 8 shows an example embodiment of an electronic module.

sda: serial data signal

scl: Serial clock signal

SDAIN, SCLIN: Input

SDAPAD, SCLPAD, SYMCLK: Output

DET1, DET2: Detection circuits

PGEN: Pulse Generator

syph: intermediate signal

syken: Triggers an event signal

OR1, OR2: OR gate

Claims (16)

An internal integrated circuit (I2C) interface circuit includes: - a clock input (SCLIN) for receiving a serial clock signal (scl); - a clock output (SCLPAD) coupled to the clock input (SCLIN) via a first detection circuit (DET1); - a data input (SDAIN) for receiving a serial data signal (sda); - a data output (SDAPAD) coupled to the data input (SDAIN) via a second detection circuit (DET2); and - a pulse generator (PGEN) configured to generate a clock pulse event at the symbol clock output (SYMCLK) in response to a trigger event; wherein - The first detection circuit (DET1) is configured to latch the serial clock signal (SCL) to detect when the signal state at the input of the first detection circuit (DET1) changes from the signal state at the clock output (SCLPAD), and to respond to this detection by executing the trigger event; and - The second detection circuit (DET2) is configured to lock the serial data signal (sda) to detect when the signal state at the input of the second detection circuit (DET2) becomes different from the signal state at the data output (SDAPAD), and to respond to this detection by performing the trigger event when the locked serial clock signal is in a predetermined signal state, especially in a higher energy state. As in the I2C interface circuit of claim 1, the second detection circuit (DET2) is coupled to the data input (SDAIN) via a delay element (DG4), the delay element (DG4) having a delay time selectable by a first delay and a second delay, the first delay being shorter than the second delay, and the first delay being applied if the serial clock signal of the latch is not in the predetermined signal state. The I2C interface circuit of claim 1, wherein the pulse generator (PGEN) is configured to: - generate a pulse event in a first intermediate signal (syph1) at a first predetermined time period after the trigger event; - generate a pulse event in a second intermediate signal (syph2) at a second predetermined time period after the pulse event in the first intermediate signal (syph1); and - generate a clock pulse event at the symbol clock output (SYMCLK) at a third predetermined time period after the pulse event in the second intermediate signal (syph2). As in claim 3, the I2C interface circuit, wherein the first detection circuit (DET1) includes: - a first pulse latching element (FFC1) having a first signal input coupled to the input of the first detection circuit (DET1) and configured to transfer a signal state at the first signal input in response to a pulse event in the first intermediate signal (syph1); - a second pulse latching element (FFC2) having a second signal input coupled to the signal output of the first pulse latching element (FFC1), having a signal output coupled to the pulse output (SCLPAD), and configured to transfer a signal state at the second signal input in response to a pulse event in the second intermediate signal (syph2); and - The mutex gate (XOR1) has a first input coupled to a first signal input of the first clock latching element (FFC1), a second input coupled to a signal output of the second clock latching element (FFC2), and an output for providing a logic output signal that forms the basis for performing the triggering event. The I2C interface circuit of claim 4 further includes an enable input (RSIN) for receiving an enable signal (rstn), wherein the first and second clock latching elements (FFC1, FFC2) are configured to output a low signal state at their respective signal outputs while the enable signal (rstn) is in a lower energy state. The I2C interface circuit of claim 4 further includes an enable input (RSIN) for receiving an enable signal (rstn), wherein the first and second clock latching elements (FFC1, FCC2) are configured to output a high signal state at their respective signal outputs while the enable signal (rstn) is in a lower energy state. The I2C interface circuit according to any one of claims 3 to 6, wherein the second detection circuit (DET2) comprises: - a first data latching element (FFD1) having a first signal input coupled to the input of the second detection circuit (DET2) and configured to transfer a signal state at the first signal input in response to a pulse event in the first intermediate signal (syph1); - a second data latching element (FFD2) having a second signal input coupled to the signal output of the first data latching element (FFD1), having a signal output coupled to the data output (SDAPAD), and configured to transfer a signal state at the second signal input in response to a pulse event in the second intermediate signal (syph2); and - The mutex gate (XOR2) has a first input coupled to a first signal input of the first data latching element (FFD1), a second input coupled to a signal output of the second data latching element (FFD2), and an output for providing a logic output signal that forms the basis for performing the triggering event. As in claim 7, the I2C interface circuit, wherein the second detection circuit (DET2) further includes an AND gate (AND3), having a first input coupled to the output of the XOR gate (XOR2) of the second detection circuit (DET2), a second input coupled to the clock output (SCLPAD), and an output for providing a logic output signal that is the basis for implementing the trigger event. The I2C interface circuit of claim 7 further includes an enable input (RSIN) for receiving an enable signal (rstn), wherein the first and second data latching elements (FFD1, FFD2) are configured to output a high signal state at their respective signal outputs when the enable signal (rstn) is in a lower energy state. As in claim 3, the I2C interface circuit, wherein the pulse generator (PGEN) comprises: - a first delay element (DG1) having a delay time corresponding to the first predetermined time period and configured to provide the first intermediate signal (syph1); - a second delay element (DG2) having a delay time corresponding to the second predetermined time period, connected downstream of the first delay element (DG1) and configured to provide the second intermediate signal (syph2); and - a third delay element (DG3) having a delay time corresponding to the third predetermined time period and connected between the second delay element (DG2) and the symbol clock output (SYMCLK); OR gate (OR2) has a first input for receiving the trigger event and a second input coupled to the connection between the first delay element (DG1) and the second delay element (DG2); and AND gate (AND1) has a first input coupled to the output of OR gate (OR2), a second input for receiving an inverted version of the signal state at the output of the third delay element (DG3), and an output coupled to the first delay element (DG1). The I2C interface circuit of claim 10 further includes an enable input (RSIN) for receiving an enable signal (rstn), wherein the delay time of the third delay element (DG3) can be selected from a first delay and a second delay, the second delay being different from the first delay and depending on the signal state of the enable signal (rstn). As in the I2C interface circuit of claim 1, the first detection circuit (DET1) is coupled to the clock input (SCLIN) via a first pulse interference filter (GL1), and/or the second detection circuit (DET2) is coupled to the data input (SDAIN) via a second pulse interference filter (GL2). The I2C interface circuit of claim 1 further includes an evaluation circuit (EVAL) coupled to the clock output (SCLPAD), the data output (SDAPAD), and the symbol clock output (SYMCLK), wherein the evaluation circuit (EVAL) is configured to, when a clock event is detected at the symbol clock output (SYMCLK), store the signal state at the clock output (SCLPAD) as the previous clock state (prevscl). As in the I2C interface circuit of claim 13, the evaluation circuit (EVAL) is configured to determine an event type when a pulse event is detected at the symbolic clock output (SYMCLK) depending on the previous clock state (prevscl) and the signal state at the clock output (SCLPAD) and the data output (SDAPAD), wherein the event type is determined as: - START event, where if the previous clock state (prevscl) is in a higher energy state, then the clock output (SCLPAD) is in a higher energy state, and the data output (SDAPAD) is in a lower energy state; - The STOP event occurs when both the current clock output (SCLPAD) and data output (SDAPAD) are in a higher energy state if the previous clock state (prevscl) was in a higher energy state; the DATA0 event occurs when both the current clock output (SCLPAD) and data output (SDAPAD) are in a higher energy state if the previous clock state (prevscl) was in a lower energy state; and the DATA1 event occurs when both the previous clock state (prevscl) and current clock output (SCLPAD) are in a higher energy state if the previous clock state (prevscl) was in a lower energy state. An electronic module (800) includes an I2C interface as described in any of requests 1 to 14. Such as the electronic module (800) of claim 15, wherein the electronic module (800) is a sensor module.