TWI836374B - Sense amplifier and operation method thereof - Google Patents

Abstract

The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.

Description

Sense Amplifiers and Methods of Operation

The present invention relates to an induction amplifier and an operating method thereof.

For non-volatile memory, as the size of memory devices shrinks and the operating voltage decreases, but the critical voltage is maintained at the same level, non-volatile memory encounters a problem of increasingly smaller read margins.

The required sensing limit for non-volatile memory is determined by the sense amplifier offset and the bit line voltage offset. Sense amplifier deviation is caused by device mismatch caused by process variation. Bit line voltage deviation is caused by noise, bias and bit line load mismatch. As device size decreases, overcoming these issues has become a major challenge for read operations of non-volatile memories with smaller read limits.

Due to these deviations, non-volatile memory encounters problems of slow read speed or high read failure rate. Therefore, in order to achieve good read operation of non-volatile memory, how to develop a sense amplifier with better deviation tolerance is one of the directions of the industry's efforts.

Based on an example of this case, an operation method of the induction amplifier is proposed. The operation method of the sense amplifier includes: in a first stage, initializing a first sense input voltage and a second sense input voltage in the sense amplifier, and using a plurality of transistors stored in the sense amplifier The charge in the body is used to record a first inductive output voltage and a second inductive output voltage in the previous round; in a second stage, the first inductive output voltage and the second inductive output voltage in the current round are sampled. into a plurality of transition points; in a first sub-stage of a third stage, amplifying a voltage difference between an input signal and a first reference voltage; and in a second sub-stage of the third stage Within, the first sensing output voltage and the second sensing output voltage are stretched to a full swing voltage range, and charges are recorded to the transistors.

According to another embodiment of the present invention, a sensing amplifier is provided, comprising: a plurality of transistors; and a plurality of transmission gates coupled to the transistors; wherein, in a first stage, a first sensing input voltage and a second sensing input voltage in the sensing amplifier are initialized, and the charges stored in the transistors are used to record a first sensing output voltage and a second sensing output voltage in a previous round; and in a second stage In a first sub-stage of a third stage, the first sensing output voltage and the second sensing output voltage of a current round are sampled into a plurality of transition points; in a first sub-stage of a third stage, a voltage difference between an input signal and a first reference voltage is amplified; and in a second sub-stage of the third stage, the first sensing output voltage and the second sensing output voltage are pulled apart to a full swing voltage range, and the charge is recorded to the transistors.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

100: Inductive amplifier

M1-M8: Transistor

PG1-PG18: Transmission gate

CL, CR: capacitor

P0, P1, P2: stages

P2-1, P2-2: sub-stage

710-740: Steps

Figure 1A shows a circuit diagram of an inductive amplifier according to an embodiment of the present invention.

Figure 1B shows the signal waveform of the inductive amplifier according to an embodiment of the present invention.

Figure 2A shows a schematic diagram of the operation of the sense amplifier in the first stage according to an embodiment of the present invention.

Figure 2B shows the signal waveform of the inductive amplifier in the first stage according to an embodiment of the present invention.

Figure 3A shows a schematic diagram of the operation of the sense amplifier in the second stage according to an embodiment of the present invention.

Figure 3B shows the signal waveform diagram of the sense amplifier in the second stage according to an embodiment of the present invention.

Figure 4A shows a schematic diagram of the operation of the sense amplifier in the first sub-stage of the third stage according to an embodiment of the present invention.

Figure 4B shows the signal waveform of the first sub-stage of the third stage of the inductive amplifier according to an embodiment of the present invention.

Figure 5A shows a schematic diagram of the operation of the inductive amplifier in the second sub-stage of the third stage according to an embodiment of the present invention.

Figure 5B shows the signal waveform of the inductive amplifier in the second sub-stage of the third stage according to an embodiment of the present invention.

Figure 6A shows a schematic diagram of the operation of the sense amplifier in the first stage of the next round according to an embodiment of the present invention.

Figure 6B shows the signal waveform of the inductive amplifier in the first stage of the next round according to an embodiment of the present case.

Figure 7 shows a flow chart of the inductive amplifier operation method according to an embodiment of the present invention.

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

FIG. 1A shows a circuit diagram of an inductive amplifier according to an embodiment of the present invention. FIG. 1B shows a signal waveform diagram of an inductive amplifier according to an embodiment of the present invention. CLK is a clock signal.

The sense amplifier 100 is used to compare the input signal IN with the first reference voltage VREF, and output the comparison result. For example, but not limited to, when the input signal IN is higher than the first reference voltage VREF, the sense amplifier 100 outputs the first sense output voltage SAOL of the first logic state (eg, but not limited to, logic low) and the second logic state ( For example, but not limited to, a logic high) second sense output voltage SAOR. When the input signal IN is lower than the first reference voltage VREF, the sense amplifier 100 outputs The first sensing output voltage SAOL of the second logic state and the second sensing output voltage SAOR of the first logic state are output. Details of the operation of the sense amplifier 100 will be described below.

The sense amplifier 100 according to an embodiment of the present invention includes a plurality of transistors, a plurality of pass gates and a plurality of capacitors. Here, the sense amplifier 100 including the first to eighth transistors M1 - M8 , the first to 18th transmission gates PG1 - PG18 , the first capacitor CL and the second capacitor CR is used as an example for explanation. However, it should be noted that this case does not Limited by this.

The first transistor M1 has: a first terminal (such as but not limited to a source terminal) coupled to the fifth transistor M5; a second terminal (such as but not limited to a drain terminal) coupled to the first sensing output voltage SAOL; and a control terminal (such as but not limited to a gate terminal) coupled to the first sensing input voltage SAIL.

The second transistor M2 has: a first end coupled to the sixth transistor M6; a second end coupled to the second sensing output voltage SAOR; and a control end coupled to the second sensing input voltage SAIR.

The third transistor M3 has: a first end coupled to the seventh transistor M7; a second end coupled to the first sensing output voltage SAOL; and a control end coupled to the first sensing input voltage SAIL.

The fourth transistor M4 has: a first end coupled to the eighth transistor M8; a second end coupled to the second sensing output voltage SAOR; and a control end coupled to the second sensing input voltage SAIR.

The fifth transistor M5 has: a first terminal coupled to the ground terminal (VSS); The second terminal is coupled to the first transistor M1; and the control terminal is selectively coupled to the second sensing output voltage SAOR and selectively coupled to the operating voltage (VDD).

The sixth transistor M6 has: a first end coupled to the ground end (VSS); a second end coupled to the second transistor M2; and a control end selectively coupled to the first sensing output voltage SAOL and selectively coupled to the operating voltage (VDD).

The seventh transistor M7 has: a first end coupled to the operating voltage (VDD); a second end coupled to the third transistor M3; and a control end selectively coupled to the second sensing output voltage SAOR and selectively coupled to the ground end.

The eighth transistor M8 has: a first terminal coupled to the operating voltage (VDD); a second terminal coupled to the fourth transistor M4; and a control terminal selectively coupled to the first sense output voltage SAOL and selectively coupled to the ground terminal.

The operating voltage (VDD) can also be called the second reference voltage, and the ground terminal (VSS) can also be called the third reference voltage.

The first transmission gate PG1 is coupled between the operating voltage VDD and the first sensing input voltage SAIL. The first transmission gate PG1 is controlled by the inverted signal SOB of the first switching signal S0.

The second transmission gate PG2 is coupled between the operating voltage VDD and the second sensing input voltage SAIR. The second transmission gate PG2 is controlled by the inverted signal S0B of the first switch signal S0.

The third transmission gate PG3 is coupled between the control terminal of the seventh transistor M7 and the second sense output voltage SAOR. The third transmission gate PG3 is controlled by the third switch signal S2.

The fourth transmission gate PG4 is coupled between the control terminal of the eighth transistor M8 and the first sensing output voltage SAOL. The fourth transmission gate PG4 is controlled by the third switch signal S2.

The fifth transmission gate PG5 is coupled between the control terminal of the fifth transistor M5 and the second sense output voltage SAOR. The fifth transmission gate PG5 is controlled by the third switch signal S2.

The sixth transmission gate PG6 is coupled between the control terminal of the sixth transistor M6 and the first sense output voltage SAOL. The sixth transmission gate PG6 is controlled by the third switch signal S2.

The seventh transmission gate PG7 is coupled between the first end of the third transistor M3 and the first sensing output voltage SAOL. The seventh transmission gate PG7 is controlled by the inverted signal S0B of the first switch signal S0.

The eighth transmission gate PG8 is coupled between the first end of the fourth transistor M4 and the second sensing output voltage SAOR. The eighth transmission gate PG8 is controlled by the inverted signal S0B of the first switch signal S0.

The ninth transmission gate PG9 is coupled between the first sensing input voltage SAIL and the first sensing output voltage SAOL. The ninth transmission gate PG9 is controlled by the second switch signal S1.

The tenth transmission gate PG10 is coupled between the second sensing input voltage SAIR and the second sensing output voltage SAOR. The tenth transmission gate PG10 is controlled by the second switch signal S1.

The eleventh transmission gate PG11 is coupled between the operating voltage and the fifth transistor. Between the M5 console. The eleventh transmission gate PG11 is controlled by the second switch signal S1.

The twelfth transmission gate PG12 is coupled between the operating voltage and the control terminal of the sixth transistor M6. The twelfth transmission gate PG12 is controlled by the second switch signal S1.

The thirteenth transmission gate PG13 is coupled between the ground terminal and the control terminal of the seventh transistor M7. The thirteenth transmission gate PG13 is controlled by the second switch signal S1.

The fourteenth transmission gate PG14 is coupled between the ground terminal and the control terminal of the eighth transistor M8. The fourteenth transmission gate PG14 is controlled by the second switch signal S1.

The fifteenth transmission gate PG15 is coupled between the reference voltage VREF and the first capacitor CL. The fifteenth transmission gate PG15 is controlled by the first switch signal S0 and the third switch signal S2. Among them, "S0 and S2" represent the signals generated by passing the switch signals S0 and S2 through the "AND Gate".

The sixteenth transmission gate PG16 is coupled between the input signal IN and the second capacitor CR. The sixteenth transmission gate PG16 is controlled by the first switch signal S0 and the third switch signal S2.

The seventeenth transmission gate PG17 is coupled between the control terminal of the first transistor M1 and the first capacitor CL. The seventeenth transmission gate PG17 is controlled by the second switch signal S1.

The eighteenth transmission gate PG18 is coupled between the control terminal of the second transistor M2 and the second capacitor CR. The eighteenth transmission gate PG18 is controlled by the second switch signal S1.

Each of the first transmission gate PG1 to the eighteenth transmission gate PG18 can be composed of a single metal-oxide-semiconductor field-effect transistor (MOSFET) or two MOSFETs, which are all within the spirit of the present invention.

The first capacitor CL is coupled between the first node PIL and the first sensing output voltage SAOL. The second capacitor CR is coupled between the second node PIR and the second sensing output voltage SAOR.

In an embodiment of this case, within a single round, the operation of the sense amplifier 100 can be divided into the first stage P0, the second stage P1 and the third stage P2, wherein the third stage P2 can be divided into the first sub-stage P2 -1 and the second sub-stage P2-2.

Figure 2A shows a schematic diagram of the operation of the sense amplifier in the first stage according to an embodiment of the present invention. Figure 2B shows a signal waveform diagram of the sense amplifier in the first stage according to an embodiment of the present invention.

When the enable signal INI_EN is enabled (for example but not limited to, transitioning from a logic low to a logic high), the sense amplifier 100 starts to sense the signal. After the enable signal INI_EN is enabled, the switch signals S0 and S1 remain at a logic low (but the inverted signal S0B of the first switch signal S0 is a logic high), but the switch signal S2 transitions from a logic high to a logic low. In response to the inverted signal S0B of the first switch signal S0 being a logic high, the transmission gates PG1, PG2, PG7 and PG8 are turned on, and the other transmission gates are turned off. Since the transmission gates PG1 and PG2 are turned on, the first sensing input voltage SAIL and the second sensing input voltage SAIR are equal to the operating voltage VDD (VSAIL=VSAIR=VDD).

In the first stage P0, because the first sense input voltage SAIL and The second sensing input voltage SAIR is equal to the operating voltage, the transistors M1 and M2 are on but the transistors M3 and M4 are off. In addition, transistors M5 to M8 are turned off.

In addition, in the first stage, the first sensing output voltage SAOL and the second sensing output voltage SAOR of the previous round are recorded by the charges in the gates of the fifth transistor M5 to the eighth transistor M8. Here, "recording" means maintaining the potentials of the first sensing output voltage SAOL and the second sensing output voltage SAOR of the previous round.

In the first phase P0, the input signal IN remains at logic high and the reference voltage VREF changes state (for example, but is not limited to, from logic high to logic low).

In the first phase P0, since the transmission gates PG15 and PG16 are disconnected, the potentials of the first node PIL and the second node PIR do not change. Since the potentials of the first node PIL and the second node PIR do not change, the first sensing input voltage SAIL and the second sensing input voltage SAIR do not change, and the first sensing output voltage SAOL and the second sensing output voltage SAOR do not change.

In the first stage P0, the first sense input voltage SAIL and the second sense input voltage SAIR are initialized (VSAIL=VSAIR=VDD), and the charges stored in the fifth transistor M5 to the eighth transistor M8 are used. To record the first inductive output voltage SAOL and the second inductive output voltage SAOR in the previous round.

FIG. 3A shows a schematic diagram of the operation of the inductive amplifier in the second stage according to an embodiment of the present invention. FIG. 3B shows a signal waveform diagram of the inductive amplifier in the second stage according to an embodiment of the present invention.

In the second stage P1, the transition point (Vtri-point) is sampled. That is, in the second stage P1, the signal paths on both sides (one signal path includes transistors M1, M3, M5, and M7, and the other signal path includes transistors M2, M4, M6, and M8) are sampled separately. transition point.

Here is an explanation of what a turning point is.

In FIG. 1A, transistors M1 and M3 can be considered to form an inverter. Assume that the source of transistor M3 is connected to the operating voltage VDD, and the source of transistor M1 is connected to the ground terminal VSS. If the first sensing input voltage SAIL is a logical 1, the first sensing output voltage SAOL is a logical 0, and vice versa.

During the transition of the first sensing input voltage SAIL from logic 1 to logic 0, when the first sensing input voltage SAIL drops from logic 1 to (1/2)*VDD, the first sensing output voltage SAOL will change from logic 0 to Instantly transitions to logic 1. Therefore, in this embodiment, the input voltage that can cause the output voltage to instantaneously transition is called the transition point.

However, when there is process variation, the instantaneous transition point of the first sense output voltage SAOL may not necessarily be when the first sense input voltage SAIL drops to (1/2)*VDD, that is, it may be When the first sensing input voltage SAIL has not dropped to (1/2)*VDD (VSAIL=(1/2)*VDD+△, △ is a positive voltage), the first sensing output voltage SAOL changes state instantaneously, or it may be When the first sensing input voltage SAIL must drop below (1/2)*VDD (VSAIL=(1/2)*VDD-△), the first sensing output voltage SAOL will instantaneously change state. That is, the instantaneous transition of the first inductive input voltage SAIL The status point may change upward or downward (△), and such changes may cause misjudgment.

Therefore, in an embodiment of this case, in order to avoid such misjudgment, sampling of instantaneous transition points is performed in the second stage P1. This will be explained in detail below.

In the second phase P1, the first switch signal S0 and the second switch signal S1 transition from logic low to logic high, while the third switch signal S2 is still logic low.

Therefore, transmission gates PG9, PG11, PG13, PG17, PG10, PG12, PG14 and PG18 are turned on, and the remaining transmission gates are turned off.

In addition, in the previous stage (that is, in the first stage P0), since the first sensing input voltage SAIL and the first node PIL, the second sensing input voltage SAIR and the second node PIR are all the operating voltage VDD, the transistor M1 and M2 are on but transistors M3 and M4 are off.

Since the transmission gates PG11 and PG12 are turned on, the operating voltage VDD is directed to the gates of the transistors M5 and M6, so the transistors M5 and M6 are turned on.

In addition, since the transmission gates PG13 and PG14 are conductive, the ground terminal VSS is led to the gates of the transistors M7 and M8, so the transistors M7 and M8 are conductive.

Through the turned-on transmission gates, the first sensing output voltage SAOL and the second sensing output voltage SAOR are sampled as instantaneous transition points stored in the first capacitor CL and the second capacitor CR, wherein the instantaneous transition point stored in the first capacitor CL is equal to the critical voltage of the transistors M7, M3, M1, and M5, and the instantaneous transition point stored in the second capacitor CR is equal to the critical voltage of the transistors M8, M4, M2, and M6. That is, the voltage of the first sensing output voltage SAOL is VSAOL=VTPL, and the voltage of the second sensing output voltage SAOR is VSAOR=VTPR, where VTPL is the instantaneous transition point of the path M7M3M1M5 (also equal to the critical voltage of the transistors M7, M3, M1, M5), and VTPR is the instantaneous transition point of the path M8M4M2M6 (also equal to the critical voltage of the transistors M8, M4, M2, M6). Similarly, VPIL=VSAIL=VSAOL=VTPL, and VPIR=VSAIR=VSAOR=VTPR.

Figure 4A shows a schematic diagram of the operation of the sense amplifier in the first sub-stage of the third stage according to an embodiment of the present invention. Figure 4B shows a signal waveform diagram of the sense amplifier in the first sub-stage of the third stage according to an embodiment of the present invention.

In the first sub-stage P2-1 of the third stage, the voltage difference between the input signal IN and the reference voltage VREF is amplified.

In the first sub-phase P2-1 of the third phase, the input signal IN is maintained, and the reference voltage VREF is logic high.

In the first sub-phase P2-1 of the third phase, transmission gates PG15 and PG16 are turned on. Before the first sub-phase P2-1 of the third phase is carried out, the potentials of the first node PIL and the second node PIR are the transition point voltages VTPL and VTPR. In the first sub-stage P2-1 of the third stage, when the transmission gates PG15 and PG16 turn from off to on, the voltage difference (VIN) between the input signal IN and the second node PIR (transition point voltage VTPR) -VTPR) is coupled to the second sensing input voltage SAIR through the second capacitor CR to cause a voltage change of the second sensing input voltage SAIR; and, the reference voltage VREF and the first node PIL (transition point voltage The voltage difference (VREF-VTPL) between the two voltages VTPL is coupled to the first sensing input voltage SAIL through the first capacitor CL to cause a voltage change of the first sensing input voltage SAIL. Therefore, the first sensing input voltage SAIL and the second sensing input voltage SAIR also have voltage changes. The voltage changes of the first sensing input voltage SAIL and the second sensing input voltage SAIR are reflected to the first sensing output voltage SAOL and the second sensing output voltage SAOR. That is, if the voltage change of the first sense input voltage SAIL and the second sense input voltage SAIR is +Δ, then the voltage change of the first sense output voltage SAOL and the second sense output voltage SAOR is -Δ.

Here, the case where the second inductive output voltage SAOR is higher than the first inductive output voltage SAOL will be described first. In this case, the second sensing output voltage SAOR turns on the fifth transistor M5 some and turns off the seventh transistor M7 some; the first sensing output voltage SAOL turns on the eighth transistor M8 some and turns off the sixth transistor M6 some. . In this way, through the positive feedback effect, the transistors M8 and M5 become more and more on, while the transistors M6 and M7 become more and more off.

Similarly, when the second sensing output voltage SAOR is lower than the first sensing output voltage SAOL, the second sensing output voltage SAOR turns on the seventh transistor M7 and turns off the fifth transistor M5; the first sensing output voltage SAOL turns on the sixth transistor M6 and turns off the eighth transistor M8. In this way, through the positive feedback effect, transistors M6 and M7 are increasingly turned on, while transistors M8 and M5 are increasingly turned off.

Therefore, when the input signal IN is higher than the reference voltage VREF, (VTPL-VREF)>(VTPR-VIN), through the positive feedback effect, the first induction output voltage VSAOL will gradually pull down, and the second induction output voltage VSAOR will gradually pull up. When the input signal IN is lower than the reference voltage VREF, (VTPL-VREF)<(VTPR-VIN), through the positive feedback effect, the first induction output voltage VSAOL will gradually pull up, and the second induction output voltage VSAOR will gradually pull down.

FIG. 5A shows an operation diagram of the inductive amplifier in the second sub-stage of the third stage according to an embodiment of the present invention. FIG. 5B shows a signal waveform diagram of the inductive amplifier in the second sub-stage of the third stage according to an embodiment of the present invention.

In the second sub-stage P2-2 of the third stage, the first inductive output voltage SAOL and the second inductive output voltage SAOR are pulled to the full-swing voltage range, and charges are recorded into the transistor M5 -Gate of M8.

In the second sub-phase P2-2 of the third phase, the first switch signal S0 transitions, so that the transmission gates PG15 and PG16 are disconnected, closing the path of the input signal. Turn on the transmission gates PG1, PG2, PG3, PG4, PG5, PG6, PG7 and PG8.

In addition, since the transmission gates PG3 and PG4 are turned on, the amplification path in the previous sub-stage is destroyed. In addition, the transistors M5 to M8 are on, the transistors M1 and M2 are on, and the transistors M3 and M4 are off. Therefore, transistors M5 to M8 form a latch unit. Thereby, the first sense output voltage SAOL and the second sense output voltage SAOR can be pulled to the full swing voltage range. That is, when the first sensing output voltage SAOL is higher than the second sensing output voltage SAOR, the first sensing The output voltage SAOL and the second sensing output voltage SAOR are respectively pulled to the operating voltage VDD and the ground terminal VSS. When the first sensing output voltage SAOL is lower than the second sensing output voltage SAOR, the first sensing output voltage SAOL and the second sensing output voltage SAOR are pulled to the ground terminal VSS and the operating voltage VDD respectively.

In addition, since the transfer gates PG3, PG4, PG5, and PG6 are turned on, charges are recorded to the gates of the transistors M5-M8.

In addition, if the first switching signal S0 does not change state, the first sensing output voltage SAOL and the second sensing output voltage SAOR will maintain the potential.

FIG. 6A is a schematic diagram showing the operation of the inductive amplifier according to an embodiment of the present invention in the first stage of the next round. FIG. 6B is a schematic diagram showing the signal waveform of the inductive amplifier according to an embodiment of the present invention in the first stage of the next round.

In the next round, the enable signal INI_EN is enabled again. So, start the first phase of the next round. As shown in Figure 6B, the first phase P0 of the next round partially overlaps with the second sub-phase P2-2 of the third phase of the previous round.

The operations of Figures 6A and 6B can be referred to Figures 2A and 2B, so the details are omitted here.

To carry out the next round of sensing operation, the transmission gates PG3, PG4, PG5, and PG6 must be disconnected.

FIG. 7 shows a flow chart of the operation method of the sense amplifier according to an embodiment of the present invention. The operation method of the sense amplifier according to an embodiment of the present invention includes: in a first stage, initializing a first sense input voltage and a second sense input voltage in the sense amplifier, and using the voltage stored in the sense amplifier. plural The charges in a transistor are used to record a first sense output voltage of a previous round and a second sense output voltage (710); in a second stage, the first sense output voltage of a current round and the The second sense output voltage is sampled into a plurality of transition points (720); in a first sub-stage of a third stage, a voltage difference between an input signal and a first reference voltage is amplified (730); And in a second sub-stage of the third stage, the first sense output voltage and the second sense output voltage are stretched to a full swing voltage range, and charges are recorded to the transistors (740).

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

710-740: Steps

Claims (10)

An operating method of an inductive amplifier includes the following steps: in a first stage, a first inductive input voltage and a second inductive input voltage in the inductive amplifier are initialized, and charges in a plurality of parasitic capacitors of a plurality of gates of a plurality of transistors in the inductive amplifier are used to record a first inductive output voltage and a second inductive output voltage of a previous round; in a second stage, the first inductive output voltage of a current round is initialized. The first sensing output voltage and the second sensing output voltage are sampled into a plurality of transition points; in a first sub-stage of a third stage, a voltage difference between an input signal and a first reference voltage is amplified; and in a second sub-stage of the third stage, the first sensing output voltage and the second sensing output voltage are pulled apart to a full swing voltage range, and the charge is recorded to the transistors, the sensing amplifier includes a first transistor to an eighth transistor, and a first transmission gate to an eighteenth transmission gate, One end of the first transistor is coupled to one end of the fifth transistor, one end of the second transistor is coupled to one end of the sixth transistor, one end of the third transistor is coupled to one end of the seventh transistor, one end of the fourth transistor is coupled to one end of the eighth transistor, the other end of the first transistor is coupled to the other end of the third transistor, the other end of the second transistor is coupled to the other end of the fourth transistor, the other end of the fifth transistor is coupled to a ground terminal, and the sixth transistor is coupled to one end of the seventh transistor. The other end of the transistor is coupled to the ground end, the other end of the seventh transistor is coupled to a second reference voltage, the other end of the eighth transistor is coupled to the second reference voltage, a control end of the first transistor and a control end of the third transistor are coupled to the first sensing input voltage, the other end of the first transistor is coupled to the first sensing output voltage, a control end of the second transistor and a control end of the fourth transistor are coupled to the second sensing input voltage, the control end of the second transistor The other end of the first transmission gate is coupled to the second sensing output voltage, one end of the first transmission gate is coupled to the second reference voltage, the other end of the first transmission gate is coupled to the first sensing input voltage, one end of the second transmission gate is coupled to the second reference voltage, the other end of the second transmission gate is coupled to the second sensing input voltage, the third transmission gate is coupled between a control end of the seventh transistor and the second sensing output voltage, the fourth transmission gate is coupled between a control end of the eighth transistor and the first sensing input voltage, and the The fifth transmission gate is coupled between a control terminal of the fifth transistor and the second sensing output voltage, the sixth transmission gate is coupled between a control terminal of the sixth transistor and the first sensing output voltage, the seventh transmission gate is coupled between the terminal of the third transistor and the first sensing output voltage, the eighth transmission gate is coupled between the terminal of the fourth transistor and the second sensing output voltage, the ninth transmission gate is coupled between the first sensing input voltage and the first sensing output voltage. The tenth transmission gate is coupled between the second sensing input voltage and the second sensing output voltage, the eleventh transmission gate is coupled between the second reference voltage and a control terminal of the fifth transistor, the twelfth transmission gate is coupled between the second reference voltage and a control terminal of the sixth transistor, the thirteenth transmission gate is coupled between the ground terminal and the control terminal of the seventh transistor, the fourteenth transmission gate is coupled between the ground terminal and the control terminal of the eighth transistor, the fifteenth transmission gate is coupled between the ground terminal and the control terminal of the eighth transistor, The transmission gate is coupled between the first reference voltage and one end of a first capacitor, the other end of the first capacitor is coupled to the first sensing input voltage, the sixteenth transmission gate is coupled between the input signal and one end of a second capacitor, the other end of the second capacitor is coupled to the second sensing input voltage, the seventeenth transmission gate is coupled between the end of the first capacitor and the other end of the first capacitor, and the eighteenth transmission gate is coupled between the end of the second capacitor and the other end of the second capacitor. The operating method of the sense amplifier according to claim 1, wherein in the first stage, the step of initializing the first sense input voltage and the second sense input voltage in the sense amplifier includes: The first sensing input voltage and the second sensing input voltage are initialized to the second reference voltage; in the second stage, the first sensing output voltage and the second sensing output voltage are sampled to the transition points. The steps include: sampling the first sensing output voltage and the second sensing output voltage into individual transition points of a plurality of signal paths; and in the second stage, sampling the first sensing output voltage into the signal paths A plurality of first threshold voltages of a plurality of transistors on one of the first signal paths, and the second sense output voltage is sampled as a plurality of the plurality of transistors on one of the second signal paths of the signal paths. second critical voltage. The operating method of the inductive amplifier as described in claim 1, wherein, in the first sub-stage of the third stage, the step of amplifying the voltage difference between the input signal and the first reference voltage includes: a voltage difference between the first reference voltage and a first node is coupled to the first inductive input voltage through a first capacitive coupling effect to cause a first voltage change of the first inductive input voltage; a voltage difference between the input signal and a second node is coupled to the second inductive input voltage through a second capacitive coupling effect to cause a second voltage change of the second inductive input voltage. changes; and the first voltage change of the first inductive input voltage and the second voltage change of the second inductive input voltage are reflected to the first inductive output voltage and the second inductive output voltage; wherein, in the first sub-stage of the third stage, when the input signal is higher than the first reference voltage, the first inductive output voltage is gradually pulled down and the second inductive output voltage is gradually pulled up through the positive feedback effect; and when the input signal is lower than the first reference voltage, the first inductive output voltage is gradually pulled up and the second inductive output voltage is gradually pulled down through the positive feedback effect. The operating method of the sense amplifier as described in claim 1, wherein in the second sub-stage of the third stage, the first sense output voltage and the second sense output voltage are stretched to the full swing voltage range This step includes: When the first sensing output voltage is higher than the second sensing output voltage, the first sensing output voltage and the second sensing output voltage are pulled to the second reference voltage and a third reference voltage respectively; and when the first sensing output voltage and the second sensing output voltage are respectively pulled to the second reference voltage and a third reference voltage; When a sensing output voltage is lower than the second sensing output voltage, the first sensing output voltage and the second sensing output voltage are pulled to the third reference voltage and the second reference voltage respectively. The operating method of the inductive amplifier as described in claim 1, wherein, in the first stage, the charges in the parasitic capacitors of the gates of the transistors in the inductive amplifier are used to record the first inductive output voltage and the second inductive output voltage of the previous round; and in the second sub-stage of the third stage, the charges are recorded in the parasitic capacitors of the individual gates of the transistors. A sense amplifier includes: a plurality of transistors; and a plurality of transmission gates coupled to the transistors; wherein, in a first stage, a first sense input voltage and a second sense input voltage in the sense amplifier are The sensing input voltage is initialized, and charges stored in a plurality of parasitic capacitances of a plurality of gates of the transistors are used to record a first sensing output voltage and a second sensing output voltage of the previous round; in a In the second stage, the first induction output voltage and the second induction output voltage of a current round are sampled into a plurality of transition points; In a first sub-stage of a third stage, a voltage difference between an input signal and a first reference voltage is amplified; and in a second sub-stage of the third stage, the first sensing The output voltage and the second sense output voltage are spread out to a full swing voltage range, and charges are recorded into the transistors, wherein one terminal of the first transistor is coupled to one terminal of the fifth transistor, and the first transistor is coupled to a terminal of the fifth transistor. One terminal of the two transistors is coupled to one terminal of the sixth transistor, one terminal of the third transistor is coupled to one terminal of the seventh transistor, and one terminal of the fourth transistor is coupled to one terminal of the eighth transistor. One end, the other end of the first transistor is coupled to the other end of the third transistor, the other end of the second transistor is coupled to the other end of the fourth transistor, the other end of the fifth transistor Coupled to a ground terminal, the other terminal of the sixth transistor is coupled to the ground terminal, the other terminal of the seventh transistor is coupled to a second reference voltage, and the other terminal of the eighth transistor is coupled to The second reference voltage, a control terminal of the first transistor and a control terminal of the third transistor are coupled to the first sensing input voltage, and the other terminal of the first transistor is coupled to the first Sensing output voltage, a control terminal of the second transistor and a control terminal of the fourth transistor are coupled to the second sensing input voltage, and the other terminal of the second transistor is coupled to the second sensing output voltage, One end of the first transmission gate is coupled to the second reference voltage, the other end of the first transmission gate is coupled to the first inductive input voltage, and one end of the second transmission gate is coupled to the second reference voltage, The other end of the second transmission gate is coupled to the second sensing input voltage, the third transmission gate is coupled between a control terminal of the seventh transistor and the second sensing output voltage, and the fourth transmission gate The gate is coupled between a control terminal of the eighth transistor and the first inductive output voltage, and the fifth transmission gate is coupled between a control terminal of the fifth transistor and the second inductive output voltage, The sixth transmission gate is coupled between a control terminal of the sixth transistor and the first sensing output voltage, and the seventh transmission gate is coupled between the terminal of the third transistor and the first sensing output voltage. The eighth transmission gate is coupled between the terminal of the fourth transistor and the second sensing output voltage, and the ninth transmission gate is coupled between the first sensing input voltage and the first sensing output voltage. The tenth transmission gate is coupled between the second sensing input voltage and the second sensing output voltage, and the eleventh transmission gate is coupled between the second reference voltage and a control terminal of the fifth transistor. between, The twelfth transmission gate is coupled between the second reference voltage and a control terminal of the sixth transistor, and the thirteenth transmission gate is coupled between the ground terminal and the control terminal of the seventh transistor. time, the fourteenth transmission gate is coupled between the ground terminal and the control terminal of the eighth transistor, and the fifteenth transmission gate is coupled between the first reference voltage and one terminal of a first capacitor , the other end of the first capacitor is coupled to the first sense input voltage, the sixteenth transmission gate is coupled between the input signal and one end of a second capacitor, the other end of the second capacitor is coupled to The second sense input voltage, the seventeenth transmission gate is coupled between the terminal of the first capacitor and the other terminal of the first capacitor, and the eighteenth transmission gate is coupled to the second terminal of the second capacitor. between the terminal and the other terminal of the second capacitor. The sense amplifier as claimed in claim 6, wherein in the first stage, when the first sense input voltage and the second sense input voltage in the sense amplifier are initialized, the first sense input voltage and the second sense input voltage are The second sense input voltage is initialized to the second reference voltage; In the second stage, when the first sensing output voltage and the second sensing output voltage are sampled into the transition points, the first sensing output voltage and the second sensing output voltage are sampled into a plurality of signal paths. individual transition points; in the second stage, the first sense output voltage is sampled as a plurality of first threshold voltages of a plurality of transistors on one of the first signal paths, and the The second sense output voltage is sampled as a plurality of second threshold voltages of a plurality of transistors on one of the second signal paths. The inductive amplifier as described in claim 6, wherein, in the first sub-stage of the third stage, when the voltage difference between the input signal and the first reference voltage is amplified: a voltage difference between the first reference voltage and a first node is coupled to the first inductive input voltage through a first capacitive coupling effect to cause a first voltage change of the first inductive input voltage; a voltage difference between the input signal and a second node is coupled to the second inductive input voltage through a second capacitive coupling effect to cause a second voltage change of the second inductive input voltage; and the The first voltage change of the first sensing input voltage and the second voltage change of the second sensing input voltage are reflected to the first sensing output voltage and the second sensing output voltage; wherein, in the first sub-stage of the third stage, when the input signal is higher than the first reference voltage, the first sensing output voltage is gradually pulled down and the second sensing output voltage is gradually pulled up through the positive feedback effect; and when the input signal is lower than the first reference voltage, the first sensing output voltage is gradually pulled up and the second sensing output voltage is gradually pulled down through the positive feedback effect. The sense amplifier as claimed in claim 6, wherein in the second sub-stage of the third stage, when the first sense output voltage and the second sense output voltage are stretched to the full swing voltage range, when When the first sensing output voltage is higher than the second sensing output voltage, the first sensing output voltage and the second sensing output voltage are pulled to the second reference voltage and a third reference voltage respectively; and when the first sensing output voltage is When the inductive output voltage is lower than the second inductive output voltage, the first inductive output voltage and the second inductive output voltage are pulled to the third reference voltage and the second reference voltage respectively. The sense amplifier according to claim 6, wherein in the first stage, the charges stored in the parasitic capacitances of the gates of the transistors in the sense amplifier are used to record the previous round the first sense output voltage and the second sense output voltage; and in the second sub-stage of the third stage, charge is recorded into the parasitic capacitances of the individual gates of the transistors.

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