TWI807963B - Method for manufacturing package structures with nano-twin layer - Google Patents

Abstract

The present application provides a method for manufacturing a package structure with a nano-twin layer, comprising: forming a first nano-twin layer, a second nano-twin layer, a third nano-twin layer, and a fourth nano-twin layer on surfaces of a metal layer, a chip, a lead frame and a substrate respectively; applying temperature and pressure, to make the first nano twin layer bond with the second nano twin layer, and the second nano twin layer bond with the third nano-twin layer to obtain an intermediate; molding and post-curing the intermediate; bonding the third nano-twin layer of the intermediate after post-curing with the fourth nano-twin layer of the substrate, so as to obtain a package structure with a nano-twin layer. The method of the present application can reduce thermal resistance, which is beneficial to improve the heat dissipation effect, and has a high yield.

Description

Manufacturing method of encapsulation structure with nano-twin layer

The present application relates to the technical field of encapsulation, and in particular to a method for manufacturing an encapsulation structure with a nano-twin layer.

At present, the die packaging methods can be divided into wire bonding (Wire Bond) packaging and copper bridging (Clip Bond) two processes. After the die is packaged, it is soldered and connected to the printed circuit board (PCB). The steps of copper sheet bridging generally include the steps of copper lead frame feeding, glue dispensing (adhesive material), glue dispensing inspection, chip placement, inspection after placement of the wafer, placement of copper sheets, and inspection after placement of copper sheets.

The advantage of the copper bridge is that it can absorb a large surge current instantaneously, and the power loss of the packaged product is low, so it can better meet the needs of high-power chips, especially the needs of the automotive field. However, the copper bridge process uses a lot of media (such as adhesive materials, leads, and solder, etc.), and the overall thermal resistance is high, which is not conducive to heat dissipation of high-power chips. Moreover, after soldering with the PCB, the positional accuracy of the chip and the copper sheet, the amount of glue dispensed, and the uniformity are the main reasons for product failure and affecting product yield.

In view of this, the present application proposes a novel method for manufacturing a packaging structure with a nano-twin layer to solve the problems of poor heat dissipation and low product yield in the existing copper bridging process.

One embodiment of the present application provides a method for manufacturing a packaging structure having a nano-twin layer, comprising the following steps: forming a first nano-twin layer on at least one surface of the metal layer; Forming a second nano twin crystal layer on opposite surfaces of the wafer; forming a third nano twin crystal layer on opposite surfaces of a lead frame; stacking the metal layer forming the first nano twin crystal layer, the wafer forming the second nano twin crystal layer, and the lead frame forming the third nano twin crystal layer in sequence; applying temperature and pressure so that the first nano twin crystal layer is joined to the second nano twin crystal layer, and the second nano twin crystal layer is joined to the third nano twin crystal layer to obtain an intermediate.

In one embodiment, the following steps are further included: performing plastic sealing and pressing on the intermediate body, and post-curing.

In one embodiment, the method further includes the following steps: forming a fourth nano-twin layer on at least one surface of the substrate; bonding the third nano-twin layer of the post-cured intermediate with the fourth nano-twin layer of the substrate to obtain the encapsulation structure having the nano-twin layer.

In one embodiment, the first nano-twinned layer, the second nano-twinned layer, the third nano-twinned layer and the fourth nano-twinned layer are all formed by an electroplating process.

In one embodiment, the electroplating solution used in the electroplating process includes metal salts, acids and chlorine-containing compounds.

In one embodiment, the metal salt includes one or more of copper sulfate, copper methanesulfonate, gold sulfate and gold sulfite. The acid includes one or more of sulfuric acid, methanesulfonic acid, hydrochloric acid and chloric acid, and the chlorine-containing compound includes hydrochloric acid.

In one embodiment, the first nano-twinned layer, the second nano-twinned layer, the third nano-twinned layer and the fourth nano-twinned layer all include nano-twinned crystal grains, and the size of the nano-twinned crystal grains is 70-10000 nm.

In one embodiment, the first nano-twinned layer, the second nano-twinned layer, the third nano-twinned layer and the fourth nano-twinned layer are nano-twinned copper or nano-twinned gold.

In one embodiment, the thickness ratio of the first nano-twin layer to the metal layer is 1:10-1:15. The thickness ratio of the second nano-twin layer to the wafer is 1:5-1:10. The thickness ratio of the third nano-twin layer to the lead frame is 1:10-1:15.

In one embodiment, the temperature is 150-300°C, and the pressure is 1×10 ^-3 -6000 torr.

The manufacturing method described in this application uses the nano-twin layer to package the chip, and uses the nano-twin layer to connect the packaged chip to the substrate, which can omit the adhesive materials, leads and solders used in the ordinary copper bridging process, and use less materials to reduce thermal resistance, thereby reducing the generation of total heat. Moreover, the contact area between the nano twin crystal layer and the substrate is larger, which is beneficial to improve the heat dissipation effect. In addition, the preparation method described in the present application can also avoid the influence of packaging failure caused by low wire bonding accuracy, inaccurate alignment between the chip and the copper sheet, difficult control of the size of the dispensing glue, or uneven dispensing, thereby improving the yield rate.

100: Package structure

10: metal layer

11: The first nano-twin layer

20: Wafer

21: The second nano-twin layer

30: lead frame

31: The third nano-twin layer

40: Substrate

41: The fourth nano-twin layer

50: Nano twin layer

60: intermediate

70: resin layer

FIG. 1 is a schematic diagram of a first nano-twin layer formed on the surface of a metal layer according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a wafer having a second nano-twin layer formed on its surface according to an embodiment of the present application.

FIG. 3 is a schematic diagram of a lead frame according to an embodiment of the present application after forming a third nano-twin layer on its surface.

FIG. 4 is a schematic diagram of a fourth nano-twin layer formed on the surface of the substrate according to an embodiment of the present application.

Fig. 5 is a schematic diagram of stacking the metal layer with the first nano-twin layer shown in Fig. 1, the wafer with the second nano-twin layer shown in Fig. 2, and the lead frame with the third nano-twin layer shown in Fig. 3 .

FIG. 6 is a schematic diagram of an intermediate obtained after joining the nano-twin layers with the structure shown in FIG. 5 .

FIG. 7 is a schematic diagram of the intermediate shown in FIG. 6 after plastic sealing, pressing, and curing.

FIG. 8 is a schematic diagram of connecting the structure shown in FIG. 7 with the substrate shown in FIG. 4 on which the fourth nano-twin layer is formed.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the embodiments of this application. The terminology used herein is only for the purpose of describing specific implementation manners, and is not intended to limit the embodiments of the present application.

It should be noted that all directional indications (such as up, down, left, right, front, rear...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions among the components in a specific posture (as shown in the drawings), and if the specific posture changes, the directional indications will also change accordingly.

In addition, the descriptions such as "first" and "second" in this application are only for description purposes, and should not be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

Embodiments of the present application are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate constructions) of the present application. As such, variations in the shapes of the illustrations as a result of manufacturing processes and/or tolerances are to be expected. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions shown in the figures are schematic in themselves and their shapes are not intended to illustrate the actual shape of the device and are not intended to limit the scope of the application.

Some implementations of the present application will be described in detail below in conjunction with the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

Example 1

Referring to FIG. 1 to FIG. 8, the present embodiment provides a method for manufacturing a package structure 100 with a nano-twin layer 50, including the following steps:

Step S1 , please refer to FIG. 1 , forming a first nano-twin layer 11 on at least one surface of the metal layer 10 . In this embodiment, the metal layer 10 is a copper clip. In this embodiment, a first nano-twinned layer 11 is formed on the upper and lower surfaces of the metal layer 10 . In other embodiments, the first nano-twinned layer 11 may be formed only on the upper or lower surface of the metal layer 10 .

Specifically, the metal layer 10 may be electroplated by an electroplating device (not shown in the figure) to form the first nano-twin layer 11 . In some embodiments, the electroplating device includes a power supply, an anode, a cathode and an electroplating solution, and the power supply is connected to the anode and the cathode respectively. The anode and the cathode are soaked in the electroplating solution, and in this step, the cathode is the metal layer 10 (copper sheet). The power supply can be a DC power supply, a high-speed pulse power supply, or both the DC power supply and the high-speed pulse power supply can be used alternately. In this embodiment, it is a DC power supply. The anode can be, but not limited to, metal copper, phosphor copper, or an inert anode (such as platinum-plated titanium), etc. In this embodiment, the anode is phosphor copper.

Further, in some embodiments, the electroplating solution includes metal salts, acids and chlorine-containing compounds. Further, the electroplating solution may also include an additive, such as gelatin, surfactant, or lattice modification agent. The metal salt compound may include, but not limited to, one or more of copper sulfate, copper methanesulfonate, gold sulfate and gold sulfite, and the metal salt compound is the main raw material source for forming nano-twin layers. The acid can be an organic or inorganic acid to increase the electrolyte concentration to increase the electroplating rate, such as but not limited to sulfuric acid, methanesulfonic acid, hydrochloric acid or chloric acid. The chlorine-containing compound may be but not limited to hydrochloric acid, etc., and the chloride ions in the chlorine-containing compound are used to fine-tune the grain growth direction of the nano-twinned layer, so that the nano-twinned layer has a preferred direction. In this example, The electroplating solution contains copper sulfate (copper ion concentration is 30g/L), sulfuric acid (concentration is 100g/L) and hydrochloric acid (chloride ion concentration is 50mg/L).

After both the anode and the cathode are immersed in the electroplating solution, the power is turned on, and electroplating is performed for about 300 seconds with a direct current of a current density of 2 to 20ASD (ampere/square foot), so as to form the first nano-twin layer 11 on at least one surface of the metal layer 10 (cathode, copper sheet in this embodiment). In this embodiment, the ratio of the thickness of the first nano-twin layer 11 to the thickness of the metal layer 10 is 1:10.

It can be understood that the metal salt in the electroplating solution in this step is copper sulfate, therefore, the first nano-twin layer 11 formed is nano-twin Cu (nano-twin Cu, nt-Cu). The electrical resistivity of nano-twinned copper is not much different from that of Coarse-grained Cu. At a temperature of 100K~300K, the resistivity is roughly 5.0×10-9Ω. m~2.0×10-8Ω． m. The mechanical strength of nano-twinned copper is greatly improved, and it has good ductility, which is suitable for plastic processing, and its electrical conductivity is not much different from that of ordinary copper, which does not affect its application in the electrical field. The nano-twinned copper includes nano-twinned crystal grains, and the size of the nano-twinned crystal grains in this step is 80-10000nm.

Certainly, the method for forming the first nano-twin layer 11 on the surface of the metal layer 10 may also be other methods, such as physical vapor deposition (PVD) or sputtering, etc., which are not limited in this application.

Step S2 , please refer to FIG. 2 , forming a second nano-twin layer 21 on opposite surfaces of the wafer 20 . In this embodiment, a second nano-twin layer 21 is formed on the upper and lower surfaces of the wafer 20 respectively.

Specifically, the wafer 20 may be electroplated by an electroplating device (not shown in the figure) to form the second nano-twin layer 21 . The difference from step S1 is that in this step, the cathode is a wafer 20 . The power supply, anode, electroplating solution, current density and electroplating time, etc., can be set by referring to step S1, and will not be repeated here.

In this embodiment, the ratio of the thickness of the second nano-twin layer 21 to the thickness of the wafer 20 is 1:5. It can be understood that the metal salt in the electroplating solution in this step is also copper sulfate, therefore, the second nano-twinned layer 21 is also nano-twinned copper (nt-Cu). The nano-twinned copper includes nano-twinned crystal grains, and the size of the nano-twinned crystal grains in this step is 70-5000nm.

Certainly, the method for forming the second nano-twin layer 21 on the surface of the wafer 20 may also be other methods, such as physical vapor deposition or sputtering, which are not limited in this application.

Step S3 , please refer to FIG. 3 , forming a third nano-twin layer 31 on opposite surfaces of a lead frame 30 . In this embodiment, a third nano-twin layer 31 is formed on the upper and lower surfaces of the lead frame 30, and the lead frame 30 is a copper lead frame.

Specifically, the lead frame 30 may be electroplated by an electroplating device (not shown in the figure) to form the third nano-twin layer 31 . The difference from step S1 is that in this step, the cathode is a lead frame 30 . The power supply, anode, electroplating solution, current density and electroplating time, etc., can be set by referring to step S1, and will not be repeated here.

In this embodiment, the ratio of the thickness of the third nano-twin layer 31 to the thickness of the wafer 20 is 1:10. It can be understood that the metal salt in the electroplating solution in this step is also copper sulfate, therefore, the third nano-twinned layer 31 formed is also nano-twinned copper (nt-Cu). The nano-twinned copper includes nano-twinned crystal grains, and the size of the nano-twinned crystal grains in this step is 80-10000nm.

Certainly, the method for forming the third nano-twin layer 31 on the surface of the lead frame 30 may also be other methods, such as physical vapor deposition or sputtering, which are not limited in this application.

Step S4 , please refer to FIG. 4 , forming a fourth nano-twin layer 41 on the upper surface of the substrate 40 . In this embodiment, the substrate 40 may be a single-layer board or a multi-layer board, which is not limited in this application. Specifically, the circuit substrate 40 may be, but not limited to, a printed circuit board (PCB), a flexible board (FPC), a rigid-flex board, or an integrated circuit board (ICS).

Specifically, the substrate 40 may be electroplated by an electroplating device (not shown in the figure) to form the fourth nano-twin layer 41 . Different from step S1, in this step, the cathode is the substrate 40 . The power supply, anode, electroplating solution, current density and electroplating time, etc., can be set by referring to step S1, and will not be repeated here.

The metal salt in the electroplating solution in this step is also copper sulfate, therefore, the fourth nano-twinned layer 41 is also nano-twinned copper (nt-Cu). The nano-twinned copper includes nano-twinned crystal grains, and the size of the nano-twinned crystal grains in this step is 70-5000nm.

Certainly, the method for forming the fourth nano-twin layer 41 on the surface of the substrate 40 may also be other methods, such as physical vapor deposition or sputtering, which are not limited in this application.

Step S5, please refer to FIG. 5, the metal layer 10 formed with the first nano-twinned layer 11, the wafer 20 formed with the second nano-twinned layer 21, and the lead frame 30 formed with the third nano-twinned layer 31 are sequentially stacked. When the first nano-twin layer 11 is formed on only one surface of the metal layer 10 , the first nano-twin layer 11 is disposed toward the second nano-twin layer 21 of the wafer 20 .

Step S6, please refer to FIG. 6 , applying a certain temperature and pressure, so that the first nano-twinned layer 11 on the lower surface of the metal layer 10 is bonded (bonded) to the second nano-twinned layer 21 on the upper surface of the wafer 20 to form a nano-twinned layer 50 , and the second nano-twinned layer 21 on the lower surface of the wafer 20 is bonded (bonded) to the third nano-twinned layer 31 on the upper surface of the lead frame 30 to form a nano-twinned layer 50 , and an intermediate 60 is obtained.

Utilizing the characteristics of the nano-twin structure, through thermocompression bonding, the copper atoms of the first nano-twin layer 11 and the second nano-twin layer 21 will diffuse at the bonding interface, and the copper atoms of the second nano-twin layer 21 and the third nano-twin layer 31 will also diffuse at the bonding interface, and the bonding is completed with the growth of the crystal grains during the diffusion process. Within a certain range, the higher the temperature, the faster the diffusion rate; the greater the pressure, the faster the diffusion rate. In this embodiment, the temperature can be adjusted in the range of 150-300° C., and the pressure can be adjusted in the range of 1×10 −3 to 6000 torr.

In step S7, please refer to FIG. 7 , performing molding and post mold cure on the intermediate body 60 .

The specific steps of plastic sealing and pressing can be as follows: the intermediate body 60 can be put into a mold (not shown in the figure), the resin is melted into a liquid state by high temperature, and the liquid resin is injected into the mold cavity by high pressure, and a resin layer 70 is formed on the side surface and the bottom surface of the intermediate body 60 after curing to protect the intermediate body 60.

Then, the above-mentioned intermediate body 60 formed with the resin layer 70 that has been molded and pressed can be put into an oven for baking, so that the chemical reaction of the resin layer 70 is more complete, and the molecular combination is tighter to avoid water vapor intrusion, thereby completing the post-curing.

Step S8 , please refer to FIG. 8 , connect the post-cured intermediate body 60 to the substrate 40 formed with the fourth nano-twin layer 41 in FIG. 4 , so as to obtain the encapsulation structure 100 with the nano-twin layer 50 .

Utilizing the properties of the nano-twin structure, through thermocompression bonding (the temperature can be 150-300° C., and the pressure can be 1×10-3-6000 torr), the copper atoms of the third nano-twin layer 31 on the lower surface of the lead frame 30 and the fourth nano-twin layer 41 on the upper surface of the substrate 40 will mutually diffuse at the bonding interface, and the bonding (bonding) will be completed with the growth of crystal grains during the diffusion process, and the nano-twin layer 50 will be formed, thereby obtaining the packaging structure with the nano-twin layer 50 1 00. The thermal resistance coefficient Rth of the package structure 100 is 2.35° C./W.

It can be understood that the purpose of labeling the steps is to clearly describe the specific preparation method, and not to limit the order of the steps. For example, the order of steps S1 to S4 can be exchanged arbitrarily; or, steps S1, S2, S3 and S4 can also be performed synchronously; or, step S4 can also be performed after step S7 and before step S8.

Example 2

The difference between this embodiment and Embodiment 1 is that: the metal salt in the electroplating solution is gold sulfate; the first nano-twin layer 11, the second nano-twin layer 21, the third nano-twin layer 31 and the fourth nano-twin layer 41 are all nano-twin gold; The size of the twin crystal grains is 100-10000 nm; the size of the nano-twin crystal grains in the second nano-twin layer 21 is 70-8000 nm; the thermal resistance coefficient Rth of the package structure 100 is 2.30° C./W. The rest are the same as in Embodiment 1, and will not be repeated here.

Example 3

The difference between this embodiment and Embodiment 1 is that: the ratio of the thickness of the first nano-twinned layer 11 to the metal layer 10 is 1:15; the ratio of the thickness of the second nano-twinned layer 21 to the wafer 20 is 1:10; the ratio of the thickness of the third nano-twinned layer 31 to the lead frame 30 is 1:15; 100-10000 nm; the thermal resistance Rth of the package structure 100 is 2.30° C./W. The rest are the same as in Embodiment 1, and will not be repeated here.

The manufacturing method described in the present application uses the nano-twin layer 50 to package the chip 20, and uses the nano-twin layer 50 to connect the packaged chip 20 to the substrate 40, which can omit the adhesive materials, leads and solders used in the common copper sheet bridging process, and use less materials to reduce thermal resistance, thereby reducing the generation of total heat. Moreover, the contact area between the nano twin crystal layer 50 and the substrate 40 is larger, which is beneficial to improve the heat dissipation effect. In addition, the preparation method described in the present application can also avoid the influence of packaging failure caused by low wire bonding accuracy, inaccurate alignment between the chip and the copper sheet, difficult control of the size of the dispensing glue, or uneven dispensing, thereby improving the yield rate.

The above descriptions are some specific implementations of the present application, but should not be limited to these implementations in actual application. For those of ordinary skill in the art, other deformations and changes made according to the technical concept of the present application should fall within the scope of protection of the present application.

100: Package structure

10: metal layer

20: Wafer

30: lead frame

40: Substrate

50: Nano twin layer

70: resin layer

Claims (8)

A method for manufacturing a package structure with a nano-twin layer, which is improved in that it includes the following steps: forming a first nano-twin layer on at least one surface of a metal layer; forming a second nano-twin layer on opposite surfaces of a wafer; forming a third nano-twin layer on opposite surfaces of a lead frame; stacking the metal layer on which the first nano-twin layer is formed, the wafer on which the second nano-twin layer is formed, and the lead frame on which the third nano-twin layer is formed; applying temperature and pressure to make the first nano-twin layer Bonding with the second nano-twin layer, the second nano-twin layer is bonded with the third nano-twin layer to obtain an intermediate; plastic sealing and pressing the intermediate, and post-curing; forming a fourth nano-twin layer on at least one surface of the substrate; bonding the third nano-twin layer of the post-cured intermediate with the fourth nano-twin layer of the substrate to obtain the encapsulation structure with the nano-twin layer. The manufacturing method of the encapsulation structure having the nano-twin layer according to claim 1, wherein the first nano-twin layer, the second nano-twin layer, the third nano-twin layer and the fourth nano-twin layer are all formed by an electroplating process. The manufacturing method of the encapsulation structure with the nano-twin layer according to claim 2, wherein the electroplating solution used in the electroplating process includes metal salts, acids and chlorine-containing compounds. The method for manufacturing a packaging structure with a nano-twin layer as described in Claim 3, wherein the metal salt compound includes one or more of copper sulfate, copper methanesulfonate, gold sulfate, and gold sulfite, the acid includes one or more of sulfuric acid, methanesulfonic acid, hydrochloric acid, and chloric acid, and the chlorine-containing compound includes hydrochloric acid. The method for manufacturing a packaging structure with a nano-twin layer according to claim 1, wherein the first nano-twin layer, the second nano-twin layer, the third nano-twin layer and the fourth nano-twin layer all include nano-twin crystal grains, and the size of the nano-twin crystal grains is 70-10000 nm. The manufacturing method of the encapsulation structure having the nano-twin layer according to claim 5, wherein the first nano-twin layer, the second nano-twin layer, the third nano-twin layer and the fourth nano-twin layer are nano-twinned copper or nano-twinned gold. The method for manufacturing a packaging structure with a nano-twin layer according to Claim 1, wherein the thickness ratio of the first nano-twin layer to the metal layer is 1:10-1:15, the thickness ratio of the second nano-twin layer to the wafer is 1:5-1:10, and the thickness ratio of the third nano-twin layer to the lead frame is 1:10-1:15. The manufacturing method of the encapsulation structure with the nano-twin layer as described in Claim 1, wherein the temperature is 150-300°C, and the pressure is 1×10 ^-3 -6000 torr.

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