TWI898839B - Chip type thermal conductive patch and method for manufacturing the same - Google Patents

Abstract

A chip type thermal conductive patch includes a first copper sheet, a second copper sheet, a thermally conductive and insulating double-sided adhesion film, an insulating solder resist protective layer, a first terminal electrode, and a second terminal electrode. The first copper sheet has a first groove to divide the first copper sheet into a first portion and a second portion, which are separated from each other. The second copper sheet has a second groove to divide the second copper sheet into a third portion and a fourth portion, which are separated from each other. The thermally conductive and insulating double-sided adhesion film is sandwiched between the first copper sheet and the second copper sheet to form a stacked structure. The stacked structure has a central axis, and the first groove and the second groove are respectively located on opposite sides of the central axis. The stacked structure includes a middle portion, and a first end portion and a second end portion located on opposite sides of the middle portion. The insulating solder resist protective layer covers the middle portion and fills the first second groove and the second groove. The first terminal electrode covers the first end portion. The second terminal electrode covers the second end portion.

Description

Chip-type thermal conductive patch and manufacturing method thereof

This disclosure relates to a thermally conductive component, and more particularly to a chip-type thermally conductive patch and its manufacturing method.

As circuit applications become increasingly complex, the sources of heat generated within circuit boards are also becoming more numerous and complex. To effectively conduct or disperse heat, insulating thermal pads or insulating ceramic materials must be used to increase thermal conductivity or heat flow.

Chip-type thermal pads primarily consist of an insulating heat sink and a pair of solderable terminal electrodes. Currently available chip-type thermal pads all utilize a highly thermally conductive ceramic substrate as the insulating heat sink. Chip-type thermal pads primarily utilize the substrate as a transfer medium, so the thermal conductivity of the substrate material determines their heat transfer capabilities.

The main materials for high thermal conductivity ceramic substrates are aluminum nitride (AlN) and silicon carbide (SiC). The maximum thermal conductivity of aluminum nitride is 230W/mK, while that of silicon carbide is 350W/mK. The cost of aluminum nitride and silicon carbide is high, and the bonding strength between the surface of aluminum nitride and silicon carbide and metal is not as good as that of traditional aluminum _oxide ( _Al2O3 ) substrates. Therefore, to form an electrode with excellent bonding strength on highly thermally conductive substrates such as aluminum nitride and silicon carbide, the substrate surface must first be modified, such as roughening or oxidation. However, such modification will increase the production cost of the thermal pad.

One objective of this disclosure is to provide a chip-type thermal patch and its manufacturing method. This chip-type thermal patch utilizes a stacked structure formed by laminating two copper sheets with a thermally conductive, insulating double-sided lamination film, replacing the traditional ceramic substrate. Because copper's thermal conductivity is significantly greater than that of the ceramic substrate, this chip-type thermal patch exhibits excellent thermal conductivity and effectively conducts heat.

Another object of this disclosure is to provide a chip-type thermal pad that can be directly soldered to a circuit board using surface mount technology (SMT) to simultaneously provide heat dissipation and circuit isolation, thus offering excellent applicability.

In accordance with the above-mentioned purpose of the present disclosure, a chip-type thermally conductive patch is proposed, comprising a first copper sheet, a second copper sheet, a thermally conductive insulating double-sided adhesive film, an insulating solder mask, a first end electrode, and a second end electrode. The first copper sheet has a first trench. The first trench divides the first copper sheet into a first part and a second part separated from each other. The second copper sheet has a second trench. The second trench divides the second copper sheet into a third part and a fourth part separated from each other. The thermally conductive insulating double-sided adhesive film is sandwiched between the first copper sheet and the second copper sheet to bond the second copper sheet to the first copper sheet to form a stacked structure. This stacked structure has a central axis, and the first trench and the second trench are respectively located on both sides of the central axis. The stacked structure includes a central portion, and first and second ends located on opposite sides of the central portion. An insulating solder mask layer covers the central portion, leaving the first and second ends exposed. The insulating solder mask layer fills the first and second trenches. A first end electrode covers the first end and a portion of the central portion covered by the insulating solder mask layer. A second end electrode covers the second end and a portion of the central portion covered by the insulating solder mask layer.

According to one embodiment of the present disclosure, the first trench and the second trench are symmetrical with respect to the central axis.

According to one embodiment of the present disclosure, the stacked structure has a first short side and a second short side facing each other, and the first trench and the second trench are adjacent to the first short side and the second short side, respectively. A first distance between the first trench and the first short side, and a second distance between the second trench and the second short side, are both 1/4 to 1/3 of the length of the stacked structure.

According to one embodiment of the present disclosure, the width of the first trench and the second trench are both 50 μm to 300 μm.

According to one embodiment of the present disclosure, the thickness of the thermally conductive and insulating double-sided lamination film is 15 μm to 30 μm.

According to one embodiment of the present disclosure, the thermal conductivity of the aforementioned thermally conductive insulating double-sided lamination film is greater than 3W/mK.

According to one embodiment of the present disclosure, the material of the aforementioned thermally conductive insulating double-sided lamination film contains graphite sheets and/or graphene, and the carbon content of the thermally conductive insulating double-sided lamination film is greater than 90%.

According to one embodiment of the present disclosure, the material of the insulating solder mask layer includes epoxy, resin, or polyimide (PI).

In accordance with the above-mentioned purpose of the present disclosure, a method for manufacturing a chip-type thermally conductive patch is also proposed. In this method, a first copper sheet and a second copper sheet are respectively bonded to the lower surface and the upper surface of a thermally conductive insulating double-sided bonding film to form a stacking structure. This stacking structure has a central axis. This stacking structure includes a middle portion, and a first end portion and a second end portion located on opposite sides of the middle portion. A first groove is formed in the first copper sheet to divide the first copper sheet into a first part and a second part separated from each other. A second groove is formed in the second copper sheet to divide the second copper sheet into a third part and a fourth part separated from each other. The first groove and the second groove are respectively located on both sides of the central axis. An insulating solder mask is formed to cover the middle portion and fill the first groove and the second groove. A first end electrode is formed to cover the first end portion and a portion of the middle portion is covered by the insulating solder mask protective layer. A second end electrode is formed to cover the second end portion and a portion of the middle portion is covered by the insulating solder mask protective layer.

According to one embodiment of the present disclosure, the formation of the first trench and the formation of the second trench both include utilizing a lithography process and an etching process.

According to one embodiment of the present disclosure, the first trench and the second trench are symmetrical with respect to the central axis.

According to one embodiment of the present disclosure, the stacked structure has a first short side and a second short side facing each other. Forming the first trench includes forming the first trench adjacent to the first short side and spaced a first distance from the first short side. Forming the second trench includes forming the second trench adjacent to the second short side and spaced a second distance from the second short side. Both the first distance and the second distance are 1/4 to 1/3 of the length of the stacked structure.

According to one embodiment of the present disclosure, the width of the first trench and the second trench is 50 μm to 300 μm.

According to one embodiment of the present disclosure, the thermal conductivity of the aforementioned thermally conductive insulating double-sided laminate film is greater than 3 W/mK. The material of the thermally conductive insulating double-sided laminate film contains graphite flakes and/or graphene, and the carbon content of the thermally conductive insulating double-sided laminate film is greater than 90%.

According to one embodiment of the present disclosure, forming the first terminal electrode and forming the second terminal electrode both include forming a copper layer, forming a nickel layer covering the copper layer, and forming a tin layer covering the nickel layer. The distance between the upper surface of the copper layer and the upper surface of the insulating solder mask layer is equal to or greater than 5 μm.

100: Chip-type thermal pad

110: The First Copper Plate

112: First Groove

114: Part 1

116: Part 2

120: Second Copper Plate

122: Second Groove

124: Part 3

126: Part 4

130: Thermally conductive and insulating double-sided laminating film

132: Lower surface

134: Upper surface

140: Insulation solder mask protective layer

142: Upper surface

144: Insulation solder mask protective material

150: First electrode

152:Copper layer

152t: Upper surface

154: Nickel layer

156: Tin layer

160: Second electrode

162:Copper layer

162t: Upper surface

164: Nickel layer

166: Tin layer

170: Stacked Structure

170a: First short side

170b: Second short side

172:Middle part

174: First end

176: Second end

180: Photoresist layer

182: Photoresist layer

CA: Central axis

d1: First distance

d2: Second distance

H:Hot

L: Length

t1: thickness

t2: Thickness

t3: Thickness

W: Width

w1: width

w2: width

A better understanding of the present disclosure can be gained from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased to facilitate discussion.

Figure 1 is a schematic three-dimensional diagram of a chip-type thermal pad according to one embodiment of the present disclosure.

Figure 2 is a schematic top view of a chip-type thermal pad according to one embodiment of the present disclosure.

Figure 3 shows a schematic bottom view of a chip-type thermal pad according to one embodiment of the present disclosure.

Figure 4 is a schematic cross-sectional view of a chip-type thermal pad according to one embodiment of the present disclosure.

Figure 5 is a top view schematically illustrating a stacked structure of a chip-type thermal pad according to one embodiment of the present disclosure.

Figure 6 is a schematic diagram illustrating heat conduction of a chip-type thermally conductive patch according to one embodiment of the present disclosure.

Figures 7 to 9 and Figure 10A are schematic cross-sectional views of various stages in the manufacturing process of a chip-type thermal pad according to an embodiment of the present disclosure.

Figure 10B is a schematic top view of the structure of Figure 10A.

Figures 11 and 12A are schematic cross-sectional views of other stages in the manufacturing of a chip-type thermal pad according to an embodiment of the present disclosure.

Figure 12B is a schematic top view of the structure of Figure 12A.

Figure 13A is a schematic cross-sectional view of a chip-type thermal pad during a manufacturing process according to an embodiment of the present disclosure.

Figure 13B is a schematic top view of the structure of Figure 13A.

The following discusses embodiments of the present disclosure in detail. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustrative purposes only and are not intended to limit the scope of the present disclosure. All embodiments of the present disclosure disclose various features, which can be implemented individually or in combination as needed.

In addition, the terms "first," "second," etc., used herein do not specifically refer to order or sequence; they are merely used to distinguish between elements or operations described using the same technical term.

The spatial relationship between two components described in this disclosure applies not only to the orientations shown in the drawings but also to orientations not shown, such as inverted orientations. Furthermore, terms such as "connection," "electrical connection," or similar terms between two components in this disclosure are not limited to direct or electrical connections between the two components but may also include indirect or electrical connections as needed.

Please refer to Figures 1 to 4 , which respectively illustrate a schematic perspective view, a top view, a bottom view, and a cross-sectional view of a chip-type thermally conductive patch 100 according to one embodiment of the present disclosure. The chip-type thermally conductive patch 100 primarily includes a first copper sheet 110, a second copper sheet 120, a thermally conductive insulating double-sided lamination film 130, an insulating solder mask 140, a first end electrode 150, and a second end electrode 160.

As shown in Figures 3 and 4 , the first copper sheet 110 has a first trench 112. The first trench 112 extends longitudinally through the first copper sheet 110, dividing the first copper sheet 110 into a first portion 114 and a second portion 116. The first trench 112 extends through the first copper sheet 110 along the thickness t1 of the first copper sheet 110, separating the first portion 114 from the second portion 116. The thickness t1 of the first copper sheet 110 can be, for example, 100 μm to 300 μm. The shape of the first copper sheet 110 can be designed based on product requirements. In some embodiments, the first copper sheet 110 is rectangular.

The width w1 of the first trench 112 can be, for example, 50 μm to 300 μm. If the width w1 of the first trench 112 is less than 50 μm, the etching process may limit the possibility of incomplete etching of the first trench 112, resulting in electrical conduction between the first portion 114 and the second portion 116. If the width w1 of the first trench 112 is greater than 300 μm, the area of the first copper sheet 110 is excessively reduced, resulting in a smaller overlap area between the first copper sheet 110 and the second copper sheet 120, and poor vertical heat conduction between the first copper sheet 110 and the second copper sheet 120.

The size and shape of the second copper sheet 120 are the same as the size and shape of the first copper sheet 110. In some embodiments, as shown in Figures 2 and 4, the shape of the second copper sheet 120 is rectangular. The second copper sheet 120 has a second trench 122. The second trench 122 penetrates the second copper sheet 120 vertically, dividing the second copper sheet 120 into a third portion 124 and a fourth portion 126. The second trench 122 penetrates the second copper sheet 120 along the direction of the thickness t2 of the second copper sheet 120, separating the third portion 124 and the fourth portion 126 from each other. The thickness t2 of the second copper sheet 120 can be, for example, 100 μm to 300 μm. The width w2 of the second trench 122 can be, for example, 50 μm to 300 μm. If the width w2 of the second trench 122 is too small, the third portion 124 and the fourth portion 126 may not be completely separated. If the width w2 is too large, the vertical heat conduction between the first copper plate 110 and the second copper plate 120 may be poor.

The thermally conductive, insulating double-sided adhesive film 130 has a lower surface 132 and an upper surface 134, both of which are adhesive. The first copper sheet 110 is attached to the lower surface 132 of the thermally conductive, insulating double-sided adhesive film 130, and the second copper sheet 120 is attached to the upper surface 134, so that the thermally conductive, insulating double-sided adhesive film 130 is sandwiched between the first and second copper sheets 110, 120. The first groove 112 exposes a portion of the lower surface 132 of the thermally conductive, insulating double-sided adhesive film 130, while the second groove 122 exposes a portion of the upper surface 134. The second copper sheet 120 can be bonded to the first copper sheet 110 via the thermally conductive and insulating double-sided laminating film 130, forming a stacked structure 170 consisting of the first copper sheet 110, the thermally conductive and insulating double-sided laminating film 130, and the second copper sheet 120.

The stacking structure 170 has a central axis CA. The first trench 112 and the second trench 122 are located on either side of the central axis CA, i.e., on the left and right sides of the central axis CA, respectively. In some embodiments, the first trench 112 and the second trench 122 are symmetrical with respect to the central axis CA, i.e., the first trench 112 and the second trench 122 are symmetrical when rotated 180 degrees relative to each other. Please also refer to Figure 5, which is a top view of the stacking structure 170 of a chip-type thermal conductive patch 100 according to one embodiment of the present disclosure. In some embodiments, the stacking structure 170 is a rectangular parallelepiped structure having a length L and a width W. The stacking structure 170 has a first short side 170a and a second short side 170b that are opposite to each other. The first groove 112 is adjacent to the first short side 170a, and the second groove 122 is adjacent to the second short side 170b.

As shown in FIG4 , a first distance d1 is defined between the first trench 112 and the first short side 170a, and a second distance d2 is defined between the second trench 122 and the second short side 170b. The first distance d1 and the second distance d2 may be the same. However, depending on the product design, the first distance d1 and the second distance d2 may differ. In some exemplary embodiments, the first distance d1 and the second distance d2 are both within a range of 1/4 to 1/3 of the length L of the stacking structure 170. As shown in FIG4 , the stacking structure 170 includes a middle portion 172, a first end portion 174, and a second end portion 176, wherein the first end portion 174 and the second end portion 176 are located on opposite sides of the middle portion 172. The first groove 112 and the second groove 122 are both located in the middle portion 172.

The first and second trenches 112, 122 are offset from the stacking structure 170, adjacent to the first and second short sides 170a, 170b, respectively. This increases the overlapping area between the first and second copper sheets 110, 120 in the center portion 172, thereby enhancing heat conduction between the first and second copper sheets 110, 120. The first and second distances d1, d2 are designed to be between 1/4 and 1/3 of the length L of the stacking structure 170, taking into account both the size of the terminal electrodes and the heat conduction between the first and second copper sheets 110, 120.

In some embodiments, the thermal conductivity of the thermally conductive double-sided insulating film 130 is greater than 3 W/mK. In some exemplary embodiments, the material of the thermally conductive double-sided insulating film 130 includes graphite flakes and/or graphene, and the carbon content of the thermally conductive double-sided insulating film 130 is greater than 90%. Furthermore, the thickness t3 of the thermally conductive double-sided insulating film 130 should not be too thick to avoid affecting heat conduction between the first copper sheet 110 and the second copper sheet 120. The thickness t3 of the thermally conductive double-sided insulating film 130 can be, for example, 15 μm to 30 μm.

As shown in Figures 2 to 4 , the insulating solder mask layer 140 covers the middle portion 172 of the stacked structure 170, leaving the first end 174 and the second end 176 exposed. Because the first trench 112 and the second trench 122 are both located in the middle portion 172, the insulating solder mask layer 140 fills the first trench 112 and the second trench 122. The insulating solder mask layer 140 has an upper surface 142. For example, the insulating solder mask layer 140 may be made of epoxy, resin, or polyimide.

As shown in Figure 4 , the first end electrode 150 covers the first end 174 of the stacked structure 170 . The first end electrode 150 may cover the outer edge of the insulating solder mask layer 140 adjacent to the second short side 170b. For example, the first end electrode 150 may include a copper layer 152, a nickel layer 154, and a tin layer 156 to facilitate soldering to an external device such as a circuit board. The copper layer 152 first covers the exposed first end 174, the nickel layer 154 covers the copper layer 152, and the tin layer 156 covers the nickel layer 154. The copper layer 152 has an upper surface 152t, wherein the upper surface 152t is higher than the upper surface 142 of the insulating solder mask layer 140.

As shown in Figure 4 , the second end electrode 160 covers the second end portion 176 . The second end electrode 160 may cover the outer edge of the insulating solder mask layer 140 adjacent to the first short side 170a. For example, the second end electrode 160 may include a copper layer 162, a nickel layer 164, and a tin layer 166 to facilitate soldering to an external device such as a circuit board. The copper layer 162 first covers the exposed second end portion 176, the nickel layer 164 covers the copper layer 162, and the tin layer 166 covers the nickel layer 164. The copper layer 162 has an upper surface 162t, wherein the upper surface 162t is higher than the upper surface 142 of the insulating solder mask layer 140.

The distance between the upper surface 152t of the copper layer 152 and the upper surface 142 of the insulating solder mask layer 140, as well as the distance between the upper surface 162t of the copper layer 162 and the upper surface 142 of the insulating solder mask layer 140, are both equal to or greater than 5 μm to ensure reliable bonding between the chip-type thermal pad 100 and external devices.

Please refer to Figure 6, which is a schematic diagram illustrating heat conduction within a chip-type thermal patch 100 according to an embodiment of the present disclosure. When the chip-type thermal patch 100 is mounted on an external device such as a circuit board, heat H transferred from the external device to the chip-type thermal patch 100 can be conducted, for example, from the first portion 114 of the first copper sheet 110, through the thermally conductive double-sided adhesive film 130 sandwiched between the first and second copper sheets 110, 120, in the middle portion 172 of the stacked structure 170, to the fourth portion 126 of the second copper sheet 120, and then dissipated externally. In this manner, heat H can be conducted from one side of the chip-type thermal patch 100 to the other.

Furthermore, the first and second trenches 112 and 122 electrically isolate the first and second portions 114 and 116 of the first copper sheet 110, and the third and fourth portions 124 and 126 of the second copper sheet 120, respectively. Furthermore, the thermally conductive double-sided lamination film 130 electrically isolates the first and second copper sheets 110 and 120, enabling the chip-type thermal pad 100 to achieve both heat dissipation and circuit isolation.

Please refer to Figures 7 to 9, 10A, 11, 12A, and 13A, which are schematic cross-sectional views illustrating various stages of the manufacturing process of a chip-type thermally conductive patch 100 according to an embodiment of the present disclosure. In some embodiments, when manufacturing the chip-type thermally conductive patch 100 shown in Figures 1 to 4, the first copper sheet 110, the second copper sheet 120, and the thermally conductive double-sided laminating film 130 described above can be provided, as shown in Figure 7. The first copper sheet 110 is then laminated to the lower surface 132 of the thermally conductive double-sided laminating film 130, and the second copper sheet 120 is laminated to the upper surface 134 of the thermally conductive double-sided laminating film 130. In this way, the second copper sheet 120 can be bonded to the first copper sheet 110 and, together with the thermally conductive double-sided insulating film 130 and the first copper sheet 110, form a stacked structure 170. The stacked structure 170 has a central axis CA. Furthermore, the stacked structure 170 can be divided into a central portion 172 and first and second end portions 174 and 176 located on opposite sides of the central portion 172. The first and second end portions 174 and 176 provide for the subsequent placement of terminal electrodes.

After the stacked structure 170 is formed, a first trench 112 can be formed in the first copper sheet 110, and a second trench 122 can be formed in the second copper sheet 120, as shown in Figure 11 . In some embodiments, the first trench 112 and the second trench 122 are formed using lithography and etching techniques. Specifically, as shown in Figure 9 , two photoresist layers 180 and 182 can be formed, respectively, overlying the first copper sheet 110 and the second copper sheet 120, using methods such as printing or lamination. Photoresist layers 180 and 182 are located on opposite sides of the stacked structure 170.

Please refer to Figures 10A and 10B , where Figure 10B is a schematic top view of the structure of Figure 10A . Next, a lithography process including exposure and development is performed on the photoresist layers 180 and 182 to remove portions of the photoresist layers 180 and 182, exposing portions of the first copper sheet 110 and the second copper sheet 120, thereby defining the areas of the first copper sheet 110 and the second copper sheet 120 to be etched.

Next, as shown in FIG11 , the remaining photoresist layers 180 and 182 can be used as etching masks to perform an etching process, such as a wet etching process, on the exposed portions of the first copper sheet 110 and the exposed portions of the second copper sheet 120. The etching process removes the exposed portions of the first copper sheet 110 and the second copper sheet 120, thereby forming a first trench 112 in the first copper sheet 110 and a second trench 122 in the second copper sheet 120. The first trench 112 exposes a portion of the lower surface 132 of the thermally conductive double-sided adhesive film 130, thereby dividing the first copper sheet 110 into a first portion 114 and a second portion 116 separated from each other. The second groove 122 exposes a portion of the upper surface 134 of the thermally conductive and insulating double-sided lamination film 130, thereby dividing the second copper sheet 120 into a third portion 124 and a fourth portion 126 that are separated from each other.

The relative positional relationship between the first trench 112 and the second trench 122, their configuration within the stacked structure 170, and their dimensions have been described above and will not be further elaborated here.

After the first trench 112 and the second trench 122 are formed, the photoresist layers 180 and 182 can be removed. Referring to Figures 12A, 12B, 13A, and 13B, Figures 12B and 13B illustrate top views of the structures of Figures 12A and 13A, respectively. Next, as shown in Figures 13A and 13B, an insulating solder mask layer 140 can be formed to cover the central portion 172 of the stacked structure 170, for example, by printing, lamination, or photolithography. The insulating solder mask layer 140 fills the first trench 112 and the second trench 122. To form the insulating solder mask layer 140, a layer of insulating solder mask material 144 is first formed to cover the middle portion 172, first end portion 174, and second end portion 176 of the stacked structure 170, as shown in Figures 12A and 12B. The insulating solder mask material 144 covering the first end portion 174 and second end portion 176 is then removed to form the insulating solder mask layer 140.

Subsequently, as shown in Figures 1 to 4 , a first end electrode 150 is formed to cover the first end 174 of the stacked structure 170, and a second end electrode 160 is formed to cover the second end 176, thereby substantially completing the fabrication of the chip-type thermal patch 100. In some embodiments, forming the first end electrode 150 includes forming a copper layer 152 to cover the first end 174, forming a nickel layer 154 to cover the copper layer 152, and forming a tin layer 156 to cover the nickel layer 154. Forming the second end electrode 160 includes forming a copper layer 162 to cover the second end 176, forming a nickel layer 164 to cover the copper layer 162, and forming a tin layer 166 to cover the nickel layer 164. The relative heights between copper layers 152 and 162 and insulating solder mask layer 140 are as described above and will not be repeated here.

As can be seen from the above embodiments, the present disclosure replaces the traditional ceramic substrate with a stacked structure formed by laminating two copper sheets with a thermally conductive, insulating double-sided lamination film. Because copper's thermal conductivity is much greater than that of the ceramic substrate, the chip-type thermally conductive patch disclosed herein has excellent thermal conductivity and can effectively transfer heat.

The chip-type thermal pad disclosed herein can be directly soldered to a circuit board using surface mount technology to simultaneously provide heat dissipation and circuit isolation, thus offering excellent applicability.

Although the present disclosure has been disclosed above through the use of embodiments, this is not intended to limit the present disclosure. Anyone with ordinary skill in the art may make various modifications and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

100: Chip-type thermal pad

110: The First Copper Plate

112: First Groove

114: Part 1

116: Part 2

120: Second Copper Plate

122: Second Groove

124: Part 3

126: Part 4

130: Thermally conductive and insulating double-sided laminating film

132: Lower surface

134: Upper surface

140: Insulation solder mask protective layer

142: Upper surface

150: First electrode

152:Copper layer

152t: Upper surface

154: Nickel layer

156: Tin layer

160: Second electrode

162:Copper layer

162t: Upper surface

164: Nickel layer

166: Tin layer

170: Stacked Structure

170a: First short side

170b: Second short side

172:Middle part

174: First end

176: Second end

CA: Central axis

d1: First distance

d2: Second distance

t1: thickness

t2: Thickness

t3: Thickness

w1: width

w2: width

Claims (15)

A chip-type thermally conductive patch comprises: a first copper sheet having a first trench, wherein the first trench divides the first copper sheet into a first portion and a second portion separated from each other; a second copper sheet having a second trench, wherein the second trench divides the second copper sheet into a third portion and a fourth portion separated from each other; a thermally conductive double-sided laminating film sandwiched between the first copper sheet and the second copper sheet to bond the second copper sheet to the first copper sheet to form a stacked structure, wherein the stacked structure has a central axis, the first trench and the second trench are respectively located on opposite sides of the central axis, and the stacked structure includes a middle portion and a first end portion and a second end portion respectively located on opposite sides of the middle portion; an insulating solder mask layer covering the middle portion and exposing the first end portion and the second end portion, wherein the insulating solder mask layer fills the first trench and the second trench; a first end electrode covering the first end portion and a portion of the middle portion covered by the insulating solder mask layer; and a second end electrode covering the second end portion and a portion of the middle portion covered by the insulating solder mask layer. The chip-type thermal patch as described in claim 1, wherein the first trench and the second trench are symmetrical with respect to the central axis. A chip-type thermal patch as described in claim 1, wherein the stacking structure has a first short side and a second short side opposite to each other, the first trench and the second trench are adjacent to the first short side and the second short side respectively, and a first distance between the first trench and the first short side, and a second distance between the second trench and the second short side are both 1/4 to 1/3 of a length of the stacking structure. The chip-type thermal patch as described in claim 1, wherein a width of each of the first trench and the second trench is 50 μm to 300 μm. The chip-type thermally conductive patch as described in claim 1, wherein a thickness of one of the thermally conductive insulating double-sided bonding films is 15μm to 30μm. A chip-type thermally conductive patch as described in claim 1, wherein a thermal conductivity coefficient of the thermally conductive insulating double-sided adhesive film is greater than 3W/mK. A chip-type thermally conductive patch as described in claim 1, wherein one of the materials of the thermally conductive insulating double-sided laminating film contains graphite sheets and/or graphene, and the carbon content of the thermally conductive insulating double-sided laminating film is greater than 90%. The chip-type thermal pad as described in claim 1, wherein one material of the insulating solder mask protective layer includes epoxy resin, resin, or polyimide. A method for manufacturing a chip-type thermally conductive patch includes: laminating a first copper sheet and a second copper sheet onto a lower surface and an upper surface of a thermally conductive double-sided laminating film, respectively, to form a stacked structure, wherein the stacked structure has a central axis and includes a middle portion and a first end portion and a second end portion located on opposite sides of the middle portion; forming a first trench in the first copper sheet to divide the first copper sheet into a first portion and a second portion that are separated from each other; forming a second trench in the second copper sheet to divide the second copper sheet into a third portion and a fourth portion that are separated from each other, wherein the first trench and the second trench are located on opposite sides of the central axis; An insulating solder mask layer is formed to cover the middle portion and fill the first trench and the second trench; a first end electrode is formed to cover the first end portion and a portion of the middle portion covered by the insulating solder mask layer; and a second end electrode is formed to cover the second end portion and a portion of the middle portion covered by the insulating solder mask layer. The method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein forming the first trench and forming the second trench both include utilizing a lithography process and an etching process. A method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein the first trench and the second trench are symmetrical with respect to the central axis. A method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein the stacking structure has a first short side and a second short side opposite to each other, and forming the first trench includes making the first trench adjacent to the first short side and separated from the first short side by a first distance, and forming the second trench includes making the second trench adjacent to the second short side and separated from the second short side by a second distance, wherein each of the first distance and the second distance is 1/4 to 1/3 of a length of the stacking structure. The method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein a width of each of the first trench and the second trench is 50 μm to 300 μm. A method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein a thermal conductivity coefficient of the thermally conductive insulating double-sided adhesive film is greater than 3W/mK, a material of the thermally conductive insulating double-sided adhesive film contains graphite sheets and/or graphene, and the carbon content of the thermally conductive insulating double-sided adhesive film is greater than 90%. A method for manufacturing a chip-type thermally conductive patch as described in claim 9, wherein forming the first end electrode and forming the second end electrode both include: forming a copper layer; forming a nickel layer covering the copper layer; and forming a tin layer covering the nickel layer, wherein a distance between an upper surface of the copper layer and an upper surface of the insulating solder mask layer is equal to or greater than 5μm.