TWI898188B - Method of fabricating storage capacitor with multiple dielectrics - Google Patents

Abstract

The present application provides a method of fabricating a storage capacitor. The method includes steps of forming a lower electrode; depositing a first dielectric layer covering the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.

Description

Method for preparing multi-layer dielectric storage capacitor

This application claims priority to and the benefit of U.S. Patent Application Nos. 17/751,936 and 17/752,638, filed on May 24, 2022, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for preparing a semiconductor structure having multiple dielectric layers, and more particularly to a method for preparing a capacitor as a semiconductor storage device having multiple dielectric layers.

Dynamic random access memory (DRAM) uses capacitors to store information bits in integrated circuits. Capacitors are fabricated by placing a dielectric material between two electrodes formed of conductive material. The capacitor's charge-holding capacity (i.e., capacitance) is a function of the surface area of the electrodes, the distance between the electrodes, and the (relative) dielectric constant, or k value, of the dielectric material. Capacitance is directly proportional to the dielectric constant, or k value, of the dielectric material. In other words, the higher the dielectric constant, or k value, of the dielectric material, the greater the charge the capacitor can hold. Therefore, for a given desired capacitance, increasing the dielectric constant, or k value, allows the capacitor's area to be reduced to maintain the same capacitance.

The above "prior art" description is merely to provide background information and does not constitute an admission that the above "prior art" description discloses the subject matter of the present disclosure. Furthermore, any description of the above "prior art" should not be considered as part of this application.

One aspect of the present disclosure provides a storage capacitor. The storage capacitor includes a lower electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer, and an upper electrode. The first dielectric layer covers the lower electrode. The second dielectric layer is disposed on the first dielectric layer. The third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.

In some embodiments, the first dielectric layer and the second dielectric layer include different materials.

In some embodiments, the first dielectric layer and the third dielectric layer include the same material.

In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer include metal oxide.

In some embodiments, the first dielectric layer includes einsteinium, zirconium, niobium, aluminum, or titanium.

In some embodiments, the second dielectric layer includes einsteinium or zirconium.

In some embodiments, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness greater than the first thickness, and the third dielectric layer has a third thickness less than the second thickness.

In some embodiments, the sum of the first thickness and the third thickness is substantially less than the second thickness.

In some embodiments, the ratio of the second thickness to the sum of the first thickness and the third thickness is substantially greater than 4.

In some embodiments, the lower electrode is columnar, a portion of the first dielectric layer connected to an outer surface of the lower electrode has a first outer diameter and a first inner diameter, a portion of the second dielectric layer surrounding the outer surface of the lower electrode has a second outer diameter and a second inner diameter, and a portion of the third dielectric layer surrounding the outer surface of the lower electrode has a third outer diameter and a third inner diameter. A first difference between the first outer diameter and the first inner diameter is smaller than a second difference between the second outer diameter and the second inner diameter, and a third difference between the third outer diameter and the third inner diameter is smaller than the second difference.

In some embodiments, the sum of the first difference and the third difference is substantially less than 2 nanometers.

In some embodiments, the sum of the first difference and the third difference is substantially greater than 0.3 nanometers.

In some embodiments, the upper electrode has a substantially planar top surface.

In some embodiments, the top electrode is cylindrical, a portion of the first dielectric layer surrounding an outer surface of the top electrode has a first outer diameter and a first inner diameter, a portion of the second dielectric layer surrounding the outer surface of the top electrode has a second outer diameter and a second inner diameter, and a portion of the third dielectric layer connected to the outer surface of the top electrode has a third outer diameter and a third inner diameter. A first difference between the first outer diameter and the first inner diameter is smaller than a second difference between the second outer diameter and the second inner diameter, and a third difference between the third outer diameter and the third inner diameter is smaller than the second difference.

In some embodiments, the sum of the first difference and the third difference is substantially less than 2 nanometers.

In some embodiments, the sum of the first difference and the third difference is substantially greater than 0.3 nanometers.

In some embodiments, the lower electrode is a doped region of a substrate, and the first dielectric layer, the second dielectric layer, the third dielectric layer, and the upper electrode are disposed in the substrate.

One aspect of the present disclosure provides a method for fabricating a storage capacitor. The method comprises the following steps: forming a lower electrode; depositing a first dielectric layer to cover the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.

In some embodiments, the first dielectric layer has a first thickness, the second dielectric layer has a second thickness greater than the first thickness, and the third dielectric layer has a third thickness less than the second thickness.

In some embodiments, the sum of the first thickness and the third thickness is substantially less than the second thickness.

In some embodiments, the ratio of the second thickness to the sum of the first thickness and the third thickness is substantially greater than 4.

In some embodiments, the first dielectric layer and the second dielectric layer include different metal oxides.

In some embodiments, the first dielectric layer and the third dielectric layer include the same material.

In some embodiments, the second dielectric layer includes einsteinium or zirconium.

In some embodiments, the first dielectric layer includes einsteinium, zirconium, niobium, aluminum, or titanium.

In some embodiments, forming the bottom electrode includes the following steps: forming a trench in a substrate and doping a portion of the substrate exposed in the trench to form the bottom electrode; then depositing the first dielectric layer, the second dielectric layer, and the third dielectric layer in the trench, and depositing a conductive material for the top electrode on the third dielectric layer until the trench is completely filled.

In some embodiments, the preparation method further includes performing a planarization process to remove the first dielectric layer, the second dielectric layer, the third dielectric layer, and the conductive material on the substrate.

In some embodiments, forming the bottom electrode comprises the following steps: depositing a sacrificial layer on a substrate; forming a trench in the sacrificial layer; and depositing a conductive material of the bottom electrode in the trench until the trench is completely filled.

In some embodiments, the preparation method further includes performing a planarization process to remove the conductive material on the sacrificial layer.

In some embodiments, the preparation method further includes removing the sacrificial layer before depositing the first dielectric layer.

With the storage capacitor configured as described above, including three dielectric layers serving as the capacitor dielectric to electrically isolate the upper and lower electrodes, the effective dielectric constant of the capacitor dielectric can be increased. Therefore, a storage capacitor of a given size can hold a larger charge.

The foregoing has broadly outlined the technical features and advantages of the present disclosure to facilitate a better understanding of the detailed description of the present disclosure set forth below. Other technical features and advantages that constitute the subject matter of the patent applications of the present disclosure are described below. Those skilled in the art will appreciate that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same objectives as those of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure as defined in the appended patent applications.

10: Storage capacitor

20: Storage capacitor

100: Base

102: Canal

104: Upper surface

110: Lower electrode

120: First dielectric layer

122: First outer diameter

124: First inner diameter

130: Second dielectric layer

132: Second outer diameter

134: Second inner diameter

140: Third dielectric layer

142: Third Outer Diameter

144: Third inner diameter

150: Conductive materials

152: Upper electrode

154: External surface

200: Base

202: Semiconductor Wafer

2021: Upper surface

2022: Active Zone

203: Isolation characteristics

204: Access transistor

2042: Gate

2044: Impurity Zone

2046: Gate dielectric

2048: Gate Gap

206: Insulating layer

208: Conductive characteristics (conductive plug)

210: Conductive materials

212: Lower electrode

214: External surface

220: First dielectric layer

222: First outer diameter

224: First inner diameter

230: Second dielectric layer

232: Second outer diameter

234: Second inner diameter

240: Third dielectric layer

242: Third Outer Diameter

244: Third inner diameter

250: Upper electrode (top electrode)

252: Top

300: Preparation Method

410: Pattern Mask

414: Window

420: Sacrifice Layer

422: Canal

430: Graphics Mask

500: Preparation Method

A-A':line

B-B': line

D1: First Difference

D2: Second Difference

D3: Third Difference

S302: Step

S304: Step

S306: Step

S310: Step

S312: Step

S314: Step

S316: Step

S502: Step

S504: Step

S506: Step

S508: Step

S510: Step

S512: Step

S514: Step

S516: Step

S518: Step

T1: First thickness

T2: Second thickness

T3: Third thickness

A more complete understanding of the disclosure of this application can be obtained by referring to the embodiments and the claims together with the drawings. Identical reference numerals in the drawings refer to identical elements.

Figure 1 is a cross-sectional view illustrating a storage capacitor according to some embodiments of the present disclosure.

Figure 2 is a cross-sectional view along line AA' in Figure 1.

FIG3 is a cross-sectional view illustrating a storage capacitor according to some embodiments of the present disclosure.

Figure 4 is a cross-sectional view along line BB' in Figure 3.

FIG5 is a flow chart illustrating a method for preparing a storage capacitor according to some embodiments of the present disclosure.

Figures 6 to 12 are cross-sectional views illustrating intermediate stages in the preparation of storage capacitors according to some embodiments of the present disclosure.

FIG13 is a flow chart illustrating a method for preparing a storage capacitor of a semiconductor storage device according to some embodiments of the present disclosure.

Figures 14 to 20 are cross-sectional views illustrating intermediate stages in the preparation of storage capacitors according to some embodiments of the present disclosure.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure, as illustrated in the accompanying drawings. It should be understood that no limitation of the scope of the present disclosure is intended. Any changes or modifications to the described embodiments, as well as any further application of the principles described herein, should be considered as routinely made by one of ordinary skill in the art to which the present disclosure pertains. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numerals.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the present inventive concept.

The terms used herein are for describing particular embodiments only and are not intended to limit the concepts of the present invention. As used herein, the singular forms "a," "an," and "the" include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprising" and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG1 is a cross-sectional view illustrating a storage capacitor 10 according to some embodiments of the present disclosure. Referring to FIG1 , storage capacitor 10 is a trench capacitor comprising a bottom electrode 110, a first dielectric layer 120, a second dielectric layer 130, a third dielectric layer 140, and an upper electrode 152. Bottom electrode 110 is a conductive doped region of substrate 100, while first dielectric layer 120, second dielectric layer 130, third dielectric layer 140, and upper electrode 152 are disposed within substrate 100. Bottom electrode 110 is in direct contact only with substrate 100 and first dielectric layer 120.

The lower electrode 110 and the upper electrode 152 are electrically isolated from each other by the first dielectric layer 120, the second dielectric layer 130, and the third dielectric layer 140. In other words, the first dielectric layer 120, the second dielectric layer 130, and the third dielectric layer 140 serve as the capacitive dielectric of the storage capacitor 10. As shown in FIG1 , the first dielectric layer 120 covers the lower electrode 110, and the second dielectric layer 130 is disposed between the first dielectric layer 120 and the third dielectric layer 140.

First dielectric layer 120 and second dielectric layer 130 have different materials to increase the effective dielectric constant of the capacitor dielectric of storage capacitor 10. Furthermore, first dielectric layer 120 and third dielectric layer 140 may comprise the same material to facilitate the formation of storage capacitor 10. First dielectric layer 120, second dielectric layer 130, and third dielectric layer 140 comprise metal oxides. For example, first dielectric layer 120 and third dielectric layer 140 may comprise cobalt, zirconium, niobium, aluminum, or titanium, while second dielectric layer 130 may comprise cobalt or zirconium.

Referring to FIG. 2 , the top electrode 152 is cylindrical and includes an outer surface 154. A portion of the first dielectric layer 120 surrounding the outer surface 154 of the top electrode 152 includes a first outer diameter 122 and a first inner diameter 124, while a portion of the second dielectric layer 130 surrounding the outer surface 154 of the top electrode 152 has a second outer diameter 132 and a second inner diameter 134. In some embodiments, a first difference D1 between the first outer diameter 122 and the first inner diameter 124 is smaller than a second difference D2 between the second outer diameter 132 and the second inner diameter 134, thereby further improving the dielectric constant of the storage capacitor 10.

Furthermore, a portion of the third dielectric layer connected to the outer surface 154 of the top electrode 152 has a third outer diameter 142 and a third inner diameter 144, and a third difference D3 between the third outer diameter 142 and the third inner diameter 144 is less than a second difference D2 between the second outer diameter 132 and the second inner diameter 134. In some embodiments, the sum of the first difference D1 and the third difference D3 is substantially less than 2 nanometers. Furthermore, the sum of the first difference D1 and the third difference D3 is substantially greater than 0.3 nanometers. In some embodiments, the first difference D1, the second difference D2, and the third difference D3 can be obtained by energy dispersive X-ray (EDX) measurement.

FIG3 is a cross-sectional view illustrating a storage capacitor 20 according to some embodiments of the present disclosure. Referring to FIG3 , the storage capacitor 20 includes a lower electrode 212, a first dielectric layer 220 covering the lower electrode 212, a second dielectric layer 230 disposed on the first dielectric layer 220, a third dielectric layer 240 disposed on the second dielectric layer 230, and an upper electrode 250 disposed on the third dielectric layer 240. The lower electrode 212 may be disposed on a substrate 200, which may include an access transistor (not shown) formed therein. Substrate 200 may include multiple layers of different materials, each with regions of different materials or structures, used to fabricate integrated circuits, active microelectronic components (such as transistors and/or diodes), and passive microelectronic components (such as capacitors and resistors). The aforementioned materials may include semiconductors, insulators, conductors, or combinations thereof.

The first dielectric layer 220, the second dielectric layer 230, and the third dielectric layer 240 serve as a capacitor dielectric, electrically isolating the lower electrode 212 from the upper electrode 250. The capacitor dielectric, including the first dielectric layer 220, the second dielectric layer 230, and the third dielectric layer 240, can conform to the substrate 200 and the lower electrode 212, with the upper electrode 250 having a substantially planar top surface 252. Alternatively, the upper electrode 250 can have a uniform thickness. The first dielectric layer 220 and the second dielectric layer 230 can include different metal oxides, while the first dielectric layer 220 and the third dielectric layer 240 can include the same metal oxide. For example, the first dielectric layer 220 and the third dielectric layer 240 include cobalt, zirconium, niobium, aluminum, or titanium, and the second dielectric layer 230 includes cobalt or zirconium.

4 , a portion of the first dielectric layer 220 connected to the outer surface 214 of the lower electrode 212 includes a first outer diameter 222 and a first inner diameter 224. A portion of the second dielectric layer 230 surrounding the outer surface 214 of the lower electrode 212 has a second outer diameter 232 and a second inner diameter 234, and a first difference D1 between the first outer diameter 222 and the first inner diameter 224 is smaller than a second difference D2 between the second outer diameter 232 and the second inner diameter 234. Furthermore, a portion of the third dielectric layer 240 surrounding the outer surface 214 of the lower electrode 212 has a third outer diameter 242 and a third inner diameter 244, and a third difference D3 between the third outer diameter 242 and the third inner diameter 244 is smaller than the second difference D2. In some embodiments, the sum of the first difference D1 and the third difference D3 is in the range of about 0.3 to about 2 nanometers.

Figure 5 is a flow chart illustrating a method 300 for preparing a storage capacitor 10 according to some embodiments of the present disclosure, while Figures 6 through 12 are cross-sectional views illustrating intermediate stages in the preparation of the storage capacitor 10 according to some embodiments of the present disclosure. The stages illustrated in Figures 6 through 12 refer to the flow chart in Figure 5 . In the following discussion, the preparation stages illustrated in Figures 6 through 12 are discussed with reference to the process steps illustrated in Figure 5 .

Referring to Figures 6 and 7 , according to step S302 in Figure 5 , a trench 102 is formed in substrate 100. Trench 102 has a substantially vertical sidewall. Substrate 100 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer or gradient substrate, or the like. Substrate 100 can include any semiconductor material, such as silicon, germanium, or similar elemental semiconductors; or silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or similar compound or alloy semiconductors.

The formation of the trench 102 may include: (1) forming a pattern mask 410 on the substrate 100, wherein the pattern mask 410 defines a trench pattern to be etched into the substrate 100, and (2) performing an etching process, such as a dry etching process, to remove portions of the substrate 100 not protected by the pattern mask 410, thereby forming the trench 102 in the substrate 100.

The pattern mask 410 can be a photoresist mask or a hard mask. The manufacturing technique for the pattern mask 410, which includes a photosensitive material, can include performing at least one exposure process and at least one development process on the photosensitive material so as to completely cover the substrate 100. The photosensitive material can be applied to the substrate 100 via a spin coating process and then dried using a soft bake process. Alternatively, the pattern mask 410, which functions as a hard mask, can include polysilicon, carbon, an inorganic material (such as nitride), or other suitable materials.

The substrate 100 is etched, for example, using a reactive ion etching (RIE) process, such that the width of the window 414 in the patterned mask 410 remains within the trench 102. After the trench 102 is formed, a wet chemical clean or other cleaning process can be performed to substantially remove any surface contaminants that may remain in the trench 102. After the trench 102 is prepared, the patterned mask 410 is removed using a suitable process. The patterned mask 410 comprising a photosensitive material is removed using an ashing process or a wet stripping process, while the patterned mask 410 serving as a hard mask is removed using a wet etching process.

8 , according to step S304 in FIG5 , a dopant is introduced into a portion of the substrate 100 exposed to the trench 102 to form a lower electrode 110. Formation of the lower electrode 110 may include: (1) depositing a sacrificial material (not shown) to partially fill the trench 102, (2) forming a passivation layer (not shown) on the exposed portion of the substrate 100 and the sacrificial material, (3) removing a horizontal portion of the passivation layer, (4) removing the sacrificial material, (5) introducing a dopant only into a portion of the substrate 100 not protected by the remaining passivation layer, and (6) removing the remaining passivation layer. The dopant may be introduced into the portion of substrate 100 by, for example, outdiffusion of a disposable material including the dopant (such as doped silicate glass) or by ion implantation. The doped region of substrate 100 may be n-type or p-type.

9 , according to step S306 in FIG5 , a first dielectric layer 120 is deposited on the exposed portions of the substrate 100. The first dielectric layer 120 is conformally and uniformly deposited on the trenches 102 and the upper surface 104 of the substrate 100, but does not completely fill the trenches 102. As shown in FIG9 , the first dielectric layer 120 has a substantially uniform first thickness T1 and has a profile that follows the exposed portions of the substrate 110 in the trenches 102. The first dielectric layer 120 includes a first metal oxide. The first metal oxide can be selected from niobium oxide (HfO2), zirconium dioxide (ZrO2), niobium oxide (Nb2O5), aluminum oxide (Al2O3), or titanium dioxide (TiO2). For example, the deposition technique for the first dielectric layer 120 may include, for example, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process, wherein the first dielectric layer 120 deposited by the ALD process has a highly uniform thickness.

Referring to FIG. 10 , according to step S310 in FIG. 5 , a second dielectric layer 130 is deposited on the first dielectric layer 120 . The second dielectric layer 130 has a substantially uniform second thickness T2, covering the first dielectric layer 120 but not completely filling the trench 102 . In some embodiments, the second thickness T2 is greater than the first thickness T1 , as shown in FIG. The second dielectric layer 130 may include a second metal oxide different from the first metal oxide. For example, the second dielectric layer 130 may be selected from bismuth oxide and zirconium dioxide. For example, the second dielectric layer 130 may be fabricated using a PVD process, an ALD process, or a CVD process.

Referring to Figure 11 , according to step S312 in Figure 5 , a third dielectric layer 140 is deposited on the second dielectric layer 130 . The third dielectric layer 140 is conformally and uniformly deposited within the trench 102 and on the upper surface 104 of the substrate 100 , but does not completely fill the trench 102 . The third dielectric layer 140 includes a first metal material and can be fabricated using a PVD process, a CVD process, or an ALD process.

Referring to Figures 9 through 11 , the third dielectric layer 140 has a third thickness T3 that is less than the second thickness T2 of the second dielectric layer 130. Furthermore, the sum of the first thickness T1 and the third thickness T3 is substantially less than the second thickness T2, thereby increasing the effective dielectric constant of the first through third dielectric layers 120 through 140. In some embodiments, the ratio of the second thickness T2 to the sum of the first thickness T1 and the third thickness T3 is substantially greater than 4.

Referring to FIG. 12 , according to step S314 in FIG. 5 , a conductive material 150 is deposited to fill the trench 102 . The conductive material 150 is conformally and uniformly deposited on the substrate 100 and in the trench 102 until the trench 102 is completely filled, thereby facilitating the deposition of the conductive material 150 . The conductive material 150 may include polysilicon or a metal such as tungsten, copper, aluminum, molybdenum, titanium, niobium, ruthenium, or a combination thereof. The conductive material 150 may be formed using a CVD process, a PVD process, an ALD process, or other suitable processes.

After depositing the conductive material 150, a planarization process is performed, according to step S316 in FIG. 5 , to remove the first dielectric layer 120, the second dielectric layer 130, the third dielectric layer 140, and the portion of the conductive material 150 above the upper surface 104 of the substrate 100. This forms a pillar-shaped top electrode 152, thereby forming the storage capacitor 10 shown in FIG. Excess first dielectric layer 120, excess second dielectric layer 130, excess third dielectric layer 140, and excess conductive material 150 can be removed from the substrate 100 using, for example, a chemical mechanical polishing (CMP) process.

FIG13 is a flow chart illustrating a method 500 for preparing a storage capacitor 20 according to some embodiments of the present disclosure, while FIG14 through FIG20 are cross-sectional views illustrating intermediate stages in the preparation of the storage capacitor 20 according to some embodiments of the present disclosure. The stages shown in FIG14 through FIG20 refer to the flow chart of FIG13 . In the following discussion, the preparation stages shown in FIG14 through FIG20 are discussed with reference to the process steps shown in FIG13 .

Referring to FIG. 14 , according to step S502 in FIG. 13 , a sacrificial layer 420 is deposited on a substrate 200 . In some embodiments, the substrate 200 includes a semiconductor wafer 202 , an access transistor 204 , an insulating layer 206 , and a conductive feature 208 . The access transistor 204 includes a gate 2042 , a plurality of impurity regions 2044 , and a gate dielectric 2046 . The gate 2042 is disposed on the semiconductor wafer 202 . The impurity regions 2044 are disposed within the semiconductor wafer 202 and on both sides of the gate 2042 . The gate dielectric 2046 is sandwiched between the semiconductor wafer 202 and the gate 2042. That is, the access transistor 204 shown in FIG14 is in the form of a planar access device (PAD) transistor; however, in some embodiments, the access transistor 204 may be a recessed access device (RAD) transistor.

In some embodiments, gate 2042 may include, but is not limited to, doped polysilicon, or a metal-containing material including tungsten, titanium, or metal silicide. The dopant region 2044 serves as the drain and source regions of the access transistor 204 . Its fabrication technique may include introducing dopants into the semiconductor wafer 202 . Techniques for introducing dopants into the semiconductor wafer 202 include diffusion processes or ion implantation processes. If the corresponding access transistor 204 is a p-type transistor, boron or indium may be used for dopant introduction; if the corresponding access transistor 204 is an n-type transistor, phosphorus, arsenic, or antimony may be used for dopant introduction.

Gate dielectric 2046 is used to maintain capacitive coupling between gate 2042 and the drain and source regions. Gate dielectric 2046 can include oxide, nitride, oxynitride, or a high-k (dielectric constant) material. Access transistor 204 may also include gate spacers 2048 on the sidewalls of gate 2042 and gate dielectric 2046. The gate spacer 2048 fabrication technique may optionally include depositing a spacer material (e.g., silicon nitride or silicon dioxide) to cover the gate 2042 and the gate dielectric 2046, and performing an anisotropic etch to remove the spacer material from the horizontal surfaces of the gate 2042 and the gate dielectric 2046.

Isolation features 203, such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features, may be introduced into the semiconductor wafer 202 to define an active area 2022, wherein the access transistor 204 is formed in the active area 2022.

The insulating layer 206 covers the semiconductor wafer 202 and the access transistor 204. The insulating layer 206 may be formed by, for example, uniformly depositing a dielectric material using a chemical vapor deposition (CVD) process or a spin coating process to cover the upper surface 2021 of the semiconductor wafer 202 and the access transistor 204. In some embodiments, the insulating layer 206 may be planarized using, for example, a chemical mechanical polishing (CMP) process to produce an acceptably flat surface. The insulating layer 206 may include oxide, tetraethyl orthosilicate (TEOS), undoped silicate glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), toner silazane (TOSZ), or a combination thereof.

Conductive plug 208 penetrates insulating layer 206 and contacts one of the impurity regions 2044 of access transistor 202. Conductive plug 208 may include tungsten. Alternatively, doped polysilicon may be used as the conductive material for forming conductive plug 208. Fabrication techniques for conductive plug 208 may include a damascene process within insulating layer 206.

The sacrificial layer 420 is deposited on the substrate 200 using a spin coating process or a CVD process. After deposition, the sacrificial layer 420 can be planarized, for example, using a chemical mechanical polishing (CMP) process, to produce an acceptably flat surface. As described below, this flat surface allows for the use of lithography equipment with a smaller depth of field for patterning the trenches. In some embodiments, the sacrificial layer 420 comprises a material that provides sufficient selectivity between the insulating layer 206 and the conductive plug 208. The sacrificial layer 420 can include a different dielectric material than the insulating layer 206. In some embodiments, the sacrificial layer 420 comprises silicon oxide or silicon nitride.

Next, a pattern mask 430 is formed on the sacrificial layer 420. The pattern mask 430 defines the trench pattern to be etched through the sacrificial layer 420. The pattern mask 430 may include a photosensitive material, and the trench pattern may be defined using a lithography process. Alternatively, the pattern mask 430 may be a hard mask.

Referring to FIG. 15 , according to step S504 in FIG. 13 , an etching process is performed to remove a portion of sacrificial layer 420 not protected by patterned mask 430. Consequently, trenches 422 are formed, exposing a portion of substrate 200. Sacrificial layer 420 is etched using, for example, an RIE process. After trenches 422 are formed, patterned mask 430, including the photosensitive material, is removed using an ashing process or a wet stripping process. The wet stripping process chemically alters patterned mask 430 so that it no longer adheres to sacrificial layer 420. Patterned mask 430, which serves as a hard mask, is removed using a wet etching process. 14 and 15 , the conductive plug 208 can be exposed through the trench 422 .

Referring to FIG. 16 , according to step S506 in FIG. 13 , a deposition process is performed to fill the trench 422 with the conductive material 210 . The conductive material 210 can be deposited using, for example, a low-pressure CVD process. The conductive material 210 is uniformly deposited on the substrate 200 and the sacrificial layer 420 until the trench 422 is completely filled, thereby facilitating the deposition of the conductive material 210 . The conductive material 210 can be formed using techniques such as doped polysilicon or metals such as titanium nitride (TiN) or ruthenium (Ru).

Next, the fabrication method 500 proceeds to step S508 , where a planarization process is performed to remove the conductive material 210 above the sacrificial layer 420 . This forms a pillar-shaped lower electrode 212 . In some embodiments, the lower electrode 212 may contact the conductive plug 208 shown in FIG. 14 . After removing excess conductive material 210, the sacrificial layer 420 is exposed. After the formation of the lower electrode 212 is complete, the fabrication method 500 proceeds to step S510 , where the sacrificial layer 420 is removed using a suitable technique. This exposes the substrate 200 , as shown in FIG. 17 .

Referring to FIG. 18 , according to step S512 in FIG. 13 , a first dielectric layer 220 is deposited to cover the lower electrode 212 . The first dielectric layer 220 includes a first metal oxide and is deposited on the substrate 200 and the lower electrode 212 . In some embodiments, the first dielectric layer 220 has a substantially uniform first thickness T1, whose configuration follows that of the substrate 200 and the lower electrode 212 . For example, the first dielectric layer 220 may include cobalt, zirconium, niobium, aluminum, or titanium. For example, the first dielectric layer 220 may be deposited using a CVD process or an ALD process.

Referring to FIG. 19 , according to step S514 in FIG. 13 , a second dielectric layer 230 is deposited on the first dielectric layer 220 . The second dielectric layer 230 is deposited on the first dielectric layer 220 until the second dielectric layer 230 has a second thickness T2 . Referring to FIG. 18 and FIG. 19 , in some embodiments, the second thickness T2 is greater than the first thickness T1 . The second metal oxide is different from the first metal oxide. For example, the second dielectric layer 230 may include einsteinium or zirconium. For example, the second dielectric layer 230 may include the second metal oxide and may be deposited using a CVD process.

Referring to FIG. 20 , according to step S516 in FIG. 13 , a third dielectric layer 240 is deposited on the second dielectric layer 230 . The third dielectric layer 204 is deposited using a CVD process and includes a first metal oxide. Referring to FIG. 18 to FIG. 20 , the third dielectric layer 204 has a third thickness T3 that is less than the second thickness T2. The sum of the first thickness T1 and the third thickness T3 is substantially less than the second thickness T2. In some embodiments, the ratio of the second thickness T2 to the sum of the first thickness T1 and the third thickness T3 is substantially greater than 4.

Next, the fabrication method 500 proceeds to step S518, where a top electrode 250 is deposited on the third dielectric layer 240. The top electrode 250 can be a conformal layer having a substantially uniform thickness. In some embodiments, the top electrode 250 can comprise a low-resistivity material such as titanium nitride or a combination of titanium nitride, tungsten nitride, ruthenium, iridium, and platinum. Thus, the storage capacitor 20 shown in FIG. 3 is formed. The top electrode 250 is deposited until it has a substantially smooth surface.

In summary, the configuration of storage capacitor 10/20, including first dielectric layer 120/220, second dielectric layer 130/230, and third dielectric layer 140/240, can increase the effective dielectric constant of the capacitor's dielectric. Consequently, storage capacitor 10/20 can hold a larger charge within a given area.

One aspect of the present disclosure provides a storage capacitor. The storage capacitor includes a lower electrode, a first dielectric layer, a second dielectric layer, a third dielectric layer, and an upper electrode. The first dielectric layer covers the lower electrode. The second dielectric layer is disposed on the first dielectric layer. The third dielectric layer is disposed on the second dielectric layer. The upper electrode is disposed on the third dielectric layer.

One aspect of the present disclosure provides a method for fabricating a storage capacitor. The method comprises the following steps: forming a lower electrode; depositing a first dielectric layer to cover the lower electrode; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; and forming an upper electrode on the third dielectric layer.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that they can use existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included within the scope of this application.

10: Storage capacitor

110: Lower electrode

120: First dielectric layer

130: Second dielectric layer

140: Third dielectric layer

152: Upper electrode

A-A': line

Claims (9)

A method for preparing a storage capacitor comprises: forming a trench in a substrate, wherein the trench has a substantially vertical sidewall and is circular in a top view; performing diffusion doping on a first portion of the substrate exposed in the trench to form a lower electrode, wherein the lower electrode has a vertical sidewall adjacent to the trench; depositing a first dielectric layer in the trench to cover the lower electrode and an upper surface of the substrate, wherein the first dielectric layer extends from the upper surface of the substrate to a bottom of the trench, the first dielectric layer contacting the substrate in the trench and covering all of the sidewalls of the trench; Depositing a second dielectric layer in the trench and on the first dielectric layer to cover the first dielectric layer and the upper surface of the substrate; Depositing a third dielectric layer in the trench and on the second dielectric layer to cover the second dielectric layer and the upper surface of the substrate; and Depositing a conductive material on the third dielectric layer until the trench is completely filled to form a top electrode, wherein the top electrode covers the upper surface of the substrate and a portion of the top electrode located in the trench has a vertical sidewall. Forming the bottom electrode includes: Depositing a sacrificial material to fill the first portion of the trench; A passivation layer is formed on a second portion of the substrate and the sacrificial material, wherein the second portion is located in the trench adjacent to the first portion and exposed to the sacrificial material; a horizontal portion of the passivation layer is removed; the sacrificial material is removed, wherein a remaining portion of the passivation layer covers the second portion of the substrate; and a dopant is introduced only into the first portion of the substrate exposed to the trench to diffusely dope the first portion and the remaining portion of the passivation layer is removed, wherein the bottom electrode is in direct contact only with the substrate and the first dielectric layer. The preparation method of claim 1, wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness greater than the first thickness, and the third dielectric layer has a third thickness less than the second thickness. A preparation method as described in claim 2, wherein the sum of the first thickness and the third thickness is substantially less than the second thickness. A preparation method as described in claim 2, wherein the ratio of the second thickness to the sum of the first thickness and the third thickness is substantially greater than 4. The preparation method of claim 1, wherein the first dielectric layer and the second dielectric layer comprise different metal oxides. The preparation method of claim 5, wherein the first dielectric layer and the third dielectric layer comprise the same material. The preparation method of claim 5, wherein the second dielectric layer comprises einsteinium or zirconium. The preparation method of claim 5, wherein the first dielectric layer comprises einsteinium, zirconium, niobium, aluminum or titanium. The preparation method as described in claim 1 further includes performing a planarization process to remove the first dielectric layer, the second dielectric layer, the third dielectric layer, and the conductive material on the substrate.