TWI895699B - Cache device and operation method thereof - Google Patents

Abstract

The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.

Description

Cache device and its operation method

The present invention relates to a memory device, and more particularly to a cache device.

Dynamic random access memory (DRAM) is a crucial memory device in computer hierarchical architecture, offering fast access speeds, random access characteristics, and high density. However, in the big data space, the bandwidth, data throughput, and latency between DRAM and processors can become bottlenecks in computing performance.

The standalone feature of DRAM components brings the advantages of high density and low cost, but the distance between DRAM components and processors also creates a performance bottleneck.

Therefore, there is a demand for fast, low-latency, and high-density memory in this technology space. However, the manufacturing process for DRAM components is incompatible with advanced logic. Furthermore, using SRAM to provide large memory capacities is also quite expensive. Embedded DRAM or the emerging L3/L4 cache have been the focus of attention in this field.

Based on the above description, according to an embodiment of the present invention, a cache device is provided, comprising a first transistor, an inverter, and a second transistor. The first transistor has a control terminal, a first terminal, and a second terminal, wherein the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node. The inverter has an input terminal and an output terminal, wherein the input terminal is coupled to the storage node. The second transistor has a control terminal, a first terminal, and a second terminal, wherein the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is used to output a read voltage.

According to another embodiment of the present invention, a method for operating a cache device is provided. The cache device includes a first transistor, an inverter, and a second transistor. The first transistor has a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a storage node. The inverter has an input terminal and an output terminal, wherein the input terminal is coupled to the storage node. The second transistor has a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the output terminal of the inverter and the second terminal is used to output a read voltage. The operating method of the cache device includes: during a write period, turning on the first transistor and turning off the second transistor so that the input voltage is stored in the storage node; during a read period, turning off the first transistor and turning on the second transistor so that the voltage at the output end of the inverter is output as the output voltage through the second end of the second transistor.

FIG1 is a schematic diagram illustrating a cache array architecture according to an embodiment of the present invention. As shown in FIG1 , cache array 10 includes a plurality of cache devices 100 arranged in an array configuration. Cache array 10 comprises a plurality of write word lines WWL0-WWLi, a plurality of write bit lines WBL0-WBLj, a plurality of read word lines RWL0-RWLi, and a plurality of read bit lines RBL0-RBLj. Here, three write and read word lines (i=3) and two write and read bit lines (j=2) are used as examples, but this is not limiting.

Furthermore, each cache device 100 is located at the intersection of each write word line WWLi and write bit line WBLj, and at the intersection of each read word line RWLi and read bit line RBLj. In other words, when writing data to each cache device 100, a write bias is applied to the corresponding write word line WWLi and write bit line WBLj, while the corresponding read word line RWLi and read bit line RBLj are deselected (disabled). Furthermore, when reading data from each cache device 100, a read bias is applied to the corresponding read word line WWLi and read bit line WBLj, while the corresponding write word line WWLi and write bit line RBLj are deselected (disabled).

According to an embodiment of the present invention, cache device 100 is constructed using transistors and does not utilize capacitors. For example, cache device 100 is configured using a 4TOC architecture. The specific architecture of cache device 100 will be further described below. In this architecture, cache device 100 is, for example, a six-terminal device, two of which are coupled to write word lines WWLi and write bit lines WBLj for write operations, two of which are coupled to read word lines RWLi and read bit lines RBLj for read operations, and two of which are coupled to voltage sources _VDD ' and _VSS ' (which, as described later, provide voltages for inverters within cache device 100).

In one embodiment, the word lines WLi (including write word lines WWLi and read word lines RWLi) and bit lines BLi (including write bit lines WBLi and read bit lines RBLj) of the cache array 10 can be arranged to be orthogonal to each other to perform array layout design.

Next, the architecture of cache device 100 is described. Figure 2 illustrates a cache device according to an embodiment of the present invention. As shown in Figure 2, cache device 100 of the present invention is composed of a first transistor M1, an inverter INV, and a second transistor M2. Cache device 100 can be composed of at least four transistors and does not require capacitors as storage units.

As shown in Figure 2, the first transistor M1 has a control end (such as the gate of the first transistor M1 shown in Figure 2), a first end and a second end (such as the source/drain end). The first end of the first transistor M1 is coupled to the input voltage. The second end of the first transistor M1 is coupled to the storage node SN. According to one embodiment of the present invention, the first transistor M1 is implemented as a low-leakage transistor. By using the low-leakage transistor M1, the retention time of the data of the storage node SN can be increased. The low-leakage transistor M1 can adopt a low-leakage CMOS transistor, a low-leakage IGZO (indium gallium zinc oxide) transistor or other equivalent transistors. The base of the low-leakage transistor M1 is coupled to the second power supply voltage V _SS '.

The inverter INV can be used as a buffer to buffer the input voltage VDD or GND of the cache device 100. The inverter INV has an input terminal IN and an output terminal OUT. The input terminal IN of the inverter INV is coupled to the storage node SN. As an example of an inverter INV, as shown in FIG2 , the inverter INV can be composed of a third transistor M3 and a fourth transistor M4 connected in series. The third transistor M3 is, for example, a PMOS transistor, whose control terminal (such as the gate of the third transistor M3 shown in FIG2 ) is coupled to the input terminal IN of the inverter INV (or the storage node SN), a first terminal is coupled to the first power supply voltage V _DD ', and a second terminal is coupled to the output terminal OUT of the inverter INV. The substrate of the third transistor M3 is coupled to the first power supply voltage V _DD '. The fourth transistor M4 is, for example, an NMOS transistor. Its control terminal (e.g., the gate of the fourth transistor M4 shown in FIG2 ) is coupled to the input terminal IN of the inverter INV (or the storage node SN). A first terminal is coupled to the output terminal OUT of the inverter INV. A second terminal is coupled to the second power supply voltage V _SS ′. The substrate of the fourth transistor M4 is coupled to the second power supply voltage V _SS ′.

Here, the first power voltage V _DD ′ is greater than the second power voltage V _SS ′. The first power voltage V _DD ′ is slightly less than the first system power voltage V _DD , while the second power voltage V _SS ′ can be substantially equal to the second system power voltage V _SS (ground).

The second transistor M2 is, for example, an NMOS transistor. The second transistor M2 has a control terminal (e.g., the gate of the second transistor M2 shown in FIG2 ), a first terminal, and a second terminal (e.g., a source/drain terminal). The first terminal of the second transistor M2 is coupled to the output terminal OUT of the inverter INV. The second terminal of the second transistor M2 is used to output a read voltage. Furthermore, the substrates of the first transistor M1 and the second transistor M2 are coupled to the second power supply voltage V _SS ′.

According to an embodiment of the present invention, the first transistor M1 serves as a write transistor. The gate of the first transistor M1 is coupled to the write word line WWL, and the first end of the first transistor M1 is coupled to the write bit line WBL to apply an input voltage. In addition, the second transistor M2 serves as a read (access) transistor. The gate of the second transistor M2 is coupled to the read word line RWL, and the second end of the second transistor M2 is coupled to the read bit line RBL, thereby outputting a read voltage. According to an embodiment of the present invention, compared to a typical SRAM cache that uses six transistors, this embodiment only requires four transistors and does not require a capacitor, thereby further reducing area cost. In addition, the cache device 100 of the present invention is a DRAM architecture such as 4TOC, so the cache device 100 can meet the requirements of CMOS logic operation and speed.

In addition, the cache device 100 of the present invention can be used to replace the L3/L4 SRAM cache memory in a processor or controller.

Next, the operation of the cache device 100 will be further described. The following description is directed to a cache device 100 in the cache array 10 shown in FIG1 .

First, the write operation of cache device 100 will be described. As shown in Figure 2, during a write operation, a deselect bias is applied to the read word line RWL and read bit line RBL of the selected cache device 100, thereby turning off the read transistor (i.e., the second transistor) M2 coupled to the read word line RWL and read bit line RBL. Furthermore, a write bias is applied to the write word line WWL and write bit line WBL of the selected cache device 100, thereby turning on the write transistor (i.e., the first transistor) M1 coupled to the write word line WWL and write bit line WBL. For example, a write voltage is applied to write word line WWL, turning on write transistor M1. System power voltage VDD or ground voltage GND (or _VSS ) is also applied to write bit line WBL. Since write transistor M1 is on, the voltage at storage node SN becomes _VDD or GND due to the system power voltage _VDD or ground voltage GND (or _VSS ) applied to write bit line WBL.

Afterwards, the write transistor M1 is turned OFF. At this time, the voltage of the storage node SN can be maintained at VDD or GND.

Next, the read operation of the cache device 100 is described. FIG3 illustrates a diagram showing the relationship between the storage voltage and the output voltage of the cache device according to an embodiment of the present invention. During the data retention time of the cache device 100, the data stored in the cache device 100 can be read. During the read operation, the read transistor M2 is turned on, such as applying a select voltage to the read word line RWL. In addition, during the read operation, the write transistor M1 is turned off. When the read transistor M2 is turned on, the voltage of the read bit line RBL can be pulled up to V _DD ' or V _SS ' (GND), depending on the voltage maintained by the storage node SN.

Referring to Figures 2 and 3 , assuming the threshold voltages of the third transistor M3 and the fourth transistor M4 are Vtp and Vtn, respectively, the third transistor M3 of the inverter INV turns on if the voltage applied to its gate (the voltage of the storage node SN) is less than VDD' + Vtp (where the threshold voltage Vtp is negative). For example, applying the second power supply voltage _VSS ' (GND) to the write bit line WBL causes the voltage of the storage node SN to become _VSS ' (GND, _VSS ), which is less than _VDD ' + Vtp. In this case, the output terminal OUT of the inverter INV becomes the first power supply voltage V _DD '. Therefore, during the read period, when the read transistor M2 is turned on, the voltage of the read bit line RBL is pulled up to the voltage V _DD '. As a result, the voltage V _DD ' can be read from the cache device 100. In other words, when the input voltage (the voltage of the storage node SN) is less than V _DD '+Vtp, the output voltage V _DD ' can be output.

Furthermore, if the voltage applied to the gate of the fourth transistor M4 of the inverter INV (the voltage of the storage node SN) is greater than Vtn, the fourth transistor M4 turns on. For example, applying the first power supply voltage _VDD ' to the write bit line WBL causes the voltage of the storage node SN to become _VDD ', which is greater than _Vtn . In this case, the output terminal OUT of the inverter INV becomes the second power supply voltage _VSS ' (GND). Therefore, during the read operation, when the read transistor M2 turns on, the voltage of the read bit line RBL is pulled down to _VSS '. Thus, the voltage V _SS ′ can be read from the cache device 100. In other words, when the input voltage (the voltage of the storage node SN) is greater than Vtn, the voltage V _SS ′ can be output.

Furthermore, when the input voltage (the voltage of storage node SN) is between _VDD '+Vtp and Vtn, the output of cache device 100 is in a floating state. Furthermore, the first power supply voltage _VDD ' applied to the third transistor M3 of inverter INV must be less than |Vtp|+Vtn to close the current path from the first power supply voltage _VDD ' through transistors M3 and M4 to the second power supply voltage _VSS '. Furthermore, the first power supply voltage _VDD ' can be less than the first system power supply voltage VDD to ensure that the relationship _VDD '< |Vtp|+Vtn holds. In addition, the voltage of the storage node SN may be greater than the first power voltage V _DD ′, such as the first system power voltage V _DD , to obtain a longer retention time.

FIG4 illustrates a schematic diagram of storage node voltage versus time for a cache device according to an embodiment of the present invention. As shown in FIG4 , the vertical axis represents the voltage of storage node SN, and the horizontal axis represents time. t0 represents the time when data writing to cache device 100 is completed, and te represents the time when the retention period for stored data in cache device 100 expires.

The voltage held at storage node SN is initially at the first system power voltage V _DD . That is, during the write phase of cache device 100, the first system power voltage V _DD is applied to write bit line WBL. At time t0, after data writing is complete, the voltage V _DD held at storage node SN begins to discharge from V _DD to V _SS '. During the discharge phase, when the voltage at storage node SN reaches the threshold voltage Vtn, the fourth transistor M4 of inverter INV is turned off, and the output voltage becomes V _SS ' (GND). When the voltage of the storage node SN is less than the critical voltage Vtn, the cache device 100 will fail to retain data and the output voltage will become floating.

Furthermore, when the voltage held at storage node SN is initially at the second system power supply voltage V _SS '(GND), the voltage at storage node SN remains at GND, and the third transistor M3 of inverter INV is turned on, while the fourth transistor M4 is turned off. At this point, the output voltage becomes V _DD '.

FIG5 is a schematic diagram of the layout of a cache device according to an embodiment of the present invention. FIG5 is a schematic diagram of a layout using a fin field-effect transistor (FinFET). FIG5(a) illustrates three transistors M2, M3, and M4 (refer to FIG2) of a unit memory cell 20 of a cache memory (i.e., corresponding to the cache device 100 of FIG2). In addition, FIG5(b) illustrates that the low leakage transistor M1 of the cache device 100 can use an IGZO transistor (i.e., transistor M1) in the back end of line (BEOL) process. The IGZO transistor can be connected to the storage node SN through another via structure. In this example, the layout area of the cache device 100 of the present invention only requires three transistors, and the other one is completed in the BEOL process. Therefore, compared with a 6T SRAM cache memory, the area size of the unit memory cell 20 can be further reduced.

FIG6 shows a schematic diagram of the layout of a cache device according to another embodiment of the present invention. The layout architecture shown in FIG6 is an architecture using planar transistors. Under this architecture, all four transistors (M1 to M4) of the cache device 100 can be formed on a single plane. In addition, three transistors (M2 to M4) can also be formed on a plane, and another low-leakage current transistor M1 (such as an IGZO transistor) can be completed using a BEOL process. In this case, the floating layer is 20% smaller than the SRAM memory. Therefore, compared with a 6T SRAM cache memory, the area size of the unit memory cell 22 can be further reduced.

Based on the above description, the cache device according to the embodiment of the present invention utilizes a DRAM architecture similar to four transistors and no capacitors (4TOC). This cache device is compatible with DRAM process, logic operations, and speed requirements. Furthermore, the cache device can reduce layout area, thereby increasing memory capacity and reducing costs.

10: Cache array 20, 22: Unit memory cell 20 100: Cache device M1: First transistor M2: Second transistor M3: Third transistor M4: Fourth transistor INV: Inverter WWL: Write word line WBL: Write bit line RWL: Read word line RBL: Read bit line SN: Storage node IN: Input OUT: Output _VDD ': First power supply voltage _VSS ': Second power supply voltage _VDD : First system power supply voltage GND: Ground

Figure 1 is a schematic diagram illustrating a cache array architecture according to an embodiment of the present invention. Figure 2 is a schematic diagram illustrating a cache device according to an embodiment of the present invention. Figure 3 illustrates a diagram illustrating the relationship between storage voltage and output voltage of a cache device according to an embodiment of the present invention. Figure 4 is a schematic diagram illustrating the relationship between storage node voltage and time of a cache device according to an embodiment of the present invention. Figure 5 is a schematic diagram illustrating the layout of a cache device according to an embodiment of the present invention. Figure 6 is a schematic diagram illustrating the layout of a cache device according to another embodiment of the present invention.

100: Cache device

M1: First transistor

M2: Second transistor

M3: The third transistor

M4: Fourth transistor

INV: Inverter

WWL: Write Word Line

WBL: Write Bit Line

RWL: Read word line

RBL: Read Bit Line

SN: Storage Node

IN: Input terminal

OUT: Output port

V _DD ': first power supply voltage

V _SS ': Second power supply voltage

Claims (12)

A cache device includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the first transistor is coupled to an input voltage and the second terminal of the first transistor is coupled to a storage node, wherein the first transistor is a low leakage current transistor; an inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the second transistor is coupled to the output terminal of the inverter and the second terminal of the second transistor is used to output a read voltage, wherein the inverter includes: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the output terminal of the inverter. The first terminal of the third transistor is coupled to the input terminal of the inverter, the first terminal of the third transistor is coupled to a first power supply voltage, and the second terminal of the third transistor is coupled to the output terminal of the inverter; a fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to the input terminal of the inverter, the first terminal of the fourth transistor is coupled to the output terminal of the inverter, and the second terminal of the fourth transistor is coupled to a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage, wherein the first power supply voltage is less than the sum of the absolute value of the critical voltage of the third transistor and the critical voltage of the fourth transistor, and wherein the input voltage is greater than the first power supply voltage. A cache device as described in claim 1, wherein the first transistor serves as a write transistor, the control end of the first transistor is coupled to a write word line, and the first end of the first transistor is coupled to a write bit line to apply the input voltage; 　　The second transistor serves as a read transistor, the control end of the second transistor is coupled to a read word line, and the second end of the second transistor is coupled to a read bit line to output the read voltage. The cache device of claim 1, wherein the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor. The cache device of claim 1, wherein the second transistor is an NMOS transistor. The cache device of claim 1, wherein the low leakage current transistor is a low leakage current CMOS transistor. The cache device of claim 1, wherein the low leakage current transistor is a low leakage current IGZO transistor. A method for operating a cache device, the cache device comprising: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to an input voltage and the second terminal is coupled to a storage node, wherein the first transistor is a low leakage current transistor; an inverter having an input terminal and an output terminal, wherein the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal is coupled to the output terminal of the inverter. The output terminal of the inverter is configured to output a read voltage, wherein the operation method includes: during a write period, turning on the first transistor and turning off the second transistor, so that the input voltage is stored in the storage node; and during a read period, turning off the first transistor and turning on the second transistor, outputting the voltage of the output terminal of the inverter as the output voltage via the second terminal of the second transistor, wherein the inverter includes: a third transistor , having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is coupled to the input terminal of the inverter, the first terminal of the third transistor is coupled to the first power voltage, and the second terminal of the third transistor is coupled to the output terminal of the inverter; a fourth transistor, having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor is coupled to the input terminal of the inverter, the first terminal of the fourth transistor is coupled to the first power voltage, and the second terminal of the third transistor is coupled to the output terminal of the inverter. The first terminal of the fourth transistor is coupled to the output terminal of the inverter, the second terminal of the fourth transistor is coupled to a second power supply voltage, wherein the first power supply voltage is greater than the second power supply voltage, wherein in the inverter, the first power supply voltage is applied to the first terminal of the third transistor, wherein the first power supply voltage is less than the sum of the absolute value of the critical voltage of the third transistor and the critical voltage of the fourth transistor, and wherein the input voltage is greater than the first power supply voltage. The operating method of the cache device as described in claim 7, wherein the first transistor serves as a write transistor, the control terminal of the first transistor is coupled to a write word line, the first terminal of the first transistor is coupled to a write bit line, during the write period, a bias is applied to the control terminal of the first transistor to turn on the first transistor, and the input voltage is applied through the write bit line, the second transistor serves as a read transistor, the control terminal of the second transistor is coupled to a read word line, the second terminal of the second transistor is coupled to a read bit line, during the read period, a bias is applied to the control terminal of the second transistor to turn on the second transistor, and the read voltage is output through the read bit line. The operating method of the cache device as described in claim 7, wherein the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor. The operating method of the cache device as described in claim 7, wherein the second transistor is an NMOS transistor. The operating method of the cache device as described in claim 7, wherein the low leakage current transistor is a low leakage current CMOS transistor. The operating method of the cache device as described in claim 7, wherein the low leakage current transistor is a low leakage current IGZO transistor.