TWI891432B - Power converting circuit and control method thereof - Google Patents

Abstract

A power convertor includes a resonant capacitor, a transformer, a high-side transistor, a low-side transistor, a control circuit, and a rectifying circuit. The resonant capacitor is coupled between a resonant node and a ground. The transformer includes a primary winding coupled between a switch node and the resonant node and a secondary winding. The high-side transistor provides an input voltage to the switch node and the low-side transistor couples the switch node to the ground. The control circuit drives the high-side transistor and the low-side transistor based on a feedback voltage, and operates in either one of a flyback mode and a non-flyback mode based on the output voltage. When the output voltage is less than an output threshold, the control circuit operates in the flyback mode and the rectifying circuit half-wave rectifies the energy of the secondary winding to generate the output voltage.

Description

Power conversion circuit and control method thereof

The present invention relates to a power conversion circuit and a control method thereof, and more particularly to a power conversion circuit and a control method thereof that can automatically switch between a flyback mode and a resonance mode.

With the continuous growth of portable electronic devices, power conversion circuits, like most power products, are trending towards high efficiency, high power density, high reliability, and low cost. Resonant power conversion circuits (including LLC resonant power conversion circuits) have seen increasing adoption in DC converters in recent years due to their advantages, such as achieving zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) in the secondary-side rectifier diodes across the full load range. Frequency control allows for a duty cycle of nearly 50% for both the high-side and low-side transistors, eliminating the need for an output inductor and enabling the use of lower-voltage transistors on the secondary side, reducing cost and improving efficiency.

However, due to the circuit characteristics of resonant power converters, a higher switching frequency is required when the output voltage is low or the load is light, resulting in poor conversion efficiency. To meet the current market demand for a wide output voltage range, high output power, and high conversion efficiency, further optimization of the power converter circuit is necessary to meet market demands.

This invention proposes a power conversion circuit capable of operating in either flyback mode or resonance mode, and a control method thereof. By automatically switching the power conversion circuit between flyback mode and resonance mode, the circuit provides a wide output voltage range and high output power, while also improving conversion efficiency under light loads and low output voltages.

In view of this, the present invention provides a power conversion circuit comprising a resonant capacitor, a transformer, a high-bridge transistor, a low-bridge transistor, a control circuit, a feedback circuit, and a rectifier circuit. The resonant capacitor is coupled between a resonant node and a ground terminal. The transformer comprises a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and the resonant node. The high-bridge transistor provides an input voltage to the switching node based on an high-bridge drive signal. The low-bridge transistor couples the switching node to the ground terminal based on a low-bridge drive signal. The control circuit generates the upper bridge drive signal and the lower bridge drive signal based on a feedback voltage and operates in either a flyback mode or a non-flyback mode based on an output voltage. The feedback circuit generates the feedback voltage based on the output voltage. The rectifier circuit generates the output voltage by full-wave or half-wave rectifying the energy in the secondary coil based on the output voltage. When the output voltage is less than an output threshold, the control circuit operates in the flyback mode, and the rectifier circuit generates the output voltage by half-wave rectifying the energy in the secondary coil.

According to one embodiment of the present invention, the control circuit switches from the flyback mode to the non-flyback mode or from the non-flyback mode to the flyback mode based on the signal edge of the lower bridge drive signal.

According to one embodiment of the present invention, the secondary coil includes a first secondary coil and a second secondary coil. When the output voltage is not less than the output threshold value, the control circuit operates in the non-flyback mode, and the rectifier circuit full-wave rectifies the energy in the first secondary coil and the second secondary coil to generate the output voltage.

According to one embodiment of the present invention, the secondary coil includes a first secondary coil and a second secondary coil, wherein the first secondary coil includes a first terminal and a second terminal, and the second secondary coil includes a third terminal and a fourth terminal, wherein the first terminal and the fourth terminal are both coupled to the output voltage. The rectifier circuit includes a first rectifier transistor, a second rectifier transistor, and a third rectifier transistor. The first rectifier transistor couples the second terminal to the ground terminal based on a first rectifier signal. The second rectifier transistor couples the third terminal to a rectifier node based on a second rectifier signal. The third rectifier transistor couples the rectifier node to the ground terminal based on a third rectifier signal. When the output voltage is less than the output threshold, the third rectifier transistor is non-conductive, causing the rectifier circuit to half-wave rectify the energy of the second secondary coil to generate the output voltage. The third rectified signal is synchronized with the first rectified signal.

According to one embodiment of the present invention, the rectifier circuit further includes a secondary control circuit. The secondary control circuit includes a synchronous rectifier controller, a first voltage divider circuit, a first comparator, a first inverter, a first flip-flop, and a second inverter. The synchronous rectifier controller generates the first rectified signal based on the voltage at the second terminal and generates the second rectified signal based on the voltage at the third terminal. The first voltage divider circuit divides the output voltage to generate a first divided voltage. The first comparator compares the first divided voltage with a low voltage threshold to generate a rectified comparison signal. The first inverter inverts the first rectified signal to generate a first inverted rectified signal. The first flip-flop outputs the rectified comparison signal as a fourth rectified signal based on the signal edge of the first inverted rectified signal. The second inverter inverts the fourth rectified signal to generate the third rectified signal. The first divided voltage is the output voltage multiplied by a first ratio, and the low voltage threshold is the output threshold multiplied by a second ratio. The first ratio is equal to the second ratio.

According to one embodiment of the present invention, the transformer further includes an auxiliary coil. The auxiliary coil is coupled between an auxiliary node and the ground terminal. The power conversion circuit further includes a second voltage divider circuit for dividing the voltage at the auxiliary node to generate a reflected voltage, wherein the reflected voltage is related to the output voltage. The control circuit further operates in one of the flyback mode and the non-flyback mode based on the reflected voltage.

According to one embodiment of the present invention, the control circuit further includes a mode determination circuit. The mode determination circuit comprises a first pulse generator, a determination AND gate, a sampling switch, a first determination inverter, a second pulse generator, a holding switch, a determination comparator, and a determination flip-flop. The first pulse generator generates a pulse signal based on the lower bridge drive signal. The determination AND gate performs a logical operation on the lower bridge drive signal and the pulse signal to generate a sampling signal. The sampling switch samples the reflected voltage based on the sampling signal and stores the sampled reflected voltage in a sampling capacitor as a sampled voltage. The first determination inverter inverts the sampling signal to generate an inverted sampling signal. The second pulse generator generates a holding signal based on the inverted sampling signal. The holding switch samples the sampled voltage based on the holding signal and stores the sampled sampled voltage in a holding capacitor as a holding voltage. The determination comparator compares the holding voltage with a low voltage threshold value to generate a determination signal. The judgment flip-flop latches the judgment signal into a mode signal based on the inversion of a pull-up dead-band timing signal. When the holding voltage is less than the low-voltage threshold, the judgment signal and the mode signal are in a disabled state. When the holding voltage is not less than the low-voltage threshold, the judgment signal and the mode signal are in an enabled state. The low-voltage threshold is the output threshold multiplied by a ratio.

According to one embodiment of the present invention, the power conversion circuit further includes a first current detection circuit, an integrator, and a full-wave rectifier. The first current detection circuit generates a current detection signal based on the voltage at the resonant node. The integrator generates an integrated signal based on the current detection signal. The full-wave rectifier full-wave rectifies the integrated signal generated by the integrator to generate a rectified signal. The control circuit further generates the upper bridge drive signal and the lower bridge drive signal based on the rectified signal.

According to one embodiment of the present invention, the first current detection circuit includes a first capacitor and a first resistor. The first capacitor is coupled between the resonant node and a first detection node. The first resistor is coupled between the first detection node and the ground terminal. The first current detection circuit generates the current detection signal at the first detection node.

According to one embodiment of the present invention, the integrator includes an integrating amplifier, a second capacitor, a second resistor, a third resistor, and a third capacitor. The integrating amplifier includes an integrating positive input terminal, an integrating negative input terminal, and an integrating output terminal, wherein the integrating positive input terminal receives a reference voltage, and the integrating output terminal generates the integrating signal. The second capacitor is coupled between the first detection node and a second detection node. The second resistor is coupled between the second detection node and the integrating negative input terminal. The third resistor is coupled between the integrating negative input terminal and the integrating output terminal. The third capacitor is coupled between the integrating negative input terminal and the integrating output terminal.

According to one embodiment of the present invention, the full-wave rectifier generates the rectified signal by full-wave rectifying the integrated signal using a base voltage as a DC level. The base voltage is equal to the sum of the reference voltage and an offset voltage. The full-wave rectifier further compares the rectified signal with a first threshold voltage to generate a crossover signal. The first threshold voltage is slightly greater than the base voltage.

According to one embodiment of the present invention, the offset voltage is determined based on the difference between the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal. The offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal is close to the enable period of the lower bridge drive signal.

The control circuit of the resonant power conversion circuit includes a digital circuit, a first amplifier, a second amplifier, a second resistor, an N-type transistor, a current mirror, and a summing circuit. The digital circuit gradually increases a soft-start voltage to the feedback voltage over a predetermined time period. The first amplifier includes a first positive input, a first negative input, and a first output. The first positive input receives the soft-start voltage, and the first negative input is coupled to the first output. The second amplifier includes a second positive input, a second negative input, and a second output. The second positive input receives a feedback threshold voltage, and the second output generates a compensation voltage. The second resistor is coupled between the second negative input terminal and the first output terminal and generates a differential current. The N-type transistor includes a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to the second output terminal, and the source terminal is coupled to the second negative input terminal. The current mirror maps the differential current into at least one mapped current. The summing circuit subtracts a sawtooth wave from the compensation voltage to generate a compensation signal. When the soft-start voltage is less than the feedback threshold voltage, the compensation voltage is equal to the feedback threshold voltage. When the soft-start voltage is not less than the feedback threshold voltage, the compensation voltage is equal to the soft-start voltage.

According to one embodiment of the present invention, when the rectified signal is less than the first critical voltage, the full-wave rectifier sets the cross signal to the disabled state. When the rectified signal exceeds the first critical voltage, the full-wave rectifier sets the cross signal to the enabled state. In response to the cross signal changing from the disabled state to the enabled state or the mode signal being the disabled state, the control circuit sets a phase signal to the enabled state. The control circuit sets the phase signal to the disabled state based on either the upper bridge dead band time signal and the lower bridge dead band time signal or the mode signal being the enabled state. The upper bridge dead band time signal controls an upper bridge dead band time of the upper bridge drive signal. The above-mentioned lower bridge dead band time signal controls the lower bridge dead band time of one of the above-mentioned lower bridge drive signals.

According to one embodiment of the present invention, when the high-bridge drive signal turns on the high-bridge transistor, the phase signal is in the enabled state, and the mode signal is in the enabled state, the control circuit disables the high-bridge drive signal in response to the rectified signal exceeding the compensation signal. When the high-bridge drive signal turns on the high-bridge transistor, the phase signal is in the enabled state, and the mode signal is in the disabled state, the control circuit disables the high-bridge drive signal in response to the voltage at the second detection node exceeding the compensation signal. When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge drive signal after the lower bridge dead band time to turn on the lower bridge transistor. When the lower bridge drive signal turns on the lower bridge transistor, the phase signal is in the enabled state, and the mode signal is in the enabled state, the control circuit disables the lower bridge drive signal in response to the rectified signal exceeding the compensation signal. When the lower bridge drive signal turns on the lower bridge transistor, the phase signal is in the enabled state, and the mode signal is in the disabled state, the control circuit disables the lower bridge drive signal in response to the voltage of the second detection node exceeding the compensation signal. When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal after the upper bridge dead time to turn on the upper bridge transistor.

According to one embodiment of the present invention, the control circuit further limits the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal to no more than a maximum enable cycle. The maximum enable cycle varies based on the mode signal.

According to one embodiment of the present invention, the feedback voltage decreases in response to an increase in the output voltage. In response to the feedback voltage falling below a low-power threshold voltage, the lower-side dead-band timing signal enables a burst signal, causing the control circuit to operate in a burst mode based on the enabled burst signal. When the control circuit operates in the burst mode, both the upper-side transistor and the lower-side transistor are non-conductive. The duration of the burst mode increases as the output power of the output voltage decreases.

According to one embodiment of the present invention, the power conversion circuit further includes a second current detection circuit. The second current detection circuit generates an overcurrent signal and a zero-current signal based on the current detection signal. When the current flowing through the resonant capacitor exceeds a preset value, the overcurrent signal is in a reset state, and the control circuit disables the upper bridge drive signal and the lower bridge drive signal based on the overcurrent signal in the reset state. When the current flowing through the resonant capacitor is approximately zero, the zero-current signal is in the enable state, causing the control circuit to enable the lower bridge drive signal based on the zero-current signal in the enable state.

According to one embodiment of the present invention, the control circuit further operates in the burst mode based on the burst signal being in the enabled state and the zero-current signal being in the enabled state. The burst mode begins when the upper bridge drive signal is in the disabled state and ends when the lower bridge drive signal is in the enabled state.

According to one embodiment of the present invention, the second current detection circuit includes a first comparison circuit and a second comparison circuit. The first comparison circuit compares the voltage at the second detection node with an upper threshold voltage and a lower threshold voltage to generate the overcurrent signal. The second comparison circuit compares the voltage at the second detection node with a zero current threshold voltage to generate the zero current signal. When the voltage at the second detection node is greater than the upper threshold voltage or less than the lower threshold voltage, the first comparison circuit resets the overcurrent signal. When the voltage of the second detection node exceeds the zero-current threshold voltage, the second comparison circuit sets the zero-current signal to the enabled state. The zero-current threshold voltage is slightly greater than zero.

The present invention further provides a control method for controlling a power conversion circuit. The power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, a high-bridge transistor that provides an input voltage to a switching node, a low-bridge transistor that couples the switching node to the ground terminal, a rectifier circuit that converts energy flowing through the secondary coil into an output voltage, and a feedback circuit that generates a feedback voltage based on the output voltage. The primary coil is coupled between the switching node and the resonant node. The control method includes: driving the upper bridge transistor and the lower bridge transistor based on the feedback voltage, the output voltage, and the current flowing through the resonant capacitor; determining whether the output voltage is less than an output threshold; when the output voltage is determined to be less than the output threshold, utilizing the rectifier circuit to half-wave rectify the energy of the secondary coil to generate the output voltage; and when the output voltage is determined to be not less than the output threshold, utilizing the rectifier circuit to full-wave rectify the energy of the secondary coil to generate the output voltage.

According to one embodiment of the present invention, the secondary coil includes a first secondary coil and a second secondary coil. When the output voltage is less than the output threshold value, the rectifier circuit converts energy from one of the first secondary coil and the second secondary coil into the output voltage. When the output voltage is not less than the output threshold value, the rectifier circuit converts energy from the first secondary coil and the second secondary coil into the output voltage.

According to one embodiment of the present invention, the transformer further includes an auxiliary coil coupled between an auxiliary node and the ground terminal. The control method further includes: utilizing a voltage divider circuit to divide the voltage at the auxiliary node to generate a reflected voltage; determining whether the reflected voltage is less than a low-voltage threshold; operating the power conversion circuit in a flyback mode when the reflected voltage is determined to be less than the low-voltage threshold; and operating the power conversion circuit in a non-flyback mode when the reflected voltage is determined to be not less than the low-voltage threshold. When the lower bridge transistor is turned on, the power conversion circuit switches from the flyback mode to the non-flyback mode or vice versa. The reflected voltage is related to the output voltage.

According to one embodiment of the present invention, the step of determining whether the reflected voltage is less than the low voltage threshold value further includes: sampling the reflected voltage and storing it as a sampled voltage based on the conduction of the lower bridge transistor; sampling the sampled voltage and storing it as a holding voltage based on the non-conduction of the lower bridge transistor; comparing the holding voltage with the low voltage threshold value using a comparator to generate a determination signal, wherein when the holding voltage is not less than the low voltage threshold value, the upper circuit breaker generates a detection signal. The determination signal is in an enabled state, wherein when the holding voltage is less than the low voltage threshold, the determination signal is in a disabled state; based on a dead-band time of a high-side transistor, the determination signal is latched into a mode signal; when the mode signal is in the enabled state, the power conversion circuit is operated in the non-flyback mode; and when the mode signal is in the disabled state, the power conversion circuit is operated in the flyback mode.

According to one embodiment of the present invention, the control method further includes: detecting current flowing through the resonant capacitor using a first current detection circuit to generate a current detection signal; integrating the current detection signal based on a reference voltage to generate an integrated signal; full-wave rectifying the integrated signal to generate a rectified signal; and driving the high-bridge transistor and the low-bridge transistor based on the rectified signal. The first current detection circuit includes a first capacitor and a first resistor. The first capacitor is coupled between the resonant node and a first detection node, and the first resistor is coupled between the first detection node and the ground terminal. The current detection signal is generated at the first detection node. A second capacitor is coupled between the first detection node and a second detection node.

According to one embodiment of the present invention, the control method further includes: performing full-wave rectification on the integrated signal using a base voltage as a DC level to generate the rectified signal; and comparing the rectified signal with a first threshold voltage to generate a crossover signal. The base voltage is equal to the sum of the reference voltage and an offset voltage, and the first threshold voltage is slightly greater than the base voltage.

According to one embodiment of the present invention, the control method further includes: gradually increasing a soft-start voltage to the feedback voltage over a predetermined period of time; converting the soft-start voltage into a compensation voltage; and subtracting a sawtooth wave from the compensation voltage to generate a compensation signal. When the soft-start voltage is less than a feedback threshold voltage, the compensation voltage is equal to the feedback threshold voltage. When the soft-start voltage is not less than the feedback threshold voltage, the compensation voltage is equal to the soft-start voltage.

According to one embodiment of the present invention, the control method further includes: setting the cross signal to a disabled state when the rectified signal is less than the first threshold voltage; setting the cross signal to an enabled state when the rectified signal exceeds the first threshold voltage; setting a phase signal to the enabled state in response to the cross signal changing from the disabled state to the enabled state; and setting the phase signal to the disabled state during an upper bridge dead band time or a lower bridge dead band time in response to the rectified signal exceeding the compensation signal. The lower bridge dead band time is the time between the time when the upper bridge transistor turns off and the time when the lower bridge transistor turns on. The upper bridge dead time is the time from when the lower bridge transistor turns off to when the upper bridge transistor turns on.

According to one embodiment of the present invention, the control method further includes: when the upper bridge transistor is turned on, the phase signal is in the enabled state, and the power conversion circuit operates in the non-flyback mode, the upper bridge transistor is turned off in response to the rectifier signal exceeding the compensation signal; when the upper bridge transistor is turned on, the phase signal is in the enabled state, and the power conversion circuit operates in the flyback mode, the upper bridge transistor is turned off in response to the voltage of the second detection node exceeding the compensation signal; when the upper bridge transistor is not turned on, after the lower bridge dead time The lower bridge transistor is turned on; when the lower bridge transistor is turned on, the phase signal is in the enabled state, and the power conversion circuit operates in the non-flyback mode, the lower bridge transistor is turned off in response to the rectified signal exceeding the compensation signal; when the lower bridge transistor is turned on, the phase signal is in the enabled state, and the power conversion circuit operates in the flyback mode, the lower bridge transistor is turned off in response to the voltage of the second detection node exceeding the compensation signal; and when the lower bridge transistor is not turned on, the upper bridge transistor is turned on after the upper bridge dead band time.

According to one embodiment of the present invention, the control method further includes: in response to the feedback voltage being lower than a low-power threshold voltage, operating the power conversion circuit in a burst mode, wherein the feedback voltage decreases in response to an increase in the output voltage; in the burst mode, simultaneously turning off the high-side transistor and the low-side transistor; and increasing a duration of the burst mode in response to a decrease in output power of the output voltage.

According to one embodiment of the present invention, the control method further includes: when the current flowing through the resonant capacitor exceeds a preset value, simultaneously turning off the upper and lower bridge transistors; and when the current flowing through the resonant capacitor is approximately zero, turning on the lower bridge transistor. The burst mode begins when the upper bridge transistor turns off and ends when the lower bridge transistor turns on.

100: Power conversion circuit

111: Upper bridge transistor

112: Lower bridge transistor

121: First current detection circuit

122: First voltage divider circuit

130: Integrator

131: Integral Amplifier

140,200: Full-wave rectifier

150,1300: Second current detection circuit

160,600: Control circuit

170: Level shift circuit

180: Rectifier circuit

181,1500: Secondary control circuit

190: Feedback circuit

TM: Transformer

LR: Resonant Inductor

CR: Resonance Capacitor

HSD: High-side drive circuit

LSD: Lower Drive Circuit

PS: Beginner coil

SS: Secondary coil

AS: Auxiliary coil

NS1: First secondary coil

NS2: Secondary coil

NR: Resonance Node

NA: auxiliary node

RD1: First voltage divider resistor

RD2: Second voltage divider resistor

N1: First endpoint

N2: Second endpoint

N3: Third endpoint

N4: Fourth endpoint

NRC: Rectifier Node

SW: switch node

HSG: High-side gate drive signal

LSG: Lower Gate Drive Signal

VIN: Input voltage

C1: First capacitor

C2: Second capacitor

R1: First resistor

R2: Second resistor

R3: The third resistor

R5: The fifth resistor

R6: Sixth resistor

R7: Seventh resistor

R8: Eighth resistor

FW: Rectified signal

FB: Feedback voltage

SZ: Cross signal

COUT: output capacitance

HS: Upper bridge drive signal

LS: Lower bridge drive signal

MR1: First rectifier transistor

MR2: Second rectifier transistor

MR3: Third rectifier transistor

VW1: First coil voltage

VW2: Second coil voltage

VOUT: output voltage

VD1: First divided voltage

PD: Photocoupler

LED: diode

Q: Transistor

VCC: supply voltage

VCS: Current detection voltage

CS: Current detection signal

INT: Integral signal

OCP: Overcurrent signal

ZCD: Zero Current Signal

ND1: First detection node

ND2: Second detection node

VREF: Reference voltage

SR1: First rectified signal

SR2: Second rectified signal

SR3: Third rectified signal

210: Full-wave rectifier

220: Bias circuit

221: Automatic adjustment circuit

CMP1: First comparator

R9: Ninth resistor

R10: Tenth resistor

R11: Eleventh resistor

R12: 12th resistor

R13: Thirteenth resistor

AMP1: First amplifier

AMP2: Second amplifier

D3: The third diode

D4: Fourth Diode

VT1: First threshold voltage

AMP3: Third amplifier

CS1: First current source

R14: Fourteenth resistor

I1: First current

VBS: Base voltage

CK_H: Bridge dead time signal

CK_L: Downbridge dead zone time signal

ID: Adjust current

VOS: offset voltage

DC: Direct current level

400: Compensation circuit

410: Digital Circuits

411: First counter

412: First Digital-to-Analog Converter

420: Summing circuit

SFT: Soft Start Voltage

AMP4: Fourth amplifier

AMP5: Fifth amplifier

R15: Fifteenth resistor

MN1: First N-type transistor

CM1: First Current Mirror

VTC: Feedback Threshold Voltage

INP4: Fourth positive input terminal

INN4: Fourth negative input terminal

O4: Fourth output port

INP5: Fifth positive input terminal

INN5: Fifth negative input terminal

O5: Fifth output port

IDIFF: differential current

IB1: First mapped current

IB2: Second mapped current

IB3: Third mapped current

G: Gate terminal

D: Drain terminal

S: Source

VCOMP: Compensation voltage

COMP: Compensation signal

RAMP: Sawtooth Wave

500: Mode determination circuit

510: First pulse generator

520: Judgment and Gate

SWS: Sampling Switch

CSMP: sampling capacitor

530: First judgment inverter

540: Second pulse generator

SWH: Hold Switch

CHLD: Holding Capacitor

550: Comparator

560: Second judgment inverter

570: Determine the flip-flop

IMP: Pulse signal

SMP: sampling signal

VSMP: sampling voltage

HLD: Holding signal

VHLD: Holding Voltage

VT_MD: Low voltage threshold

SD: Judgment signal

CK_HB: Inverted upper bridge dead time signal

MOD: Mode signal

MODB: Inverted mode signal

FF1: First Flip-Flop

AND1: First AND gate

ORE: Phase or Gate

SEP: Pre-phase signal

SE: Phase signal

CMP2: Second comparator

SWM1: First mode switch

SWM2: Second mode switch

OR1: First OR gate

OR2: Second OR gate

DT1: First dead time generator

DT2: Second dead time generator

FF2: Second flip-flop

FF3: Third Flip-Flop

ANDE: Mode and Gate

AND2: Second AND gate

AND3: Third AND gate

AND4: Fourth and Gate

AND5: Fifth and Gate

AND6: Sixth and Gate

AND7: Seventh and Gate

AND8: The Eighth and Gate

dHS: Delayed bridge drive signal

IHS: Initial Hit-Speed Drive Signal

dLS: Delayed lower bridge drive signal

ILS: Initial Lower Link Drive Signal

IX: First current adjustment

IY: Second adjustment current

INV1: First inverter

INV2: Second inverter

601: First cycle limit circuit

602: Second cycle limit circuit

700: Waveform

T1: First time

T2: Second Time

T3: The third time

T4: The Fourth Time

800: Delay time generator

INV3: Third inverter

MN2: Second N-type transistor

C3: The third capacitor

CS2: Second current source

CS3: Third current source

CM2: Second current mirror

CMP3: Third comparator

IN: Input signal

VCAP1: First capacitor voltage

I2: Second current

I3: Third current

I4: Fourth current

I5: Fifth current

I6: Sixth current

I7: Seventh Current

VT2: Second threshold voltage

OUT: output signal

IA: Input current

900: Time-to-voltage conversion circuit

CS4: Fourth current source

OR3: Third OR Gate

SW1: First switch

SW2: Second switch

SW3: Third switch

SW4: Fourth switch

NAND1: First NAND Gate

C4: Fourth capacitor

C5: Fifth capacitor

C6: Sixth capacitor

VDH: Upper bridge enable cycle voltage

VDL: Lower bridge enable cycle voltage

1000: Automatically adjust the circuit

1010: Comparison Circuits

1020: Signal generation circuit

1030: Second counter

1040: Second digital-to-analog converter

FF4: Fourth Flip-Flop

FF5: Fifth Flip-Flop

UP: Upward signal

DWN: Downward signal

LTH: latch signal

CLK: clock signal

B:Digital code

CMP4: Fourth comparator

CMP5: Fifth Comparator

INV4: Fourth inverter

INV5: Fifth inverter

INV6: Sixth inverter

AND9: Ninth and Gate

AND10: The Tenth Gate

AND11: The Eleventh and Gate

AND12: The Twelfth Gate

LUP: Latch Up Digital Signal

LDWN: latch down signal

CS5: Fifth Current Source

C7: Seventh capacitor

VCAP2: Second capacitor voltage

MN3: Third N-type transistor

1100: Output voltage detection circuit

1110: Delay circuit

CMP6: Sixth Comparator

FF6: The Sixth Flip-Flop

FF7: The Seventh Flip-Flop

INV7: Seventh Inverter

INV8: Eighth Inverter

INV9: Ninth Inverter

VTLP: Threshold Voltage for Low Power

CP: Comparative Signal

PSR: Pre-Surprise Signal

PSB: Phase-inverted pre-burst signal

BST: Burst Signal

ST: Reset signal

MN4: Fourth N-type transistor

CS6: Sixth current source

C8: Eighth capacitor

I8: Eighth current

NOR1: First NOR gate

OR4: Fourth OR Gate

AND13: The Thirteenth Gate

VCAP3: Third capacitor voltage

S1: First signal

S1B: The First Anti-Belief Signal

S2: Second signal

1310: First comparison circuit

1311: Delay circuit

1320: Second comparison circuit

CS7: Seventh Current Source

I9: Ninth Current

VTH: upper threshold voltage

VTL: Lower Threshold Voltage

VTZ: Zero current threshold voltage

CMP7: Seventh Comparator

CMP8: Eighth Comparator

CMP9: Comparator No. 9

OR5: Fifth Or Gate

C9: Ninth capacitor

MN5: Fifth N-type transistor

NOR2: Second NOR gate

VCAP4: Fourth capacitor voltage

CRE: Comparison Results

1510: Synchronous Rectification Controller

1520: Second voltage divider circuit

CMP10: Tenth Comparator

INV10: Tenth Inverter

FF8: The Eighth Flip-Flop

INV11: Eleventh Inverter

VD2: Second divided voltage

CMPR: Rectified comparison signal

SR1B: First inverted rectified signal

SR4: Fourth rectified signal

1600: Control Method

S1610~S1640: Step Flow

FIG1 is a block diagram of a power conversion circuit according to an embodiment of the present invention; FIG2 is a block diagram of a full-wave rectifier according to an embodiment of the present invention; FIG3 is a waveform diagram of a rectified signal and an integrated signal according to an embodiment of the present invention; FIG4 is a block diagram of a compensation circuit according to an embodiment of the present invention; FIG5 is a block diagram of a compensation circuit according to an embodiment of the present invention; FIG6 is a block diagram of a mode determination circuit according to an embodiment of the present invention; FIG7 is a waveform diagram of the control circuit according to an embodiment of the present invention operating in a non-flyback mode; FIG8 is a circuit diagram of a delay time generator according to an embodiment of the present invention; FIG9 is a circuit diagram of a control circuit according to an embodiment of the present invention. FIG10 is a schematic diagram of an automatic adjustment circuit according to an embodiment of the present invention; FIG11 is a block diagram of an output voltage detection circuit according to an embodiment of the present invention; FIG12 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG13 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG14 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG15 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG16 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG17 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG18 is a waveform diagram of a resonant power conversion circuit according to an embodiment of the present invention operating at a light load; FIG19 ... FIG14 is a block diagram of a second current detection circuit according to an embodiment of the present invention; FIG15 is a block diagram of a secondary control circuit according to an embodiment of the present invention; and FIG16 is a flow chart of a control method for controlling a power conversion circuit according to an embodiment of the present invention.

The following descriptions are examples of embodiments of the present disclosure. They are provided for illustrative purposes only. This disclosure generally describes the principles of the present disclosure and should not be construed as limiting the scope of the present disclosure. The scope of the present disclosure shall be determined by the scope of the patent applications.

It is important to note that the following disclosure provides multiple embodiments or examples for implementing various features of the present disclosure. The specific component examples and arrangements described below are intended only to briefly illustrate the spirit of the present disclosure and are not intended to limit the scope of the present disclosure. Furthermore, the following description may reuse the same component symbols or text in multiple examples. However, this reuse is intended solely to simplify and clarify the description and is not intended to limit the relationship between the various embodiments and/or configurations discussed below.

Furthermore, descriptions in the following description of a feature being connected to, coupled to, and/or formed on another feature may actually include a variety of different embodiments, including those features being directly in contact, or including additional features formed between those features, so that the features are not in direct contact.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It will be understood that if the device in the drawings is turned upside down, the element described as being on the "lower" side would become the element on the "upper" side.

It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts should not be limited by these terms, and these terms are merely used to distinguish one element, component, region, layer, and/or part from another. Thus, a first element, component, region, layer, and/or part discussed below could be referred to as a second element, component, region, layer, and/or part without departing from the teachings of some embodiments of this disclosure.

Some embodiments of this disclosure can be understood in conjunction with the accompanying drawings, which are considered part of the description of the disclosed embodiments. It should be understood that the drawings of the disclosed embodiments are not drawn to scale relative to actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly illustrate the features of the disclosed embodiments. Furthermore, the structures and devices in the drawings are schematically depicted to clearly illustrate the features of the disclosed embodiments.

Herein, the terms "about," "approximately," and "substantially" generally mean within 20%, preferably within 10%, and more preferably within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The quantities given herein are approximate quantities, meaning that even without the specific wording "about," "approximately," or "substantially," the meaning of "about," "approximately," or "substantially" is implied.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, unless otherwise specified, may refer to two structures being in direct contact, or to two structures not being in direct contact, with another structure positioned between them. Furthermore, these terms may include situations where both structures are movable or both structures are fixed.

In the drawings, similar components and/or features may have the same reference numerals. Components of the same type may be distinguished by adding a letter or number after the reference numeral to distinguish similar components and/or similar features.

FIG1 is a block diagram of a power conversion circuit according to one embodiment of the present invention. As shown in FIG1 , the power conversion circuit 100 includes a transformer TM, a resonant inductor LR, a resonant capacitor CR, a high-side transistor 111, a low-side transistor 112, a first current detection circuit 121, a first voltage divider circuit 122, an integrator 130, a full-wave rectifier 140, a second current detection circuit 150, a control circuit 160, a level shifter circuit 170, a high-side driver circuit HSD, a low-side driver circuit LSD, a rectifier circuit 180, and a feedback circuit 190.

The transformer TM includes a primary coil PS and a secondary coil SS, wherein the primary coil PS is coupled to a resonance node NR. A resonant inductor LR is coupled between a switching node SW and the primary coil PS, and a resonant capacitor CR is coupled between the resonant node NR and ground. According to one embodiment of the present invention, the resonant inductor LR can be replaced by the leakage inductance of the primary coil PS of the transformer TM. In other words, the primary coil PS can be coupled between the switching node SW and the resonance node NR.

As shown in Figure 1, the secondary winding SS further includes a first secondary winding NS1 and a second secondary winding NS2. The first secondary winding NS1 includes a first terminal N1 and a second terminal N2, while the second secondary winding NS2 includes a third terminal N3 and a fourth terminal N4. Both the first terminal N1 and the fourth terminal N4 are coupled to the output voltage VOUT. The transformer TM further includes an auxiliary winding AS, which is coupled between an auxiliary node NA and ground.

The high-gate drive signal HSG turns high-bridge transistor 111 on and off, providing the input voltage VIN to the switching node SW. The low-gate drive signal LSG turns low-bridge transistor 112 on and off, coupling the switching node SW to ground. The first current detection circuit 121 includes a first capacitor C1 and a first resistor R1. The first capacitor C1 is coupled between the resonance node NR and the first detection node ND1, and the first resistor R1 is coupled between the first detection node ND1 and ground.

According to one embodiment of the present invention, the first current detection circuit 121 generates a current detection signal CS at the first detection node ND1. The first voltage divider circuit 122 includes a first voltage divider resistor RD1 and a second voltage divider resistor RD2, which divide the voltage at the auxiliary node NA to generate a reflected voltage RFV. According to one embodiment of the present invention, the reflected voltage RFV is related to the output voltage VOUT.

Integrator 130 is used to integrate the current detection signal CS from the first detection node ND1 to generate an integrated signal INT. As shown in Figure 1, integrator 130 includes a second capacitor C2, a second resistor R2, an integrator amplifier 131, a third resistor R3, and a third capacitor C3. The second capacitor C2 is coupled between the first detection node ND1 and the second detection node ND2, and the second resistor R2 is coupled between the second detection node ND2 and the negative input terminal of integrator amplifier 131. The positive input terminal of integrator amplifier 131 receives a reference voltage VREF, and the third resistor R3 and third capacitor C3 are connected in parallel between the output terminal and the negative input terminal of integrator amplifier 131.

The full-wave rectifier 140 full-wave rectifies the integrated signal INT to generate a rectified signal FW and a crossover signal SZ. The second current detection circuit 150 is coupled to the second detection node ND2 and generates an overcurrent signal OCP and a zero-current signal ZCD based on the current detection voltage VCS at the second detection node ND2. In other words, the second current detection circuit 150 generates the overcurrent signal OCP and the zero-current signal ZCD based on the current detection voltage VCS at the second detection node ND2.

The control circuit 160 generates a high-side drive signal HS and a low-side drive signal LS based on the rectified signal FW, the feedback voltage FB, the overcurrent signal OCP, the zero-current signal ZCD, the current detection voltage VCS, and the reflected voltage RFV. The level shift circuit 170 converts the high-side drive signal HS to the voltage level of the input voltage VIN and generates a high-side gate drive signal HSG via the high-side drive circuit HSD to drive the high-side transistor 111. The low-side drive circuit LSD generates a low-side drive signal LSG based on the low-side drive signal LS to drive the low-side transistor 112.

According to one embodiment of the present invention, when the reflected voltage RFV is less than the low voltage threshold VT_MD, indicating that the output voltage VOUT is less than the output threshold, the control circuit 160 operates in flyback mode, and the power conversion circuit 100 is a flyback power conversion circuit. When the power conversion circuit 100 is a flyback power conversion circuit, the conduction time of the high-side transistor 111 of the power conversion circuit 100 adjusts the voltage level of the output voltage VOUT.

According to another embodiment of the present invention, when the reflected voltage RFV is not less than the low voltage threshold VT_MD, indicating that the output voltage VOUT is not less than the output threshold, the control circuit 160 operates in non-flyback mode, and the power conversion circuit 100 is a resonant power conversion circuit. When the power conversion circuit 100 operates in non-flyback mode, the power conversion circuit 100 adjusts the voltage level of the output voltage VOUT by adjusting the switching frequency of the high-side transistor 111 and the low-side transistor 112.

Rectifier circuit 180 is coupled to secondary winding SS and is used to generate output voltage VOUT by full-wave or half-wave rectifying the energy in secondary winding SS based on output voltage VOUT. As shown in Figure 1, rectifier circuit 180 includes a first rectifier transistor MR1, a second rectifier transistor MR2, a third rectifier transistor MR3, an output capacitor COUT, and a secondary control circuit 181. First rectifier transistor MR1 couples second terminal N2 to ground based on a first rectifier signal SR1. Second rectifier transistor MR2 couples third terminal N3 to a rectifier node NRC based on a second rectifier signal SR2. Third rectifier transistor MR3 couples rectifier node NRC to ground based on a third rectifier signal SR3.

The secondary control circuit 181 determines whether the output voltage VOUT is less than the output threshold value. Based on the first coil voltage VW1 at the third terminal N3 and the second coil voltage VW2 at the second terminal N2, the secondary control circuit 181 generates a first rectified signal SR1, a second rectified signal SR2, and a third rectified signal SR3. This rectified signal then performs full-wave or half-wave rectification on the energy in the first secondary coil NS1 and the second secondary coil NS2 to generate the output voltage VOUT across the output capacitor COUT. According to one embodiment of the present invention, when the output voltage VOUT is not less than the output threshold value, the secondary control circuit 181 turns off the third rectifier transistor MR3 and performs half-wave rectification on the energy in the second secondary coil NS2 to generate the output voltage VOUT. According to another embodiment of the present invention, when the output voltage is less than the output threshold, the secondary control circuit 181 turns on the third rectifier transistor MR3 to full-wave rectify the energy of the first secondary coil NS1 and the second secondary coil NS2, thereby generating the output voltage VOUT.

Feedback circuit 190 generates a feedback voltage FB based on the output voltage VOUT. As shown in Figure 1, feedback circuit 190 includes a fifth resistor R5, a sixth resistor R6, a voltage regulator DR, an optocoupler PD, a seventh resistor R7, and an eighth resistor R8. The fifth resistor R5 and the sixth resistor R6 divide the output voltage VOUT to generate a first divided voltage VD1. Based on the first divided voltage VD1, the voltage regulator DR generates a current flowing through the diode LED of the optocoupler PD, causing the diode LED to emit light, thereby turning on the transistor Q of the optocoupler PD through optical coupling.

The seventh resistor R7 is used to limit the current flowing through the diode LED. The supply voltage VCC generates the feedback voltage FB through the eighth resistor R8 and the conductive transistor Q. According to one embodiment of the present invention, the voltage regulator element DR can be a TL431. According to some embodiments of the present invention, as the output voltage VOUT increases, the feedback voltage FB decreases accordingly. According to other embodiments of the present invention, as the output voltage VOUT decreases, the feedback voltage FB increases accordingly. The control method of the power conversion circuit 100 will be described in detail below.

FIG2 is a block diagram of a full-wave rectifier according to one embodiment of the present invention. According to one embodiment of the present invention, the full-wave rectifier 200 of FIG2 corresponds to the full-wave rectifier 140 of FIG1 . As shown in FIG2 , the full-wave rectifier 200 includes a full-wave rectifier 210 , a first comparator CMP1 , and a bias circuit 220 . The full-wave rectifier 210 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first amplifier AMP1, a twelfth resistor R12, a thirteenth resistor R13, a third diode D3, a fourth diode D4, and a second amplifier AMP2. The full-wave rectifier 210 uses the base voltage VBS as the DC level to perform full-wave rectification on the integrated signal INT generated by the integrator 130 to generate a rectified signal FW.

The first comparator CMP1 compares the rectified signal FW with a first threshold voltage VT1 to generate a cross signal SZ. According to one embodiment of the present invention, the first threshold voltage VT1 is slightly greater than the base voltage VBS. According to one embodiment of the present invention, when the rectified signal FW is less than the first threshold voltage VT1, the first comparator CMP1 disables the cross signal SZ. According to another embodiment of the present invention, when the rectified signal FW exceeds the first threshold voltage VT1, the first comparator CMP1 enables the cross signal SZ.

The bias circuit 220 includes a third amplifier AMP3, a first current source CS1, a fourteenth resistor R14, and an automatic adjustment circuit 221. As shown in Figure 2, the positive input of the third amplifier AMP3 receives a reference voltage VREF, and the third amplifier AMP3 is coupled as a unity-gain buffer, ensuring that the voltage at the output of the third amplifier AMP3 is equal to the reference voltage VREF. The first current source CS1 provides a first current I1 to flow to the base voltage VBS, and the fourteenth resistor R14 is coupled between the base voltage VBS and the output of the third amplifier AMP3.

The automatic adjustment circuit 221 extracts an adjustment current ID from the base voltage VBS based on the upper bridge drive signal HS, the lower bridge drive signal LS, the upper bridge dead-band timing signal CK_H, and the lower bridge dead-band timing signal CK_L. The automatic adjustment circuit 221, the upper bridge dead-band timing signal CK_H, and the lower bridge dead-band timing signal CK_L are described in detail below. According to one embodiment of the present invention, the base voltage VBS is equal to the sum of the reference voltage VREF and the offset voltage VOS.

According to one embodiment of the present invention, when the first current I1 is greater than the adjusted current ID, the offset voltage VOS is positive, and the base voltage VBS is greater than the reference voltage VREF. According to another embodiment of the present invention, when the first current I1 is less than the adjusted current ID, the offset voltage VOS is negative, and the base voltage VBS is less than the reference voltage VREF. According to another embodiment of the present invention, when the first current I1 is equal to the adjusted current ID, the base voltage VBS is equal to the reference voltage VREF. According to another embodiment of the present invention, when the first current I1 is equal to the adjusted current ID, the offset voltage VOS is zero, and the base voltage VBS is equal to the reference voltage VREF.

Figure 3 shows waveforms of the rectified signal and the integrated signal according to one embodiment of the present invention. As shown in Figure 3, the divided signal SD has a DC level DC. The full-wave rectifier 210 uses the base voltage VBS as the DC level to full-wave rectify the integrated signal INT, generating a rectified signal FW. Next, the first comparator CMP1 compares the rectified signal FW with the first threshold voltage VT1 to generate a crossover signal SZ. As shown in Figure 3, when the rectified signal FW is less than the first threshold voltage VT1, the first comparator CMP1 disables the crossover signal SZ. When the rectified signal FW is not less than the first threshold voltage VT1, the crossover signal SZ remains enabled.

FIG4 is a block diagram of a compensation circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the control circuit 160 of FIG1 includes a compensation circuit 400. As shown in FIG4 , the compensation circuit 400 includes a digital circuit 410, a fourth amplifier AMP4, a fifth amplifier AMP5, a fifteenth resistor R15, a first N-type transistor MN1, a first current mirror CM1, and a summing circuit 420.

The compensation circuit 400 generates a compensation voltage VCOMP based on the feedback voltage FB and limits the compensation voltage VCOMP to no less than the feedback threshold voltage VTC. In other words, the compensation voltage VCOMP generated by the compensation circuit 400 is equal to the feedback voltage FB, and the minimum value of the compensation voltage VCOMP is limited to the feedback threshold voltage VTC. Furthermore, the compensation circuit 400 subtracts the sawtooth wave RAMP from the compensation voltage VCOMP to generate the compensation signal COMP.

When the power conversion circuit 100 is initially started, the digital circuit 410 is used to gradually increase the soft-start voltage SFT to the feedback voltage FB over a predetermined period of time. As shown in Figure 4 , the digital circuit 410 includes a first counter 411 and a first digital-to-analog converter 412. The first counter 411 counts from 0 to a maximum value based on the clock signal CLK. The first digital-to-analog converter 412 generates the soft-start voltage SFT based on the count value of the first counter 411 and the feedback voltage FB.

For example, the first counter 411 counts from 0 to 1024 according to the clock signal CLK, and the maximum value of the feedback voltage FB is 5V. Therefore, with each cycle of the clock signal CLK, the soft-start voltage SFT increases by approximately 5mV until it equals the feedback voltage FB. As the soft-start voltage SFT slowly climbs to the correct voltage value of the feedback voltage FB, the power conversion circuit 100 in Figure 1 gradually builds up the output voltage VOUT.

The fourth amplifier AMP4 includes a fourth positive input terminal INP4, a fourth negative input terminal INN4, and a fourth output terminal O4. The fourth positive input terminal INP4 receives a soft-start voltage SFT, and the fourth negative input terminal INN4 is coupled to the fourth output terminal O4. The fifth amplifier AMP5 includes a fifth positive input terminal INP5, a fifth negative input terminal INN5, and a fifth output terminal O5. The fifth positive input terminal INP5 receives a feedback threshold voltage VTC. According to one embodiment of the present invention, the fourth amplifier AMP4 is coupled as a unity-gain amplifier, so the voltage at the fourth output terminal O4 is equal to the soft-start voltage SFT.

The fifteenth resistor R15 is coupled between the fifth negative input terminal INN5 and the fourth output terminal O4 and generates a differential current IDIFF. The first N-type transistor MN1 includes a gate terminal G, a drain terminal D, and a source terminal S. The gate terminal G is coupled to the fifth output terminal O5, and the source terminal S is coupled to the fifth negative input terminal INN5 and generates a compensation voltage VCOMP. The summing circuit 420 is used to subtract the sawtooth wave RAMP from the compensation voltage VCOMP to generate a compensation signal COMP.

The first current mirror CM1 is coupled to the drain terminal D and maps the differential current IDIFF into a first mapped current IB1, a second mapped current IB2, and a third mapped current IB3. According to some embodiments of the present invention, the first mapped current IB1, the second mapped current IB2, and the third mapped current IB3 are respectively N, M, and P times the differential current IDIFF, where N, M, and P are the magnifications of the mapping by the first current mirror CM1, and N, M, and P can be the same or different.

According to one embodiment of the present invention, when the soft-start voltage SFT is less than the feedback threshold voltage VTC, the difference between the feedback threshold voltage VTC and the soft-start voltage SFT and the resistance value of the fifteenth resistor R15 generate a differential current IDIFF. The first current mirror CM1 generates a first mirror current IB1, a second mirror current IB2, and a third mirror current IB3. The compensation voltage VCOMP is equal to the feedback threshold voltage VTC. According to another embodiment of the present invention, when the soft-start voltage SFT is greater than or equal to the feedback threshold voltage VTC, the fifth amplifier AMP5 turns off the first N-type transistor MN1, so that the first current mirror CM1 does not generate the first mirror current IB1, the second mirror current IB2, and the third mirror current IB3, and the compensation voltage VCOMP equals the soft-start voltage SFT.

In other words, when the soft-start voltage SFT is less than the feedback threshold voltage VTC, the compensation voltage VCOMP is equal to the feedback threshold voltage VTC, and accordingly, the first mirrored current IB1, the second mirrored current IB2, and the third mirrored current IB3 are generated. When the soft-start voltage SFT is not less than the feedback threshold voltage VTC, the compensation voltage VCOMP is equal to the soft-start voltage SFT, and the first mirrored current IB1, the second mirrored current IB2, and the third mirrored current IB3 are not generated. The functions of the first mirrored current IB1, the second mirrored current IB2, and the third mirrored current IB3 will be explained in detail below.

FIG5 is a block diagram of a mode determination circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the control circuit 160 of FIG1 includes a mode determination circuit 500. As shown in FIG5 , the mode determination circuit 500 includes a first pulse generator 510, a determination gate 520, a sampling switch SWS, a sampling capacitor CSMP, a first determination inverter 530, a second pulse generator 540, a holding switch SWH, a holding capacitor CHLD, a determination comparator 550, a second determination inverter 560, and a determination flip-flop 570.

When the low-side drive signal LS transitions from a low logic level to a high logic level, the first pulse generator 510 generates a pulse signal IMP. The decision gate 520 performs logic operations on the low-side drive signal LS and the pulse signal IMP to enable the sampling signal SMP, thereby turning on the sampling switch SWS. When the sampling switch SWS is turned on, it samples the reflected voltage RFV and stores it in the sampling capacitor CSMP as the sample voltage VSMP.

The sampled signal SMP is fed through the first determination inverter 530 and the second pulse generator 540 to generate the hold signal HLD, which in turn turns on the hold switch SWH. When the hold switch SWH is on, it stores the sampled voltage VSMP in the hold capacitor CHLD, resulting in the hold voltage VHLD. The determination comparator 550 compares the hold voltage VHLD with the low-voltage threshold VT_MD to generate the determination signal SD.

The second decision inverter 560 inverts the upper bridge dead-band timing signal CK_H to generate the inverted upper bridge dead-band timing signal CK_HB. Based on the positive signal edge of the inverted upper bridge dead-band timing signal CK_HB, the decision flip-flop 570 latches the decision signal SD into the mode signal MOD and generates the inverted mode signal MODB, where the inverted mode signal MODB is the inverse of the mode signal MOD. In other words, based on the negative signal edge of the upper bridge dead-band timing signal CK_HB, the decision flip-flop 570 latches the decision signal SD into the mode signal MOD.

According to one embodiment of the present invention, when the reflected voltage RFV (i.e., the holding voltage VHLD) is less than the low-voltage threshold value VT_MD, the mode signal MOD is disabled, and the control circuit 160 operates in the flyback mode. According to another embodiment of the present invention, when the reflected voltage RFV (i.e., the holding voltage VHLD) is not less than the low-voltage threshold value VT_MD, the mode signal MOD is enabled, and the control circuit 160 operates in the non-flyback mode.

FIG6 is a block diagram of a control circuit according to one embodiment of the present invention. As shown in FIG6 , the control circuit 600 includes a first flip-flop FF1, a first AND gate AND1, and a phase OR gate ORE. The first flip-flop FF1 outputs the supply voltage VCC as the pre-phase signal SEP (i.e., sets the pre-phase signal SEP to the enabled state) based on a positive signal edge of the cross signal SZ (i.e., when the cross signal SZ changes from a disabled state to an enabled state). According to some embodiments of the present invention, the cross signal SZ is disabled at a low logic level and enabled at a high logic level. In other words, as shown in FIG2 , when the rectified signal FW increases and exceeds the first threshold voltage VT1, the pre-phase signal SEP is enabled.

The first flip-flop FF1 further disables the pre-phase signal SEP based on the disabled state (i.e., low logical level) of the upper bridge dead-band timing signal CK_H or the lower bridge dead-band timing signal CK_L. In other words, the pre-phase signal SEP is disabled during the upper bridge dead-band timing and the lower bridge dead-band timing. The phase OR gate ORE performs a logical OR operation on the pre-phase signal SEP and the inverted mode signal MODB to generate the phase signal SE. In other words, when the pre-phase signal SEP is enabled or the mode signal MOD is disabled (i.e., the control circuit 600 operates in flyback mode), the phase signal SE is enabled.

As shown in Figure 6 , the control circuit 600 further includes a first mode switch SWM1, a second mode switch SWM2, a second comparator CMP2, a second AND gate AND2, a first OR gate OR1, a first dead-time generator DT1, a second flip-flop FF2, and a third AND gate AND3. When the mode signal MOD is enabled (i.e., the control circuit 600 operates in non-flyback mode), the first mode switch SWM1 provides the rectified signal FW to the comparison voltage VCMP. When the inverted mode signal MODB is enabled (i.e., the control circuit 600 operates in flyback mode), the second mode switch SWM2 provides the current detection voltage VCS to the comparison voltage VCMP.

When the comparison voltage VCMP exceeds the compensation signal COMP generated by the compensation circuit 400, the delayed high-bridge drive signal dHS is enabled, and the phase signal SE is enabled, the second AND gate AND2 and the first OR gate OR1 trigger the first dead-time generator DT1 to generate a negative pulse on the low-bridge dead-time signal CK_L. The third AND gate AND3 disables the high-bridge drive signal HS, thereby turning off the high-bridge transistor 111 in Figure 1.

Furthermore, the negative pulse of the lower bridge dead-band timing signal CK_L resets the second flip-flop FF2, disabling the delayed upper bridge drive signal dHS. According to one embodiment of the present invention, the width of the negative pulse of the lower bridge dead-band timing signal CK_L is used to determine the lower bridge dead-band time of the lower bridge transistor 112. According to one embodiment of the present invention, the first adjustment current IX is used to adjust the length of the lower bridge dead-band time.

As shown in FIG6 , the control circuit 600 further includes a first inverter INV1, a fourth AND gate AND4, a third flip-flop FF3, a mode AND gate ANDE, a fifth AND gate AND5, a second OR gate OR2, a second dead-time generator DT2, and a sixth AND gate AND6. The first inverter INV1 inverts the disabled delayed high-bridge drive signal dHS and enables the initial high-bridge drive signal IHS. When the lower bridge dead-band timing signal CK_L changes from a disabled state (negative pulse) to an enabled state and the burst signal BST is in a disabled state (a high logic level in the embodiment of FIG. 6 ), the third flip-flop FF3 outputs the enabled initial upper bridge drive signal IHS as a delayed lower bridge drive signal dLS (i.e., in an enabled state).

Next, when the delayed lower bridge drive signal dLS is enabled, the comparison voltage VCMP exceeds the compensation signal COMP, the phase signal SE is enabled, and the mode signal MOD is enabled (i.e., the control circuit 600 operates in the non-flyback mode), the second dead-time generator DT2 is enabled via the mode AND gate ANDE, the fifth AND gate AND5, and the second OR gate OR2 to generate a negative pulse in the upper bridge dead-time signal CK_H, and the lower bridge drive signal LS is set to a disabled state via the sixth AND gate AND6, thereby turning off the lower bridge transistor 112 in FIG. 1. Furthermore, the negative pulse of the upper bridge dead-band timing signal CK_H resets the third flip-flop FF3, disabling the delayed lower bridge drive signal dLS. According to one embodiment of the present invention, the width of the negative pulse of the upper bridge dead-band timing signal CK_H is used to determine the upper bridge dead-band time of the upper bridge transistor 111. According to one embodiment of the present invention, the second adjustment current IY is used to adjust the length of the upper bridge dead-band time.

As shown in FIG6 , the control circuit 600 further includes a first cycle limit circuit 601, a second cycle limit circuit 602, and a second inverter INV2. When the enable cycle of the upper bridge drive signal HS exceeds the maximum enable cycle, the first cycle limit circuit 601, based on the first mirrored current IB1 generated by the compensation circuit 400 in FIG4 , issues an enable signal to trigger the first dead-time generator DT1 to generate a negative pulse, thereby resetting (or disabling) the delayed upper bridge drive signal dHS, thereby disabling the upper bridge drive signal HS. According to one embodiment of the present invention, during the enable cycle of the upper bridge drive signal HS, the upper bridge transistor 111 is turned on; during the enable cycle of the lower bridge drive signal LS, the lower bridge transistor 112 is turned on.

When the enable cycle of the lower bridge drive signal LS exceeds the maximum enable cycle, the second cycle limit circuit 602, based on the second mirrored current IB2 generated by the compensation circuit 400, issues an enable signal to trigger the second dead-time generator DT2 to generate a negative pulse, resetting or disabling the delayed lower bridge drive signal dLS, thereby disabling the lower bridge drive signal LS. The second inverter INV2 is used to invert the delayed lower bridge drive signal dLS to generate the initial lower bridge drive signal ILS.

When the delayed lower bridge drive signal dLS is enabled, the comparison voltage VCMP exceeds the compensation signal COMP, the phase signal SE is enabled, and the mode signal MOD is disabled (i.e., the control circuit 600 operates in flyback mode), the output signal of the mode gate ANDE is disabled, causing the output signal of the fifth gate AND5 to also be disabled. Therefore, based on the enable signal from the second cycle limit circuit 602, the second OR gate OR2 enables the second dead-time generator DT2 to generate a negative pulse in the upper bridge dead-time signal CK_H. This disables the lower bridge drive signal LS via the sixth gate AND6, thereby preventing the lower bridge transistor 112 in FIG. 1 from conducting.

In other words, when the control circuit 600 operates in flyback mode (i.e., the mode signal MOD is disabled), the conduction time of the low-bridge transistor 112 is equal to the maximum enable cycle set by the second cycle limit circuit 602. According to some embodiments of the present invention, the maximum enable cycles set by the first cycle limit circuit 601 and the second cycle limit circuit 602 can be changed based on the mode signal MOD.

As shown in Figure 6 , the control circuit 600 further includes a seventh AND gate AND7 and an eighth AND gate AND8. The seventh AND gate AND7 is used to perform logical operations on the lower-side dead-band timing signal CK_L and the overcurrent signal OCP to reset the second flip-flop FF2. Specifically, when the lower-side dead-band timing signal CK_L is at a low logic level (i.e., a negative pulse) or the overcurrent signal OCP is at a low logic level (i.e., a negative pulse), the delayed upper-side drive signal dHS is reset to a disabled state.

The eighth AND gate AND8 performs a logical operation on the upper bridge dead-band timing signal CK_H and the overcurrent signal OCP to reset the third flip-flop FF3. Specifically, when the upper bridge dead-band timing signal CK_H is in a negative pulse state or the overcurrent signal OCP is in a negative pulse state, the delayed lower bridge drive signal dLS is reset to a disabled state.

Figure 7 shows waveforms of a control circuit according to an embodiment of the present invention operating in non-flyback mode. The following detailed explanation combines control circuit 600 in Figure 6 and waveform diagram 700 in Figure 7. For simplicity, the explanation is based on non-flyback mode. The waveforms of the control circuit operating in flyback mode can also be derived by modifying the description of control circuit 600 in Figure 6 and waveform diagram 700 in Figure 7.

At the first time T1 in Figure 7, the lower-side drive signal LS is enabled and the rectifier signal FW continues to increase, just exceeding the compensation signal COMP. As shown in Figure 6, because the rectifier signal FW exceeds the compensation signal COMP, the output of the second comparator CMP2 triggers the second dead-time generator DT2 to generate a negative pulse in the upper-side dead-time signal CK_H via the fifth AND gate AND5 and the second OR gate OR2. This negative pulse of the upper-side dead-time signal CK_H resets the first flip-flop FF1, disabling the phase signal SE. Furthermore, the negative pulse of the upper-side dead-time signal CK_H simultaneously passes through the sixth AND gate AND6, disabling the lower-side drive signal LS.

According to one embodiment of the present invention, when the upper bridge dead-band timing signal CK_H is disabled, that is, between the first time T1 and the second time T2, the third flip-flop FF3 is reset, disabling the delayed lower bridge drive signal dLS. Furthermore, the disabled delayed lower bridge drive signal dLS stops the second dead-band generator DT2 via the fifth AND gate AND5 and the second OR gate OR2, further disabling the upper bridge dead-band timing signal CK_H, thus ending the upper bridge dead-band timing and reaching the second time T2.

At the second time T2 in Figure 7, the upper bridge dead-band timing signal CK_H pulses back to the enabled state from the negative pulse. That is, the upper bridge dead-band timing signal CK_H generates a positive signal edge at the second time T2, causing the second flip-flop FF2 to output the initially enabled lower bridge drive signal ILS as the delayed upper bridge drive signal dHS, and to enable the upper bridge drive signal HS through the third AND gate AND3.

At the third time T3 in Figure 7, the upper-side drive signal HS remains enabled, and the rectifier signal FW continues to increase, just exceeding the compensation signal COMP. As shown in Figure 5, as the rectifier signal FW increases and exceeds the compensation signal COMP, the output of the second comparator CMP2 triggers the first dead-time generator DT1 to generate a negative pulse in the lower-side dead-time signal CK_L via the second AND gate AND2 and the first OR gate OR1. This negative pulse of the lower-side dead-time signal CK_L resets the first flip-flop FF1, disabling the phase signal SE. In addition, the negative pulse of the lower-bridge dead-band time signal CK_L simultaneously passes through the third AND gate AND3, disabling the upper-bridge drive signal HS.

According to one embodiment of the present invention, when the lower-bridge dead-band timing signal CK_L is disabled, the second flip-flop FF2 is reset, disabling the delayed upper-bridge driving signal dHS. The disabled delayed upper-bridge driving signal dHS stops the first dead-band timing generator DT1 from continuing to disable the lower-bridge dead-band timing signal CK_L via the second AND gate AND2 and the first OR gate OR1, thereby enabling the lower-bridge dead-band timing signal CK_L.

At the fourth time T4 in Figure 7, the lower bridge dead-band timing signal CK_L pulses back from a negative state to an enabled state. That is, the lower bridge dead-band timing signal CK_L generates a positive edge at the fourth time T4. Combined with the fact that the burst signal BST is in a disabled state (i.e., a high logic level), the third flip-flop FF3 outputs the enabled initial upper bridge drive signal IHS as a delayed lower bridge drive signal dLS, and sets the lower bridge drive signal LS to an enabled state through the sixth AND gate AND6.

FIG8 is a circuit diagram of a delay time generator according to one embodiment of the present invention. According to one embodiment of the present invention, the delay time generator 800 in FIG8 corresponds to the first dead time generator DT1 and the second dead time generator DT2 in FIG6.

As shown in FIG8 , the delay time generator 800 includes a third inverter INV3, a second N-type transistor MN2, a third capacitor C3, a second current source CS2, a second current mirror CM2, a third current source CS3, and a third comparator CMP3.

When the third inverter INV3 receives a disabled input signal IN, the second N-type transistor MN2 is conductive and couples the first capacitor voltage VCAP1 generated by the third capacitor C3 to ground. When the third inverter INV3 then receives an enabled input signal IN, the second N-type transistor MN2 is non-conductive, and the second current mirror CM2 mirrors the second current I2 generated by the second current source CS2 into a fourth current I4. Adding the third current I3 generated by the third current source CS3 connected in parallel to the second current mirror CM2, the third capacitor C3 is charged by the fifth current I5, generating the first capacitor voltage VCAP1. According to one embodiment of the present invention, the fifth current I5 is the sum of the third current I3 and the fourth current I4.

When the first capacitor voltage VCAP1 exceeds the second threshold voltage VT2, the third comparator CMP3 generates a disabled output signal OUT. When the input signal IN returns to the disabled state, the second N-type transistor MN2 turns on, discharging the first capacitor voltage VCAP1 to ground, causing the output signal OUT generated by the third comparator CMP3 to return to the enabled state. According to one embodiment of the present invention, the fifth current I5 is determined by the capacitance of the third capacitor C3 to determine the charging time.

According to one embodiment of the present invention, when additional input current IA is supplied to second current source CS2, the magnitude of fourth current I4 is reduced, thereby reducing fifth current I5 charging third capacitor C3, thereby extending the duration that output signal OUT remains in the disabled state. In other words, by increasing the magnitude of input current IA, the duration of the negative pulse of output signal OUT can be adjusted. According to some embodiments of the present invention, input current IA in FIG8 corresponds to first adjusted current IX and second adjusted current IY in FIG6.

FIG9 is a schematic diagram of a time-to-voltage conversion circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the automatic adjustment circuit 221 of FIG2 includes a time-to-voltage conversion circuit 900. As shown in FIG9 , the time-to-voltage conversion circuit 900 includes a fourth current source CS4, a third OR gate OR3, a first switch SW1, a first NAND gate NAND1, a second switch SW2, a fourth capacitor C4, a third switch SW3, a fifth capacitor C5, a fourth switch SW4, and a sixth capacitor C6.

The fourth current source CS4 generates a fourth current I4. The third OR gate OR3 performs a logical OR operation on the upper bridge drive signal HS and the lower bridge drive signal LS, turning on the first switch SW1. This causes the sixth current I6 to charge the fourth capacitor C4. The first NAND gate NAND1 performs a logical NAND operation on the upper bridge dead-band timing signal CK_H and the lower bridge dead-band timing signal CK_L, turning on the second switch SW2, causing the fourth capacitor C4 to discharge to ground.

The high-bridge drive signal HS controls the third switch SW3, allowing the sixth current I6 to charge the fifth capacitor C5 and generate the high-bridge enable cycle voltage VDH. The low-bridge drive signal LS controls the fourth switch SW4, allowing the sixth current I6 to charge the sixth capacitor C6 and generate the low-bridge enable cycle voltage VDL.

In other words, when the high-bridge drive signal HS is enabled, the sixth current I6 charges the fourth capacitor C4 and the fifth capacitor C5. When the low-bridge drive signal LS is enabled, the sixth current I6 charges the fourth capacitor C4 and the sixth capacitor C6. During the high-bridge dead time and the low-bridge dead time, the fourth capacitor C4 is discharged, clearing the charge stored in the fourth capacitor C4. Therefore, the high-bridge enable cycle voltage VDH represents the enable cycle of the high-bridge drive signal HS, and the low-bridge enable cycle voltage VDL represents the enable cycle of the low-bridge drive signal LS.

FIG10 is a schematic diagram of an automatic adjustment circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the automatic adjustment circuit 1000 corresponds to the automatic adjustment circuit 221 of FIG2.

As shown in Figure 10 , the automatic adjustment circuit 1000 includes a comparison circuit 1010, a signal generation circuit 1020, a fourth flip-flop FF4, a fifth flip-flop FF5, a second counter 1030, and a second digital-to-analog converter 1040. The comparison circuit 1010 is used to compare the upper bridge enable cycle voltage VDH with the lower bridge enable cycle voltage VDL to generate an up signal UP and a down signal DWN.

Signal generation circuit 1020 generates a clock signal CLK and a latch signal LTH based on the upper dead-band timing signal CK_H and the lower dead-band timing signal CK_L. A fourth flip-flop FF4 generates a latched up count signal LUP based on the latch signal LTH and the latched up count signal UP. A fifth flip-flop FF5 generates a latched down count signal LDWN based on the latch signal LTH and the latched down count signal DWN. A second counter 1030 counts digital code B based on the clock signal CLK. When the latched up count signal LUP is enabled and the latched down count signal LDWN is disabled, second counter 1030 counts digital code B. When the latch-up signal LUP is in a disabled state and the latch-down signal LDWN is in an enabled state, the second counter 1030 counts digital code B.

As shown in FIG. 10 , comparator circuit 1010 includes a fourth comparator CMP4, a fifth comparator CMP5, a fourth inverter INV4, a fifth inverter INV5, a ninth AND gate AND9, and a tenth AND gate AND10. When the upper bridge enable period voltage VDH exceeds the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is enabled and the output of the fifth comparator CMP5 is disabled. When the upper bridge enable period voltage VDH does not exceed the lower bridge enable period voltage VDL, the output of the fourth comparator CMP4 is disabled and the output of the fifth comparator CMP5 is enabled. Next, the up signal UP and the down signal DWN are generated through the fourth inverter INV4, the fifth inverter INV5, the ninth AND gate AND9, and the tenth AND gate AND10.

In other words, when the upper bridge enable cycle voltage VDH exceeds the lower bridge enable cycle voltage VDL, the up-count signal UP is enabled and the down-count signal DWN is disabled. When the upper bridge enable cycle voltage VDH does not exceed the lower bridge enable cycle voltage VDL, the up-count signal UP is disabled and the down-count signal DWN is enabled. In other words, when the enable cycle of the upper bridge drive signal HS exceeds the enable cycle of the lower bridge drive signal LS, the second counter 1030 counts up the digital code B, causing the second digital-to-analog converter 1040 to increase the adjustment current ID. When the enable period of the upper bridge drive signal HS does not exceed the enable period of the lower bridge drive signal LS, the second counter 1030 counts down the digital code B, causing the second digital-to-analog converter 1040 to reduce the adjustment current ID.

Signal generation circuit 1020 includes an eleventh AND gate AND11, a fifth current source CS5, a third N-type transistor MN3, a seventh capacitor C7, a sixth inverter INV6, and a twelfth AND gate AND12. AND11 performs logic operations on the upper-bridge dead-band timing signal CK_H and the lower-bridge dead-band timing signal CK_L to generate a clock signal CLK. When either the upper-bridge dead-band timing signal CK_H or the lower-bridge dead-band timing signal CK_L is in a negative pulse, the clock signal CLK is disabled, and the seventh current I7 of the fifth current source CS5 charges the seventh capacitor C7 to generate the second capacitor voltage VCAP2. Furthermore, the sixth inverter INV6 inverts the clock signal CLK, causing the latch signal LTH output by the twelfth AND gate AND12 to generate a positive edge, thereby triggering the fourth flip-flop FF4 and the fifth flip-flop FF5 to latch the up signal UP and the down signal DWN, respectively.

According to one embodiment of the present invention, when the enable period of the upper bridge drive signal HS exceeds the enable period of the lower bridge drive signal LS, the adjustment current ID is increased to increase the offset voltage VOS and the base voltage VBS, thereby shortening the enable period of the upper bridge drive signal HS and extending the enable period of the lower bridge drive signal LS. According to another embodiment of the present invention, when the enable period of the high-side drive signal HS does not exceed the enable period of the low-side drive signal LS, the adjustment current ID is reduced to lower the offset voltage VOS and the base voltage VBS, thereby extending the enable period of the high-side drive signal HS and shortening the enable period of the low-side drive signal LS. In other words, by adjusting the base voltage VBS, the enable period of the high-side drive signal HS is brought closer to the enable period of the low-side drive signal LS.

FIG11 is a block diagram of an output voltage detection circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the control circuit 160 of FIG1 further includes an output voltage detection circuit 1100. As shown in FIG11 , the output voltage detection circuit 1100 includes a sixth comparator CMP6, a sixth flip-flop FF6, a seventh inverter INV7, an eighth inverter INV8, and a delay circuit 1110.

The sixth comparator CMP6 compares the feedback voltage FB with the low-power threshold voltage VTLP to generate a comparison signal CP. According to one embodiment of the present invention, when the output voltage VOUT in FIG. 1 increases, the feedback voltage FB decreases. This increase in output voltage VOUT indicates a decrease in output power. In other words, when the comparison signal CP in FIG. 10 is at a high logical level, it indicates that the output power is too low.

The seventh inverter INV7 inverts the lower-bridge dead-band timing signal CK_L, triggering the sixth flip-flop FF6 to output the comparison signal CP as the pre-burst signal PSR. This in turn generates the inverted pre-burst signal PSB via the eighth inverter INV8. The sixth flip-flop FF6 outputs the comparison signal CP as the pre-burst signal PSR in response to the positive edge of the output signal from the seventh inverter INV7. Furthermore, the pre-burst signal PSR is enabled when the overcurrent signal OCP is at a low logic level and disabled when the reset signal ST is at a low logic level.

After receiving the high-logic-level inverted pre-burst signal PSB, the delay circuit 1110 delays the signal by a delay time to generate a reset signal ST to reset the pre-burst signal PSR. The third mapped current IB3 in FIG. 4 is used to adjust the delay time of the delay circuit 1110. According to one embodiment of the present invention, the delay circuit 1110 can be implemented by the delay time generator 800 in FIG. 8 , where the pre-burst signal PSR corresponds to the input signal IN in FIG. 8 , and the reset signal ST corresponds to the output signal OUT in FIG. The detailed operation will not be repeated here.

As shown in FIG11 , the output voltage detection circuit 1100 further includes a fourth N-type transistor MN4, a sixth current source CS6, an eighth capacitor C8, a first NOR gate NOR1, a seventh flip-flop FF7, a ninth inverter INV9, a fourth OR gate OR4, and a thirteenth AND gate AND13.

The fourth N-type transistor MN4 is controlled by the zero-current signal ZCD and discharges the third capacitor voltage VCAP3 to ground. The eighth capacitor C8 is coupled between the third capacitor voltage VCAP3 and ground. The sixth current source CS6 provides an eighth current I8 to charge the eighth capacitor C8, generating the third capacitor voltage VCAP3. The seventh flip-flop FF7 enables the first signal S1 (i.e., a high logic level) based on the positive edge of the pre-burst signal PSR. The ninth inverter INV9 inverts the first signal S1 to generate a first inverted signal S1B. The first NOR gate NOR1 performs a negative-OR operation on the third capacitor voltage VCAP3 and the low-bridge drive signal LS to reset the first signal S1.

The fourth OR gate OR4 performs a logical OR operation on the first inverted signal S1B and the zero-current signal ZCD to generate the second signal S2. The thirteenth AND gate AND13 performs a logical AND operation on the inverted pre-burst signal PSB and the second signal S2 to generate the burst signal BST. According to one embodiment of the present invention, when the power conversion circuit 100 returns from the burst mode to the normal operating mode (i.e., the burst signal BST transitions from a low logic level to a high logic level), the rising edge of the burst signal BST is aligned with the rising edge of the zero-current signal ZCD. In other words, the power conversion circuit 100 returns from the burst mode to the normal operating mode only when the current flowing through the resonant capacitor CR approaches zero. According to some embodiments of the present invention, when the power conversion circuit 100 operates in a normal operation mode, the power conversion circuit 100 can operate in one of a flyback mode and a non-flyback mode.

FIG12 shows waveforms of a resonant power conversion circuit according to an embodiment of the present invention operating under light load. As shown in FIG12 , when the burst signal BST is at a high logic level (i.e., disabled), the resonant power conversion circuit 100 of FIG1 operates in normal operation mode. Therefore, the high-side drive signal HS and the low-side drive signal LS alternate to turn on the high-side transistor 111 and the low-side transistor 112, respectively.

When the output voltage VOUT continues to rise, causing the burst signal BST to transition to a low logic level (i.e., enabled), the power conversion circuit 100 operates in burst mode, causing both the high-side drive signal HS and the low-side drive signal LS to remain disabled, while simultaneously turning off the high-side transistor 111 and the low-side transistor 112. Furthermore, the falling edge of the burst signal BST is aligned with the falling edge of the high-side drive signal HS, and the rising edge of the burst signal BST is aligned with the rising edge of the low-side drive signal LS.

FIG13 is a block diagram of a second current detection circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the second current detection circuit 1300 corresponds to the second current detection circuit 150 in FIG1 and includes a first comparison circuit 1310 and a second comparison circuit 1320.

When the current detection voltage VCS at the second current detection node ND2 exceeds the upper threshold voltage VTH or is lower than the lower threshold voltage VTL, the first comparison circuit 1310 generates a negative pulse on the over-current signal OCP. When the current detection voltage VCS exceeds the upper threshold voltage VTH or is lower than the lower threshold voltage VTL, an over-current condition has occurred (i.e., the current flowing through the resonant capacitor CR exceeds a preset value).

When the current detection voltage VCS is less than the zero-current threshold voltage VTZ, the second comparison circuit 1320 generates a negative pulse on the zero-current signal ZCD. In other words, when the zero-current signal ZCD is at a low logical level, it indicates that the current flowing through the resonant capacitor CR is close to zero. According to one embodiment of the present invention, the zero-current threshold voltage VTZ is slightly greater than zero.

Specifically, the first comparator circuit 1310 includes a seventh comparator CMP7, an eighth comparator CMP8, a fifth OR gate OR5, and a delay circuit 1311. The seventh comparator CMP7 is used to compare the current detection voltage VCS with the upper threshold voltage VTH, and the eighth comparator CMP8 is used to compare the current detection voltage VCS with the lower threshold voltage VTL. When the current detection voltage VCS exceeds the upper threshold voltage VTH or falls below the lower threshold voltage VTL, the output signals of the seventh comparator CMP7 and the eighth comparator CMP8 trigger the delay circuit 1311 via the fifth OR gate OR5, generating a negative pulse on the overcurrent signal OCP. According to one embodiment of the present invention, the delay circuit 1311 can be implemented by the delay time generator 800 of Figure 8 , where the output signal of the fifth OR gate OR5 corresponds to the input signal IN of Figure 8 , and the overcurrent signal OCP corresponds to the output signal OUT of Figure 8 . The detailed operation will not be repeated here.

The second comparator circuit 1320 includes a ninth comparator CMP9, a seventh current source CS7, a ninth capacitor C9, a fifth N-type transistor MN5, and a second NOR gate NOR2. The ninth comparator CMP9 compares the current detection voltage VCS with the zero-current threshold voltage VTZ to generate a comparison result CRE. The seventh current source CS7 provides a ninth current I9 to the fourth capacitor voltage VCAP4 to charge the ninth capacitor C9. The fifth N-type transistor MN5 couples the fourth capacitor voltage VCAP4 to ground based on the comparison result CRE. The second NOR gate NOR2 performs a logical NOR operation on the fourth capacitor voltage VCAP4 and the comparison result CRE to generate a zero-current signal ZCD.

According to one embodiment of the present invention, when the comparison result CRE transitions from a high logic level to a low logic level, that is, when the current detection voltage VCS drops below the zero current threshold voltage VTZ, the fifth N-type transistor MN5 turns off, causing the ninth capacitor C9 to begin charging, thereby generating a positive pulse on the zero current signal ZCD.

Figure 14 shows a waveform diagram of a power conversion circuit according to one embodiment of the present invention. The following description of the waveform diagram in Figure 14 will be used in conjunction with Figures 1 and 13 for detailed explanation.

As shown in Figures 1 and 13, when power conversion circuit 100 is operating, a sine wave-like signal appears at switching node SW. As shown in Figure 1, the signal at resonant node NR is coupled to current detection voltage VCS via first capacitor C1 and second capacitor C2. In other words, current detection voltage VCS is an AC signal.

As shown in Figures 13 and 14, when the current detection voltage VCS exceeds the zero-current threshold voltage VTZ, the comparison result CRE is at a high logical level. As the current detection voltage VCS gradually decreases and falls below the zero-current threshold voltage VTZ, the comparison result CRE begins to fall, causing a positive pulse to appear on the zero-current signal ZCD. Furthermore, as shown in Figure 14, the positive pulse of the zero-current signal ZCD occurs near the trough of the signal at the switching node SW.

As shown in Figure 11 , the burst signal BST is at a high logic level based on the zero current signal ZCD being at a high logic level. As shown in Figure 11 , when the burst signal BST is at a high logic level (i.e., disabled), the power conversion circuit 100 enters normal operation mode. When the resonant power conversion circuit 100 enters normal operation mode, the lower bridge drive signal LS first enters an enabled state. That is, when the resonant power conversion circuit 100 transitions from burst mode to normal operation mode, the lower bridge transistor 112 turns on first, and the lower bridge transistor 112 turns on when the signal at the switching node SW is at its lowest point.

In other words, when the power conversion circuit 100 switches from the burst mode to the normal operation mode, the low-bridge transistor 112 is turned on at the valley of the signal at the switching node SW, which helps reduce the power loss caused by the switching.

FIG15 is a block diagram of a secondary control circuit according to one embodiment of the present invention. According to one embodiment of the present invention, the secondary control circuit 1500 in FIG15 corresponds to the secondary control circuit 181 in FIG1.

As shown in Figure 15 , secondary control circuit 1500 includes a synchronous rectifier controller 1510, a second voltage divider circuit 1520, a tenth comparator CMP10, a tenth inverter INV10, an eighth flip-flop FF8, and an eleventh inverter INV11. Synchronous rectifier controller 1510 generates a first rectified signal SR1 based on a first coil voltage VW1 and a second rectified signal SR2 based on a second coil voltage VW2, thereby controlling the first rectifier transistor MR1 and the second rectifier transistor MR2 shown in Figure 1 .

The second voltage divider circuit 1520 divides the output voltage VOUT to generate a second divided voltage VD2. The tenth comparator CMP10 compares the second divided voltage VD2 with the low-voltage threshold value VT_MD to generate a rectifier comparison signal CMPR. According to one embodiment of the present invention, when the second divided voltage VD2 is not less than the low-voltage threshold value VT_MD, the rectifier comparison signal CMPR is enabled. According to another embodiment of the present invention, when the second divided voltage VD2 is less than the low-voltage threshold value VT_MD, the rectifier comparison signal CMPR is disabled.

According to one embodiment of the present invention, the second divided voltage VD2 is the output voltage VOUT multiplied by a first ratio, and the low voltage threshold VT_MD is the output threshold multiplied by a second ratio, where the first ratio is equal to the second ratio. According to some embodiments of the present invention, the second divided voltage VD2 is equal to the reflected voltage RFV. According to other embodiments of the present invention, the second divided voltage VD2 may not be equal to the reflected voltage RFV. This is for illustrative purposes only and is not intended to be limiting in any way.

The tenth inverter INV10 inverts the first rectified signal SR1 to generate a first inverted rectified signal SR1B. The eighth flip-flop FF8, based on the signal edge of the first inverted rectified signal SR1B, outputs the rectified comparison signal CMPR as a fourth rectified signal SR4. The eleventh inverter INV11 inverts the fourth rectified signal SR4 to generate a third rectified signal SR3, which is used to drive the third rectifier transistor MR3 in Figure 1.

In other words, when the control circuit 160 of FIG. 1 operates in non-flyback mode, the third rectifier transistor MR3 is conductive, causing the rectifier circuit 180 of FIG. 1 to perform full-wave rectification of the energy in the first and second secondary windings NS1 and NS2 to generate the output voltage VOUT, and the third rectified signal SR3 is synchronized with the first rectified signal SR1. When the control circuit 160 of FIG. 1 operates in flyback mode, the third rectifier transistor MR3 is non-conductive, causing the rectifier circuit 180 of FIG. 1 to perform half-wave rectification of the energy in the second secondary winding NS2 to generate the output voltage VOUT, and the third rectified signal SR3 is synchronized with the first rectified signal SR1.

FIG16 is a flow chart illustrating a control method for controlling a power conversion circuit according to one embodiment of the present invention. The following description of the control method 1600 in FIG16 will be used in conjunction with the power conversion circuit 100 in FIG1 for detailed explanation.

The control circuit 160 in Figure 1 drives the high-side transistor 111 and the low-side transistor 112 based on the feedback voltage FB, the output voltage VOUT, and the current flowing through the resonant capacitor CR (step S1610). Specifically, the reflected voltage RFV is related to the output voltage VOUT. The mode determination circuit 500 of the control circuit 160 (shown in Figure 5) uses the reflected voltage RFV related to the output voltage VOUT to determine whether to operate in the flyback mode or the non-flyback mode.

Furthermore, the control circuit 160 drives the high-side transistor 111 and the low-side transistor 112 based on the rectified signal FW generated by the full-wave rectifier 140, the over-current signal OCP and the zero-current signal ZCD generated by the second current detection circuit 150, and the current detection voltage VCS at the second detection node ND2. The detailed operation is described in Figures 2, 4, and 6 and will not be repeated here.

Next, the rectifier circuit 180 is used to determine whether the output voltage VOUT is less than the output threshold (step S1620). If the output voltage VOUT is less than the output threshold, the power conversion circuit 100 is operated in flyback mode and the energy of the secondary winding SS is half-wave rectified by the rectifier circuit 180 to generate the output voltage VOUT (step S1630). If the output voltage VOUT is not less than the output threshold, the power conversion circuit 100 is operated in non-flyback mode and the energy of the secondary winding SS is full-wave rectified by the rectifier circuit 180 to generate the output voltage VOUT (step S1640).

As shown in Figure 15 , the second voltage divider circuit 1520 and the tenth comparator CMP10 determine whether the second divided voltage VD2 is less than the low-voltage threshold VT_MD, thereby generating a third rectified signal SR3 to control the third rectifier transistor MR3. The synchronous rectifier controller 1510 generates the first rectified signal SR1 based on the first coil voltage VW1 and the second rectified signal SR2 based on the second coil voltage VW2. The third rectified signal SR3 is synchronized with the signal edge of the first rectified signal SR1.

According to one embodiment of the present invention, the second divided voltage VD2 is the output voltage VOUT multiplied by a first ratio, and the low voltage threshold VT_MD is the output threshold multiplied by a second ratio, where the first ratio is equal to the second ratio.

This invention proposes a power conversion circuit capable of operating in either flyback mode or resonance mode, and a control method thereof. By automatically switching the power conversion circuit between flyback mode and resonance mode, the circuit provides a wide output voltage range and high output power, while also improving conversion efficiency under light loads and low output voltages.

While the embodiments and advantages of this disclosure have been described above, it should be understood that changes, substitutions, and modifications may be made by anyone skilled in the art without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps described in the specific embodiments herein. Anyone skilled in the art will be able to understand from the disclosure of certain embodiments of this disclosure that any current or future developed processes, machines, manufactures, compositions of matter, devices, methods, and steps that can perform substantially the same functions or achieve substantially the same results as those described herein may be used in accordance with certain embodiments of this disclosure. Therefore, the scope of protection of the present disclosure includes the aforementioned processes, machines, manufacture, compositions of matter, devices, methods, and steps. In addition, each patent claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of individual patent claims and embodiments.

100: Power conversion circuit

111: Upper bridge transistor

112: Lower bridge transistor

121: First current detection circuit

122: First voltage divider circuit

130: Integrator

131: Integral Amplifier

140: Full-wave rectifier

150: Second current detection circuit

160: Control circuit

170: Level shift circuit

180: Rectifier circuit

181: Secondary control circuit

190: Feedback circuit

TM: Transformer

LR: Resonant Inductor

CR: Resonance Capacitor

HSD: High-side drive circuit

LSD: Lower Drive Circuit

PS: Beginner coil

SS: Secondary coil

AS: Auxiliary coil

NS1: First secondary coil

NS2: Secondary coil

NR: Resonance Node

NA: auxiliary node

RD1: First voltage divider resistor

RD2: Second voltage divider resistor

N1: First endpoint

N2: Second endpoint

N3: Third endpoint

N4: Fourth endpoint

NRC: Rectifier Node

SW: switch node

HSG: High-side gate drive signal

LSG: Lower Gate Drive Signal

VIN: Input voltage

C1: First capacitor

C2: Second capacitor

C3: The third capacitor

DR: Voltage Regulator

R1: First resistor

R2: Second resistor

R3: The third resistor

R5: The fifth resistor

R6: Sixth resistor

R7: Seventh resistor

R8: Eighth resistor

FW: Rectified signal

FB: Feedback voltage

SZ: Cross signal

COUT: output capacitance

HS: Upper bridge drive signal

LS: Lower bridge drive signal

MR1: First rectifier transistor

MR2: Second rectifier transistor

MR3: Third rectifier transistor

VW1: First coil voltage

VW2: Second coil voltage

VOUT: output voltage

VD1: First divided voltage

PD: Photocoupler

LED: diode

Q: Transistor

VCC: supply voltage

VCS: Current detection voltage

CS: Current detection signal

INT: Integral signal

OCP: Overcurrent signal

ZCD: Zero Current Signal

ND1: First detection node

ND2: Second detection node

VREF: Reference voltage

SR1: First rectified signal

SR2: Second rectified signal

SR3: Third rectified signal

Claims (31)

A power conversion circuit includes: a resonant capacitor coupled between a resonant node and a ground terminal; a transformer including a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and the resonant node; a high-side transistor providing an input voltage to the switching node based on an high-side drive signal; a low-side transistor coupling the switching node to the ground terminal based on a low-side drive signal; a control circuit generating the high-side drive signal and the low-side drive signal based on a feedback voltage, and operating in one of a flyback mode and a non-flyback mode based on an output voltage; A feedback circuit generates the feedback voltage based on the output voltage; and A rectifier circuit generates the output voltage by full-wave or half-wave rectifying the energy in the secondary coil based on the output voltage. When the output voltage is less than an output threshold, the control circuit operates in the flyback mode, and the rectifier circuit half-wave rectifys the energy in the secondary coil to generate the output voltage. The power conversion circuit of claim 1, wherein the control circuit switches from the foldback mode to the non-foldback mode or from the non-foldback mode to the foldback mode based on a signal edge of the lower bridge drive signal. A power conversion circuit as claimed in claim 1, wherein the secondary coil includes a first secondary coil and a second secondary coil, and when the output voltage is not less than the output threshold value, the control circuit operates in the non-flyback mode and the rectifier circuit full-wave rectifies the energy of the first secondary coil and the second secondary coil to generate the output voltage. The power conversion circuit of claim 1, wherein the secondary coil includes a first secondary coil and a second secondary coil, wherein the first secondary coil includes a first terminal and a second terminal, and the second secondary coil includes a third terminal and a fourth terminal, wherein the first terminal and the fourth terminal are both coupled to the output voltage; The rectifier circuit includes: a first rectifier transistor, coupling the second terminal to the ground terminal based on a first rectifier signal; a second rectifier transistor, coupling the third terminal to a rectifier node based on a second rectifier signal; and a third rectifier transistor, coupling the rectifier node to the ground terminal based on a third rectifier signal; When the output voltage is less than the output threshold, the third rectifier transistor is non-conductive, causing the rectifier circuit to half-wave rectify the energy of the second secondary coil to generate the output voltage. The third rectified signal is synchronized with the first rectified signal. The power conversion circuit of claim 4, wherein the rectifier circuit further comprises: a secondary control circuit comprising: a synchronous rectifier controller, generating the first rectified signal based on the voltage at the second terminal and generating the second rectified signal based on the voltage at the third terminal; a first voltage divider circuit, dividing the output voltage to generate a first divided voltage; a first comparator, comparing the first divided voltage with a low voltage threshold to generate a rectified comparison signal; a first inverter, inverting the first rectified signal to generate a first inverted rectified signal; a first flip-flop, outputting the rectified comparison signal as a fourth rectified signal based on a signal edge of the first inverted rectified signal; and A second inverter inverts the fourth rectified signal to generate the third rectified signal. The first divided voltage is the output voltage multiplied by a first ratio, and the low voltage threshold is the output threshold multiplied by a second ratio. The first ratio is equal to the second ratio. The power conversion circuit of claim 1, wherein the transformer further comprises: an auxiliary coil coupled between an auxiliary node and the ground terminal; the power conversion circuit further comprises a second voltage divider circuit for dividing the voltage at the auxiliary node to generate a reflected voltage; the reflected voltage is related to the output voltage; the control circuit further operates in one of the flyback mode and the non-flyback mode based on the reflected voltage. The power conversion circuit of claim 6, wherein the control circuit further comprises: A mode determination circuit comprising: A first pulse generator, generating a pulse signal based on the lower bridge drive signal; A determination gate, performing a logic operation on the lower bridge drive signal and the pulse signal to generate a sampling signal; A sampling switch, sampling the reflected voltage based on the sampling signal and storing the sampled reflected voltage in a sampling capacitor as a sampling voltage; A first determination inverter, inverting the sampling signal to generate an inverted sampling signal; A second pulse generator generates a holding signal based on the inverted sampling signal; a holding switch samples the sampled voltage based on the holding signal and stores the sampled voltage in a holding capacitor as a holding voltage; a determination comparator compares the holding voltage with a low-voltage threshold to generate a determination signal; and a determination flip-flop latches the determination signal into a mode signal based on the inverted phase of a load dead-band time signal; wherein when the holding voltage is less than the low-voltage threshold, the determination signal and the mode signal are in a disabled state. When the holding voltage is not less than the low-voltage threshold, the determination signal and the mode signal are in the same enabled state. The low-voltage threshold is the output threshold multiplied by a ratio. The power conversion circuit of claim 7 further comprises: a first current detection circuit generating a current detection signal based on the voltage at the resonant node; an integrator generating an integrated signal based on the current detection signal; and a full-wave rectifier device generating a rectified signal by full-wave rectifying the integrated signal generated by the integrator; wherein the control circuit further generates the upper bridge drive signal and the lower bridge drive signal based on the rectified signal. The power conversion circuit of claim 8, wherein the first current detection circuit comprises: a first capacitor coupled between the resonant node and a first detection node; and a first resistor coupled between the first detection node and the ground terminal; wherein the first current detection circuit generates the current detection signal at the first detection node. The power conversion circuit of claim 9, wherein the integrator comprises: an integrating amplifier including an integrating positive input terminal, an integrating negative input terminal, and an integrating output terminal, wherein the integrating positive input terminal receives a reference voltage and the integrating output terminal generates the integrating signal; a second capacitor coupled between the first detection node and a second detection node; a second resistor coupled between the second detection node and the integrating negative input terminal; a third resistor coupled between the integrating negative input terminal and the integrating output terminal; and a third capacitor coupled between the integrating negative input terminal and the integrating output terminal. The power conversion circuit of claim 10, wherein the full-wave rectifier performs full-wave rectification on the integrated signal using a base voltage as a DC level to generate the rectified signal; wherein the base voltage is equal to the sum of the reference voltage and an offset voltage; wherein the full-wave rectifier further compares the rectified signal with a first threshold voltage to generate a crossover signal; wherein the first threshold voltage is slightly greater than the base voltage. The power conversion circuit of claim 11, wherein the offset voltage is determined based on a difference between an enable period of the upper bridge drive signal and an enable period of the lower bridge drive signal; The offset voltage is used to adjust the enable period of the upper bridge drive signal and the enable period of the lower bridge drive signal so that the enable period of the upper bridge drive signal is closer to the enable period of the lower bridge drive signal. The power conversion circuit of claim 11, wherein the control circuit comprises: a digital circuit that gradually increases a soft-start voltage to the feedback voltage over a predetermined time period; a first amplifier comprising a first positive input terminal, a first negative input terminal, and a first output terminal, wherein the first positive input terminal receives the soft-start voltage, and the first negative input terminal is coupled to the first output terminal; a second amplifier comprising a second positive input terminal, a second negative input terminal, and a second output terminal, wherein the second positive input terminal receives a feedback threshold voltage, and the second output terminal generates a compensation voltage; a second resistor coupled between the second negative input terminal and the first output terminal, and generating a differential current; An N-type transistor comprising a gate terminal, a drain terminal, and a source terminal, wherein the gate terminal is coupled to the second output terminal, and the source terminal is coupled to the second negative input terminal; A current mirror maps the differential current into at least one mapped current; and A summing circuit subtracts a sawtooth wave from the compensation voltage to generate a compensation signal; When the soft-start voltage is less than the feedback threshold voltage, the compensation voltage is equal to the feedback threshold voltage; When the soft-start voltage is not less than the feedback threshold voltage, the compensation voltage is equal to the soft-start voltage. The power conversion circuit of claim 13, wherein when the rectified signal is less than the first threshold voltage, the full-wave rectifier sets the cross signal to the disabled state; When the rectified signal exceeds the first threshold voltage, the full-wave rectifier sets the cross signal to the enabled state; In response to the cross signal changing from the disabled state to the enabled state or the mode signal being in the disabled state, the control circuit sets a phase signal to the enabled state; In response to the control circuit setting the phase signal to the disabled state based on either the upper bridge dead-band time signal and the lower bridge dead-band time signal or the mode signal being in the enabled state; In response to the upper bridge dead-band time signal controlling the upper bridge dead-band time of one of the upper bridge drive signals; The above-mentioned lower bridge dead zone time signal controls the lower bridge dead zone time of one of the above-mentioned lower bridge drive signals. The power conversion circuit of claim 14, wherein when the upper bridge drive signal turns on the upper bridge transistor, the phase signal is in the enabled state, and the mode signal is in the enabled state, the control circuit disables the upper bridge drive signal in response to the rectified signal exceeding the compensation signal; When the upper bridge drive signal turns on the upper bridge transistor, the phase signal is in the enabled state, and the mode signal is in the disabled state, the control circuit disables the upper bridge drive signal in response to the voltage at the second detection node exceeding the compensation signal; When the upper bridge signal does not turn on the upper bridge transistor, the control circuit enables the lower bridge drive signal after the lower bridge dead band time to turn on the lower bridge transistor. When the lower bridge drive signal turns on the lower bridge transistor, the phase signal is in the enabled state, and the mode signal is in the enabled state, the control circuit disables the lower bridge drive signal in response to the rectified signal exceeding the compensation signal. When the lower bridge drive signal turns on the lower bridge transistor, the phase signal is in the enabled state, and the mode signal is in the disabled state, the control circuit disables the lower bridge drive signal in response to the voltage of the second detection node exceeding the compensation signal. When the lower bridge driving signal does not turn on the lower bridge transistor, the control circuit enables the upper bridge driving signal after the upper bridge dead time to turn on the upper bridge transistor. The power conversion circuit of claim 14, wherein the control circuit further limits the enable cycle of the upper bridge drive signal and the enable cycle of the lower bridge drive signal to no more than a maximum enable cycle; wherein the maximum enable cycle varies based on the mode signal. The power conversion circuit of claim 14, wherein the feedback voltage decreases in response to an increase in the output voltage; in response to the feedback voltage being lower than a low-power threshold voltage, the lower-side dead-band timing signal enables a burst signal, causing the control circuit to operate in a burst mode based on the enabled burst signal; when the control circuit operates in the burst mode, both the upper-side transistor and the lower-side transistor are non-conductive; in which a duration of the burst mode increases as the output power of the output voltage decreases. The power conversion circuit of claim 17 further comprises: A second current detection circuit generating an overcurrent signal and a zero-current signal based on the current detection signal; When the current flowing through the resonant capacitor exceeds a preset value, the overcurrent signal is in a reset state, and the control circuit disables the upper bridge drive signal and the lower bridge drive signal based on the overcurrent signal being in the reset state; When the current flowing through the resonant capacitor is approximately zero, the zero-current signal is in the enable state, causing the control circuit to enable the lower bridge drive signal based on the zero-current signal being in the enable state. The power conversion circuit of claim 18, wherein the control circuit further operates in the burst mode based on the burst signal being in the enabled state and the zero-current signal being in the enabled state; The burst mode begins when the upper bridge drive signal is in the disabled state and ends when the lower bridge drive signal is in the enabled state. The power conversion circuit of claim 19, wherein the second current detection circuit comprises: a first comparison circuit that compares the voltage of the second detection node with an upper threshold voltage and a lower threshold voltage to generate the overcurrent signal; and a second comparison circuit that compares the voltage of the second detection node with a zero current threshold voltage to generate the zero current signal; wherein, when the voltage of the second detection node is greater than the upper threshold voltage or the voltage of the detection node is less than the lower threshold voltage, the first comparison circuit sets the overcurrent signal to the reset state; When the voltage at the second detection node exceeds the zero-current threshold voltage, the second comparison circuit sets the zero-current signal to the enabled state. The zero-current threshold voltage is slightly greater than zero. A control method is provided for controlling a power conversion circuit, wherein the power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, a high-bridge transistor that provides an input voltage to a switching node, a low-bridge transistor that couples the switching node to the ground terminal, a rectifier circuit that converts energy flowing through the secondary coil into an output voltage, and a feedback circuit that generates a feedback voltage based on the output voltage. The primary coil is coupled between the switching node and the resonant node. The control method includes: The upper and lower bridge transistors are driven based on the feedback voltage, the output voltage, and the current flowing through the resonant capacitor. Determining whether the output voltage is less than an output threshold value; When the output voltage is determined to be less than the output threshold value, half-wave rectifying the energy in the secondary coil by the rectifying circuit to generate the output voltage; and When the output voltage is determined to be not less than the output threshold value, full-wave rectifying the energy in the secondary coil by the rectifying circuit to generate the output voltage. The control method of claim 21, wherein the secondary coil includes a first secondary coil and a second secondary coil; When the output voltage is less than the output threshold value, the rectifier circuit converts energy from one of the first secondary coil and the second secondary coil into the output voltage; When the output voltage is not less than the output threshold value, the rectifier circuit converts energy from the first secondary coil and the second secondary coil into the output voltage. The control method of claim 21, wherein the transformer further includes an auxiliary coil coupled between an auxiliary node and the ground terminal, wherein the control method further includes: Using a voltage divider circuit to divide the voltage of the auxiliary node to generate a reflected voltage; Determining whether the reflected voltage is less than a low voltage threshold; When the reflected voltage is determined to be less than the low voltage threshold, operating the power conversion circuit in a flyback mode; and When the reflected voltage is determined to be not less than the low voltage threshold, operating the power conversion circuit in a non-flyback mode; When the lower bridge transistor is turned on, the power conversion circuit switches from the flyback mode to the non-flyback mode or vice versa. The reflected voltage is related to the output voltage. The control method of claim 23, wherein the step of determining whether the reflected voltage is less than the low voltage threshold further includes: Based on the lower bridge transistor being conductive, sampling the reflected voltage and storing it as a sampled voltage; Based on the lower bridge transistor being non-conductive, sampling the sampled voltage and storing it as a holding voltage; Comparing the holding voltage with the low voltage threshold using a comparator to generate a determination signal, wherein when the holding voltage is not less than the low voltage threshold, the determination signal is in an enabled state, and when the holding voltage is less than the low voltage threshold, the determination signal is in a disabled state; Based on a dead-band time of a pull-up transistor, the determination signal is latched as a mode signal. When the mode signal is in the enabled state, the power conversion circuit is operated in the non-flyback mode. And when the mode signal is in the disabled state, the power conversion circuit is operated in the flyback mode. The control method of claim 23 further includes: Detecting the current flowing through the resonant capacitor using a first current detection circuit to generate a current detection signal; Integrating the current detection signal based on a reference voltage to generate an integrated signal; Full-wave rectifying the integrated signal to generate a rectified signal; and Driving the upper bridge transistor and the lower bridge transistor based on the rectified signal; The first current detection circuit includes a first capacitor and a first resistor, the first capacitor coupled between the resonant node and a first detection node, and the first resistor coupled between the first detection node and the ground terminal; The current detection signal is generated at the first detection node; A second capacitor is coupled between the first detection node and a second detection node. The control method of claim 25 further comprises: Full-wave rectifying the integrated signal using a base voltage as a DC level to generate the rectified signal; Comparing the rectified signal with a first threshold voltage to generate a crossover signal; Wherein, the base voltage is equal to the sum of the reference voltage and an offset voltage; Wherein, the first threshold voltage is slightly greater than the base voltage. The control method of claim 26 further includes: gradually increasing a soft-start voltage to the feedback voltage over a predetermined period of time; converting the soft-start voltage into a compensation voltage; and subtracting a sawtooth wave from the compensation voltage to generate a compensation signal; wherein, when the soft-start voltage is less than a feedback threshold voltage, the compensation voltage is equal to the feedback threshold voltage; wherein, when the soft-start voltage is not less than the feedback threshold voltage, the compensation voltage is equal to the soft-start voltage. The control method of claim 27 further includes: When the rectified signal is less than the first threshold voltage, setting the cross signal to a disabled state; When the rectified signal exceeds the first threshold voltage, setting the cross signal to an enabled state; In response to the cross signal changing from the disabled state to the enabled state, setting a phase signal to the enabled state; and In response to the rectified signal exceeding the compensation signal, setting the phase signal to the disabled state during an upper bridge dead band time or a lower bridge dead band time; wherein the lower bridge dead band time is the time from when the upper bridge transistor becomes non-conductive to when the lower bridge transistor becomes conductive; The upper bridge dead time is the time from when the lower bridge transistor turns off to when the upper bridge transistor turns on. The control method of claim 28 further comprises: When the upper bridge transistor is conducting, the phase signal is in the enabled state, and the power conversion circuit operates in the non-flyback mode, in response to the rectifier signal exceeding the compensation signal, turning off the upper bridge transistor; When the upper bridge transistor is conducting, the phase signal is in the enabled state, and the power conversion circuit operates in the flyback mode, in response to the voltage of the second detection node exceeding the compensation signal, turning off the upper bridge transistor; When the upper bridge transistor is non-conducting, turning on the lower bridge transistor after the lower bridge dead band time; When the lower bridge transistor is conducting, the phase signal is in the enabled state, and the power conversion circuit operates in the non-flyback mode, the lower bridge transistor is turned off in response to the rectified signal exceeding the compensation signal. When the lower bridge transistor is conducting, the phase signal is in the enabled state, and the power conversion circuit operates in the flyback mode, the lower bridge transistor is turned off in response to the voltage at the second detection node exceeding the compensation signal. When the lower bridge transistor is off, the upper bridge transistor is turned on after the upper bridge dead band time. The control method of claim 28 further includes: In response to the feedback voltage being lower than a low-power threshold voltage, operating the power conversion circuit in a burst mode, wherein the feedback voltage decreases in response to an increase in the output voltage; In the burst mode, simultaneously turning off the high-side transistor and the low-side transistor; and In response to a decrease in output power of the output voltage, increasing a duration of the burst mode. The control method of claim 30 further includes: When the current flowing through the resonant capacitor exceeds a preset value, simultaneously turning off the upper and lower bridge transistors; and When the current flowing through the resonant capacitor is approximately zero, turning on the lower bridge transistor; Wherein, the burst mode begins when the upper bridge transistor turns off and ends when the lower bridge transistor turns on.