TWI891425B - Pixel driving circuit and display - Google Patents

Abstract

A pixel driving circuit and a display are provided. The pixel driving circuit includes multiple stages of data driving circuits. The data driving circuits are disposed in a non-display area. An n-th data driving circuit includes a horizontal shift register and multiple stages of data processing circuits. The horizontal shift register is divided into horizontal shift register blocks based on a default number. The data processing circuits are divided into data processing circuit blocks based on the default number. Each one of the horizontal shift register blocks is coupled to one of the corresponding data processing circuit blocks, and is disposed at each one of side edges of the non-display area, thereby, a circuit area of the data driving circuits in the non-display area being reduced.

Description

Pixel driver circuit and display

The present invention relates to an electronic circuit, and in particular to a pixel driver circuit and a display.

Displays achieve display functionality by using pixel driver circuits to drive multiple pixel circuits within the display area. Generally speaking, each level of data driver circuits (or source driver circuits) within the pixel driver circuits is coupled to multiple pixel circuits located in the same row to provide corresponding display data.

For non-rectangular display areas, multiple levels of data driver circuits are arranged sequentially in the non-display area based on the display area's outer frame. However, the spacing between these data driver circuits in the arrangement direction (e.g., horizontally) is limited by the spacing between the multiple pixel circuits corresponding to each level of data driver circuits. This increases the circuit area required for the multi-level data driver circuits in the non-display area, and the blank layout area between the multi-level data driver circuits and the display area also increases, making this design impractical for displays with slim borders.

An embodiment of the present invention provides a pixel driver circuit suitable for use in a display, capable of reducing the circuit area of a multi-level data driver circuit in a non-display area.

A pixel driver circuit according to an embodiment of the present invention includes a multi-stage data driver circuit. The multi-stage data driver circuit is disposed in a non-display area of a display. The nth stage of the multi-stage data driver circuit includes a horizontal shift register and a multi-stage data processing circuit. The horizontal shift register is divided into a plurality of horizontal shift register blocks based on a preset number. The multi-stage data processing circuit is divided into a plurality of data processing circuit blocks based on a preset number. Each horizontal shift register block is coupled to a corresponding one of the plurality of data processing circuit blocks and is disposed on each of the plurality of sides of the non-display area. n is a positive integer.

Another embodiment of the present invention provides a display. The display includes a pixel array and the aforementioned pixel driver circuit. The pixel array is disposed in a display area. The pixel driver circuit is coupled to the pixel array. The pixel driver circuit is disposed in a non-display area adjacent to the display area and is used to drive the pixel array.

Based on the above, the pixel driver circuit and display of the present invention divide the multiple circuit elements in each level of the data driver circuit into corresponding blocks based on a preset number. The data driver circuits are then arranged sequentially based on the spacing between the pixels corresponding to the blocks. This reduces the spacing between multiple levels of data driver circuits, thereby reducing the circuit area of these data driver circuits in the non-display area, enabling application in displays with narrow bezels.

To make the above features and advantages of the present invention more clearly understood, the following examples are given and described in detail with reference to the accompanying drawings.

10, 50: Display

10a, 20a, 50a: Pixel driver circuit

10b: Pixel array

100_1~100_N1, 200: Data drive circuit

110, 210, 310, 410: Horizontal shift registers

110_R1~110_RN3, 210_R1~210_R4, 310_R1~310_R4, 410_R1~410_R8: Horizontal shift register block

120_1~120_N2, 220_1~220_8: Data processing circuits

120_R1~120_RN4, 220_R1~220_R4: Data processing circuit blocks

230_1~230_4: Gate drive circuit

311-314, 314a-314b, 411-415: Buffers

A1: Non-display area

AA: Display Area

CK: Clock signal

D1: First Distance

D2: Second distance

DLH[n]: control signal

GL1~GL4: Gate lines

GLD[n]: Gate control signal

HSR[n]: control signal

HSR[n+1]: post-stage control signal

HSR[n-1]: pre-stage control signal

HSR_R1~HSR_R4, HSR_R1~HSR_R8: Partial circuit

INV1~INV2: Buffer

LG1: Anti-AND Gate

LG2: Anti-OR Gate

SB1~SB2, SB1~SB4: Side

SCS: reverse control signal

SW1~SW4: Switches

X: First direction

XCK: reverse clock signal

Y: Second direction

Figure 1A is a block diagram of a display according to an embodiment of the present invention.

Figure 1B is a block diagram of the pixel driver circuit according to the embodiment of Figure 1A of the present invention.

Figure 2 is a block diagram of a pixel driver circuit according to another embodiment of the present invention.

FIG3 is a circuit diagram of the horizontal shift register in the n-th stage data driver circuit shown in FIG2 according to the embodiment of the present invention.

FIG4 is a circuit diagram of the horizontal shift register in the n-th stage data driver circuit shown in FIG2 according to the embodiment of the present invention.

Figure 5 is a schematic diagram of a display according to an embodiment of the present invention.

Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Component numbers used in the following description will be used to identify identical or similar components when the same component numbers appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are merely examples within the scope of the present invention's patent application.

Figure 1A is a block diagram of a display according to one embodiment of the present invention. Referring to Figure 1A , display 10 may be a liquid crystal display (LCD), a light-emitting diode (LED), an organic light-emitting diode (OLED), or other display that provides display functionality. Display 10 includes a pixel driver circuit 10a and a pixel array 10b. Pixel driver circuit 10a is coupled to pixel array 10b and is used to drive pixel array 10b.

In this embodiment, the pixel driver circuit 10a is disposed in the non-display area A1 of the display 10. The pixel array 10b is disposed in the display area AA of the display. The display area AA is a non-rectangular polygon, and may be, for example, a polygon that is approximately circular. The non-display area A1 is adjacent to the display area AA of the display 10. The non-display area A1 has multiple sides (e.g., sides SB1 and SB2). These sides are adjacent to (or overlap) the multiple sides corresponding to the display area AA.

Referring also to FIG. 1B , FIG. 1B is a block diagram of a pixel driver circuit according to the embodiment shown in FIG. 1A of the present invention. The pixel driver circuit 10a includes multiple stages of data driver circuits 100_1 through 100_N1, where N1 is a positive integer greater than 1. These data driver circuits 100_1 through 100_N1 are disposed in the non-display area A1 and are used to drive corresponding pixel circuits in the pixel array 10b. In this embodiment, the data driver circuits may also be referred to as source driver circuits. The multiple stages of data driver circuits 100_1 through 100_N1 have the same circuit architecture.

In this embodiment, the n-th stage data driver circuit 100_1 among the multi-stage data driver circuits 100_1 to 100_N1 includes a horizontal shift register (HSR) 110 and multi-stage data processing circuits 120_1 to 120_N2, where n is a positive integer and N2 is a positive integer greater than 1.

In this embodiment, the horizontal shift register 110 is coupled to the multi-stage data processing circuits 120_1 through 120_N2. The horizontal shift register 110 is used to temporarily store the display data corresponding to the pixel array 10b and provide the aforementioned display data to the corresponding multi-stage data processing circuits 120_1 through 120_N2.

In this embodiment, multiple stages of data processing circuits 120_1-120_N2 are coupled to multiple pixel circuits in the pixel array 10b. These pixel circuits are arranged in consecutive rows and columns. Each data processing circuit 120_1-120_N2 is used to temporarily store display data stored in the horizontal shift register 110. Each data processing circuit 120_1-120_N2 is coupled to multiple pixel circuits arranged in the same corresponding row and is also used to provide display data to the corresponding pixel circuits.

In this embodiment, the horizontal shift register 110 is divided into a plurality of horizontal shift register blocks 110_R1 through 110_RN3 based on a preset number, where RN3 is a positive integer greater than 1. Furthermore, the multi-stage data processing circuits 120_1 through 120_N2 are divided into a plurality of data processing circuit blocks 120_R1 through 120_RN4 based on a preset number, where RN4 is a positive integer greater than 1 and may be the same as RN3. Each horizontal shift register block 110_R1 through 110_RN3 is coupled to a corresponding one of the data processing circuit blocks 120_R1 through 120_RN4. Each horizontal shift register block 110_R1 to 110_RN3 is disposed on each of the multiple sides of the non-display area A1.

For example, horizontal shift register block 110_R1 is coupled to a corresponding data processing circuit block 120_R1 and is disposed on side SB1 of non-display area A1. Horizontal shift register block 110_RN3 is coupled to a corresponding data processing circuit block 120_RN4 and is disposed on another side (not shown) of non-display area A1.

In this embodiment, the preset number can be set to various values based on the design requirements of display 10. For example, when the narrow bezel used in display 10 is narrower, the preset number has a larger value.

That is, based on a preset number, the horizontal shift register 110 is divided into different circuit blocks 110_R1-10_RN3, and the multi-stage data processing circuits 120_1-120_N2 are further divided into multiple circuit blocks 120_R1-120_RN4. These different circuit blocks 110_R1-10_RN3 and their coupled circuit blocks 120_R1-120_RN4 are sequentially arranged on different sides of the non-display area A1.

It is worth noting that, based on a preset number, the horizontal shift register 110 and the multi-stage data processing circuits 120_1 to 120_N2 are respectively divided into corresponding circuit blocks 110_R1 to 110_RN3 and 120_R1 to 120_RN4, so that the circuit blocks 110_R1 and 120_R1 can be arranged as a set of units on a corresponding single side SB1, and so on.

Therefore, the pixel driver circuit 10a can reduce the arrangement pitch between the multi-level data driver circuits 100_1-100_N1. This arrangement pitch can, for example, be reduced to a multiple of the aforementioned arrangement unit (e.g., the pitch between circuit blocks 110_R1 and 120_R1 and circuit blocks 110_R2 and 120_R2). In this way, the pixel driver circuit 10a can reduce the circuit area of the multi-level data driver circuits 100-100_N1 in the non-display area A1 and simultaneously reduce the blank layout area between the multi-level data driver circuits 100_1-100_N1 and the display area AA, thereby enabling narrow bezel applications.

Figure 2 is a block diagram of a pixel driver circuit according to another embodiment of the present invention. Referring to Figure 2 , pixel driver circuit 20a includes multiple stages of data driver circuits, wherein the n-th stage data driver circuit 200 includes a horizontal shift register 210 and multiple stages of data processing circuits 220_1 through 220_8. The number of these data processing circuits 220_1 through 220_8 is for illustrative purposes only. The horizontal shift register 210 and multiple stages of data processing circuits 220_1 through 220_8 can be similarly described with reference to the description of the n-th stage data driver circuit 100.

In this embodiment, the horizontal shift register 210 is used to output a multi-stage control signal HSR[n] to a multi-stage data processing circuit 220_1 to 220_8.

In this embodiment, the multi-stage data processing circuits 220_1-220_8 are controlled by a multi-stage control signal HSR[n] to temporarily store identification signals (SID signals) stage by stage based on the multi-stage control signal HSR[n] and output the temporarily stored SID signals to corresponding pixel circuits based on the multi-stage control signals (including the control signal DLH[n]). In this embodiment, each stage of the data processing circuits 220_1-220_8 can be implemented, for example, as a data latch.

In the embodiment shown in FIG. 2 , the pixel driver circuit 20 a further includes multiple stages of gate driver circuits (e.g., multiple stages of gate driver circuits 230_1 through 230_4). These multiple stages of gate driver circuits 230_1 through 230_4 are coupled to multiple stages of data driver circuits (including the nth stage of data driver circuit 200) within the pixel driver circuit 20 a. These gate driver circuits 230_1 through 230_4 are sequentially arranged in the non-display area A1 along multiple sides (e.g., sides SB1 through SB4) of the non-display area A1. Each gate driver circuit 230_1-230_4 is used to control the conduction of multiple gate lines GL1-GL4 according to the corresponding gate control signal GLD[n]. These gate lines GL1-GL4 are also coupled to the corresponding pixel circuits in the pixel array 10b.

In this embodiment, the default number of data driver circuits used to split each level is greater than one. Furthermore, the default number is the number of multi-level gate driver circuits 230_1 to 230_4 coupled to the n-th level data driver circuit 200 (e.g., four). In other words, based on design requirements, each level of data driver circuit (e.g., the n-th level data driver circuit 200) is configured to couple four multi-level gate driver circuits 230_1 to 230_4.

Under this design requirement, the horizontal shift register 210 and the multi-stage data processing circuits 220_1-220_8 in the n-th stage data driver circuit 200 are divided into corresponding circuit blocks (i.e., HSR_R1 through HSR_R4) 210_R1-210_R4 and circuit blocks (i.e., DLH_R1 through DLH_R4) 220_R1-220_R4, respectively, based on a preset number (e.g., 4). Consequently, the multi-stage gate driver circuits 230_1-230_4 and the corresponding circuit blocks 210_R1-210_R4 and 220_R1-220_R4 are sequentially arranged on the sides SB1-SB4 of the non-display area A1.

Specifically, based on a preset number (e.g., 4), the horizontal shift register 210 is divided into multiple horizontal shift register blocks 210_R1 to 210_R4, and the multi-stage data processing circuits 220_1 to 220_8 are divided into multiple data processing circuit blocks 220_R1 to 220_R4.

It should be noted that each data processing circuit block 220_R1-220_R4 includes m of the multiple stages of data processing circuits 220_1-220_8. m is a positive integer and is less than the total number of the multiple stages of data processing circuits 220_1-220_8 (i.e., 8). In other words, the multiple stages of data processing circuits 220_1-220_8 are evenly divided into multiple circuit blocks 220_R1-220_R4, where these circuit blocks 220_R1-220_R4 have the same circuit architecture (e.g., m parallel-connected data processing circuits).

In the embodiment of FIG. 2 , m can be, for example, 2. Based on a preset number (e.g., 4), the multi-stage data processing circuits 220_1 through 220_8 are divided into four circuit blocks 220_R1 through 220_R4. In other words, each circuit block 220_R1 through 220_R4 includes two of the multi-stage data processing circuits 220_1 through 220_8. For example, data processing circuit block 220_R1 includes two data processing circuits 220_1 through 220_2, and data processing circuit block 220_R2 includes two data processing circuits 220_3 through 220_4, and so on.

That is, for the n-th stage data driver circuit 200, each quarter of the horizontal shift registers 210 (e.g., circuit block 210_R1) is configured to connect m corresponding data processing circuits (e.g., two stages of data processing circuits 220_1 and 220_2) in series and are all located on the same side (e.g., side SB1).

Furthermore, in the non-display area A1, multiple stages of data driver circuits (including the n-th stage data driver circuit 200) are arranged in a staircase pattern in the first direction X. Specifically, the horizontal shift register block 210_R1 and the corresponding data processing circuit block 220_R1 can be considered as a set of arrangement units and are arranged on the side SB1 along with the corresponding gate driver circuit 230_1. The arrangement units have a first distance D1 in the first direction X and a second distance D2 in the second direction Y.

In this embodiment, the first distance D1 is the required layout length of the data processing circuit block 220_R1 in the first direction X. Since the data processing circuit block 220_R1 includes m (e.g., two) data processing circuits 220_1-220_2, the aforementioned layout length is the pitch between multiple pixel circuits arranged in m (e.g., two) rows. In other words, the first distance D1 can be, for example, the pixel pitch between m (e.g., two) pixel circuits.

Furthermore, the second distance D2 is the required layout height of the horizontal shift register block 210_R1 in the second direction Y. The second distance D2 may be, for example, the pixel pitch between m (e.g., 2) pixel circuits.

It should be noted that because the horizontal shift register 210 and the multi-stage data processing circuits 220_1-220_8 are divided into multiple circuit blocks 210_R1-210_R4 and 220_R1-220_R4, respectively, the arrangement unit of the n-th stage data driver circuit 200 in the first direction X can be reduced from a multiple of eight pixel pitches required for the eight data processing circuits 220_1-220_8 to a multiple of m (e.g., two) pixel pitches, compared to conventional layouts.

For example, horizontal shift register block 210_R2 and its corresponding data processing circuit block 220_R2 are shifted by one arrangement unit relative to circuit blocks 210_R1 and 220_R1, so as to be located on adjacent side SB1 along with the corresponding gate driver circuit 230_2. In other words, relative to circuit blocks 210_R1 and 220_R1, circuit blocks 210_R2 and 220_R2 are shifted by a first distance D1 in the first direction X and a second distance D2 in the second direction Y, and so on.

FIG3 is a circuit diagram of a horizontal shift register in the n-th stage data driver circuit shown in FIG2 according to the embodiment of the present invention. Referring to FIG3 , a horizontal shift register 310 can be implemented in the n-th stage data driver circuit 200 of FIG2 . Based on a preset number (e.g., 4), the horizontal shift register 310 is divided into a plurality of horizontal shift register blocks 310_R1 through 310_R4.

In the embodiment shown in FIG3 , the horizontal shift register 310 includes a first circuit section HSR_R1, a second circuit section HSR_R2, a third circuit section HSR_R3, and a fourth circuit section HSR_R4. These circuit sections HSR_R1 through HSR_R4 belong to different horizontal shift register blocks 310_R1 through 310_R4, respectively.

Specifically, the first circuit HSR_R1 includes a first buffer 311, a second buffer 312, a third buffer 313, a first switch SW1, a second switch SW2, and a third switch SW3. The input of the first buffer 311 receives the pre-stage control signal HSR[n-1]. The output of the first buffer 311 is coupled to the input of the second buffer 312. The second buffer 312 is also coupled to the first switch SW1 to be controlled by the first switch SW1. The first switch SW1 is implemented, for example, as an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET). The control terminal of the first switch SW1 receives the subsequent control signal HSR[n+1] to perform a switching operation according to the subsequent control signal HSR[n+1].

Continuing with the above description, the input end of the third buffer 313 is coupled to the output end of the second buffer 312. The third buffer 313 is also coupled to the second switch SW2 and the third switch SW3 to be controlled by these switches SW2 and SW3. The second switch SW2 is implemented, for example, by a p-type metal-oxide-semiconductor field-effect transistor (NMOSFET). The third switch SW3 is implemented, for example, by an NMOSFET. The control end of the second switch SW2 receives the post-stage control signal HSR[n+1] to perform a switching operation according to the post-stage control signal HSR[n+1]. The control end of the third switch SW3 is coupled to the output end of the first buffer 311 to perform a switching operation according to the output signal of the first buffer 311.

In this embodiment, the second circuit HSR_R2 includes multiple fourth buffers 314 and a fourth switch SW4. These fourth buffers 314 are connected in series. These fourth buffers 314 are coupled to the fourth switch SW4, the output of the second buffer 312, and the output of the third buffer 313, and are controlled by the fourth switch SW4.

Specifically, the plurality of fourth buffers 314 include buffers 314a and 314b. The input of buffer 314a is coupled to the output of the second buffer 312, the input of the third buffer 313, and the fourth switch SW4. The fourth switch SW4 is implemented, for example, as an NMOSFET. The control terminal of the fourth switch SW4 receives the reverse control signal SCS to perform a switching operation based on the reverse control signal SCS. The input of buffer 314b is coupled to the output of buffer 314a and the output of the third buffer 313.

In this embodiment, the third circuit HSR_R2 includes a plurality of logic gates LG1 and LG2. These logic gates LG1 and LG2 are connected in series. These logic gates LG1 and LG2 are coupled to the output terminals of the plurality of fourth buffers 314.

Specifically, the multiple logic gates LG1 and LG2 include a NAND gate (NAND) LG1 and a NOR gate (NOR) LG2. The first input of the NAND gate LG1 receives the clock signal CK. The second input of the NAND gate LG1 is coupled to the outputs of the plurality of fourth buffers 314. The first input of the NOR gate LG2 receives the inverted clock signal XCK. The second input of the NOR gate LG2 is coupled to the output of the NAND gate LG1. The output of the NOR gate LG2 is coupled to the input of the fourth circuit HSR_R2.

In this embodiment, the fourth circuit HSR_R2 includes a plurality of fifth buffers INV1-INV2. These fifth buffers INV1-INV2 are implemented, for example, as inverters. These fifth buffers INV1-INV2 are connected in series. These fifth buffers INV1-INV2 are coupled to the output terminals of a plurality of logic gates LG1-LG2.

Specifically, the plurality of fifth buffers INV1-INV2 include buffers INV1 and INV2. The input of buffer INV1 is coupled to the output of NOR gate LG2. The output of buffer INV1 is coupled to the input of buffer INV2. The output of buffer INV2 provides a control signal HSR[n] to the multi-stage data processing circuits 220_1-220_8.

FIG4 is a circuit diagram of a horizontal shift register in the n-stage data driver circuit shown in FIG2 according to the embodiment of the present invention. Referring to FIG4 , a horizontal shift register 410 can be implemented in the n-stage data driver circuit 200 of FIG2 . Based on a preset number (e.g., 8), the horizontal shift register 410 is divided into a plurality of horizontal shift register blocks 410_R1 through 410_R8. Correspondingly, based on a preset number (e.g., 8), the multi-stage data processing circuits 220_1 through 220_8 in the n-stage data driver circuit 200 are divided into eight data processing circuit blocks. In other words, each data processing circuit block includes m (e.g., 1) of the multi-stage data processing circuits 220_1 through 220_8.

It should be noted that because the horizontal shift register 210 and the multi-stage data processing circuits 220_1-220_8 are divided into eight horizontal shift register blocks 210_R1-210_R8 and eight data processing circuit blocks, respectively, the arrangement unit of the n-th stage data driver circuit 200 in the first direction X can be reduced from a multiple of eight pixel pitches required for the eight data processing circuits 220_1-220_8 to a multiple of m (e.g., one) pixel pitches, compared to conventional layouts.

In the embodiment shown in FIG4 , the horizontal shift register 410 includes a first circuit section HSR_R1, a second circuit section HSR_R2, a third circuit section HSR_R3, a fourth circuit section HSR_R4, a fifth circuit section HSR_R5, a sixth circuit section HSR_R6, a seventh circuit section HSR_R7, and an eighth circuit section HSR_R8. These circuit sections HSR_R1 through HSR_R8 belong to different horizontal shift register blocks 410_R1 through 410_R8, respectively. The horizontal shift register 410 has the same circuit architecture as the horizontal shift register 310 shown in FIG3 .

Specifically, the first circuit HSR_R1 includes a first buffer 411, a second buffer 412, and a first switch SW1. The input of the first buffer 411 receives the front-end control signal HSR[n-1]. The output of the first buffer 411 is coupled to the input of the second buffer 312. The second buffer 412 is also coupled to the first switch SW1. The control terminal of the first switch SW1 receives the rear-end control signal HSR[n+1].

In this embodiment, the second circuit HSR_R2 includes a third buffer 413, a second switch SW2, and a third switch SW3. The input of the third buffer 413 is coupled to the output of the second buffer 412. The third buffer 413 is also coupled to the second switch SW2 and the third switch SW3. The control terminal of the second switch SW2 receives the post-stage control signal HSR[n+1]. The control terminal of the third switch SW3 is coupled to the output of the first buffer 411.

In this embodiment, the third circuit HSR_R3 includes a fourth buffer 414 and a fourth switch SW4. The input of the fourth buffer 414 is coupled to the output of the second buffer 412, the input of the third buffer 413, and the fourth switch SW4. The control terminal of the fourth switch SW4 receives the reverse control signal SCS.

In this embodiment, the fourth partial circuit HSR_R4 includes a fifth buffer 415. The input terminal of the fifth buffer 415 is coupled to the output terminal of the fourth buffer 414 and the output terminal of the third buffer 413.

In this embodiment, the fifth circuit HSR_R5 includes a first logic gate LG1 (e.g., a NAND gate). A first input terminal of the first logic gate LG1 receives a clock signal CK. A second input terminal of the first logic gate LG1 is coupled to the output terminal of the fifth buffer 415.

In this embodiment, the sixth circuit HSR_R6 includes a second logic gate LG2 (e.g., a NOR gate). A first input terminal of the second logic gate LG2 receives a negative clock signal XCK. A second input terminal of the second logic gate LG2 is coupled to an output terminal of the first logic gate LG1.

In this embodiment, the seventh circuit HSR_R7 includes a sixth buffer INV1. An input terminal of the sixth buffer INV1 is coupled to an output terminal of the second logic gate LG2.

In this embodiment, the eighth circuit HSR_R8 includes a seventh buffer INV2. The input of the seventh buffer INV2 is coupled to the output of the sixth buffer INV1. The output of the seventh buffer INV2 provides a control signal HSR[n] to the multi-stage data processing circuits 220_1 to 220_8.

FIG5 is a schematic diagram of a display according to an embodiment of the present invention. Referring to FIG5 , display 50 includes a pixel driver circuit 50a and a pixel array (not shown). The pixel driver circuit 50a and the pixel array can be similarly described with reference to the description of display 10.

In this embodiment, the display area AA is a non-rectangular polygon, and may be, for example, a polygon that is approximately circular. The non-display area A1 is adjacent to the display area AA. The non-display area A1 has multiple sides adjacent to (or overlapping with) the display area AA.

In this embodiment, based on the split circuit blocks, the multi-level data driver circuits in pixel driver circuit 50a are sequentially arranged with a reduced spacing within non-display area A1. This allows display 50 to be implemented as a narrow-frame, circular display.

In summary, the pixel driver circuit and display of the present invention are suitable for narrow-bezel, circular displays. Based on a preset number, they can reduce the spacing between horizontal shift registers and multi-stage data processing circuits in each stage of the data driver circuit, thereby reducing the spacing between the multi-stage data driver circuits. This reduces the circuit area of the multi-stage data driver circuits in the non-display area and the blank layout area between the multi-stage data driver circuits and the display area.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make minor modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

10a: Pixel driver circuit

100_1~100_N1: Data drive circuit

110: Horizontal shift register

110_R1~110_RN3: Horizontal shift register block

120_1~120_N2: Data processing circuits

120_R1~120_RN4: Data processing circuit block

Claims (10)

A pixel driver circuit, suitable for use in a display, comprises: Multi-stage data driver circuits disposed in a non-display area of the display, wherein the nth stage of the data driver circuits comprises: A horizontal shift register divided into a plurality of horizontal shift register blocks based on a preset number; and Multi-stage data processing circuits divided into a plurality of data processing circuit blocks based on the preset number, wherein each horizontal shift register block is coupled to a corresponding one of the data processing circuit blocks and disposed on each of a plurality of sides of the non-display area, where n is a positive integer. The pixel driver circuit as described in claim 1, wherein each of the data processing circuit blocks has m of the multi-stage data processing circuits, where m is a positive integer. The pixel driver circuit of claim 1 further comprises: A multi-stage gate driver circuit coupled to the data driver circuits and arranged sequentially based on the sides so as to be disposed in the non-display area. The pixel driver circuit as described in claim 3, wherein the preset number is the number of the gate driver circuits coupled to the n-th stage data driver circuit, and the preset number is greater than 1. The pixel driver circuit as described in claim 1, wherein in the non-display area, the data driver circuits are arranged in a staircase shape in a first direction. The pixel driver circuit of claim 1, wherein the horizontal shift register comprises: a first circuit portion including a first buffer, a second buffer, a third buffer, a first switch, a second switch, and a third switch, wherein the first switch is coupled to the second buffer, the second switch and the third switch are coupled to the third buffer, an output terminal of the first buffer is coupled to an input terminal of the second buffer and a control terminal of the third switch, and an output terminal of the second buffer is coupled to an input terminal of the third buffer; A second circuit section includes a plurality of fourth buffers and a fourth switch, wherein the fourth buffers are connected in series and coupled to the fourth switch, the output of the second buffer, and the output of the third buffer; A third circuit section includes a plurality of logic gates, wherein the logic gates are connected in series and coupled to the outputs of the fourth buffers; and A fourth circuit section includes a plurality of fifth buffers, wherein the fifth buffers are connected in series and coupled to the outputs of the logic gates. The first circuit section, the second circuit section, the third circuit section, and the fourth circuit section each belong to a different horizontal shift register block. The pixel driver circuit of claim 6, wherein the logic gates include an NAND gate and an NOR gate, wherein multiple input terminals of the NAND gate receive a clock signal and are coupled to the output terminals of the fourth buffers, multiple input terminals of the NOR gate receive an inverse clock signal and are coupled to the output terminal of the NAND gate, and the output terminal of the NOR gate is coupled to the input terminals of the fifth buffers. The pixel driver circuit of claim 1, wherein the horizontal shift register comprises: a first circuit portion comprising a first buffer, a second buffer, and a first switch, wherein the first switch is coupled to the second buffer, and an output of the first buffer is coupled to an input of the second buffer; a second circuit portion comprising a third buffer, a second switch, and a third switch, wherein the second switch and the third switch are coupled to the third buffer, a control terminal of the third switch is coupled to the output of the first buffer, and an input of the third buffer is coupled to the output of the second buffer; A third circuit section includes a fourth buffer and a fourth switch, wherein the fourth switch is coupled to the fourth buffer, and an input of the fourth buffer is coupled to the output of the second buffer; A fourth circuit section includes a fifth buffer, wherein an input of the fifth buffer is coupled to the output of the fourth buffer and the output of the third buffer; A fifth circuit section includes a first logic gate, wherein a plurality of inputs of the first logic gate receive a clock signal and are coupled to the output of the fifth buffer; A sixth circuit section includes a second logic gate, wherein multiple input terminals of the second logic gate receive an inverting clock signal and are coupled to the output terminal of the first logic gate; A seventh circuit section includes a sixth buffer, wherein the input terminals of the sixth buffer are coupled to the output terminal of the second logic gate; and An eighth circuit section includes a seventh buffer, wherein the input terminals of the seventh buffer are coupled to the output terminal of the sixth buffer. The first, second, third, fourth, fifth, sixth, seventh, and eighth circuit sections belong to different horizontal shift register blocks. A display comprises: A pixel array disposed in a display area; and The pixel driver circuit of claim 1, coupled to the pixel array, disposed in a non-display area adjacent to the display area, and configured to drive the pixel array. A display as described in claim 9, wherein the display area is a non-rectangular polygon.