TWI891022B - Wiring carrier, electronic package and manufacturing method of electronic structure - Google Patents

Abstract

A wiring carrier is suitable for mounting a plurality of chip components. The wiring carrier includes a plurality of wiring sub-boards, an encapsulant layer and a redistribution circuit structure. The encapsulant layer covers the wiring sub-boards and fills the gap between the wiring sub-boards. One side of the wiring layer exposes one side of each of the wiring sub-boards. The redistribution wiring structure is arranged on the side of the wiring layer farther away from the wiring sub-boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the wiring sub-boards through the redistribution wiring structure. An electronic package and a method of manufacturing an electronic structure are also presented herein.

Description

Circuit carrier, electronic package and electronic structure manufacturing method

The present invention relates to an electronic component, and more particularly to a method for manufacturing a circuit carrier, an electronic package, and an electronic structure.

Circuit carriers used in chip packaging secure integrated circuit (IC) chips and serve as a medium for electrical connections to other electronic components. Circuit carriers are categorized as either cored or coreless, depending on whether they have a dielectric core. Multi-chip packaging requires large circuit carriers. However, large circuit carriers have lower layout utilization and yield rates during mass production, increasing production costs.

The present invention provides a circuit carrier board for reducing production costs.

The present invention provides an electronic package for reducing production costs.

The present invention provides a method for manufacturing an electronic structure, which is used to manufacture the electronic structure.

One embodiment of the present invention provides a circuit carrier suitable for mounting multiple chip components. The circuit carrier includes multiple circuit daughter boards, an encapsulation layer, and a redistribution wiring structure. The encapsulation layer covers the circuit daughter boards and fills the gaps between the circuit daughter boards. One side of the encapsulation layer exposes one side of each of the circuit daughter boards. The redistribution wiring structure is configured on a side of the encapsulation layer farther from the circuit daughter boards and is suitable for mounting the chip components thereon, such that the chip components are electrically connected to the circuit daughter boards via the redistribution wiring structure.

An electronic package according to one embodiment of the present invention includes a plurality of chip components and a circuit carrier. The circuit carrier includes a plurality of circuit daughter boards, an encapsulation layer, and a redistribution wiring structure. The encapsulation layer covers the circuit daughter boards and fills the gaps between the circuit daughter boards. One side of the encapsulation layer exposes one side of each of the circuit daughter boards. The redistribution wiring structure is configured on a side of the encapsulation layer farther from the circuit daughter boards and allows the chip components to be mounted thereon, so that the chip components are electrically connected to the circuit daughter boards via the redistribution wiring structure.

A method for fabricating an electronic structure according to an embodiment of the present invention includes the following steps: securing a plurality of circuit daughter boards to a temporary carrier via a temporary bonding layer; forming an encapsulation layer covering the temporary bonding layer and the circuit daughter boards, wherein the encapsulation layer fills the gaps between the circuit daughter boards; and forming a redistribution wiring structure on the encapsulation layer, wherein the redistribution wiring structure electrically connects the circuit daughter boards.

Based on the above, multiple circuit daughter boards are encapsulated with a layer of encapsulant, and a redistribution wiring structure is placed on the encapsulant layer to electrically connect these circuit daughter boards. Compared to the large-scale circuit carrier boards traditionally used for chip packaging, small-sized circuit carrier boards have significantly higher layout utilization and yield. Therefore, in this case, using small-sized circuit carrier boards as circuit daughter boards to construct a large-scale circuit carrier board can also reduce production costs.

Referring to FIG. 1 , in this embodiment, an electronic package 50 includes multiple chip components 51 and a circuit carrier 100. These chip components 51 may be, for example, bare integrated circuit chips or small chip packages (e.g., multi-chip packages, stacked chip packages, chip-scale packages, etc.). These chip components 51 are mounted to the circuit carrier 100, for example, via conductive bumps 53.

In this embodiment, circuit carrier 100 includes multiple circuit daughter boards 110, an encapsulation layer 120, and a redistribution wiring structure 130. The encapsulation layer 120 covers the circuit daughter boards 110 and fills the gaps between them, effectively isolating the circuit daughter boards 110 within the encapsulation layer 120. One side of the encapsulation layer 120 exposes one side of each circuit daughter board 110 for connection to the next-level electronic components (e.g., a motherboard or module board). The redistribution wiring structure 130 is disposed on a side of the encapsulation layer 120 that is farther from the circuit daughter boards 110. The chip components 51 are mounted thereon, allowing the chip components 51 to be electrically connected to the circuit daughter boards 110 via the redistribution wiring structure 130. Because the circuit daughter boards 110 are insulated from one another within the encapsulation layer 120 and cannot be directly electrically connected through the encapsulation layer 120, the circuit daughter boards 110 can be electrically connected to one another via the redistribution wiring structure 130. Furthermore, the circuit daughter boards 110 can be mounted to the next level of electronic components, such as a motherboard or module board, via a plurality of daughter board conductive balls 140.

In this embodiment, each circuit daughterboard 110 may include multiple daughterboard dielectric layers 112, multiple daughterboard patterned conductive layers 114, and multiple daughterboard conductive vias 116. The daughterboard patterned conductive layers 114 alternate with the daughterboard dielectric layers 112. The daughterboard conductive vias 116 connect the daughterboard patterned conductive layers 114, respectively. Furthermore, the redistribution wiring structure 130 may include multiple redistribution dielectric layers 132, multiple redistribution patterned conductive layers 134, and multiple redistribution conductive vias 136. The redistribution patterned conductive layers 134 alternate with the redistribution dielectric layers 132. These redistribution conductive vias 136 are connected to the redistribution patterned conductive layers 134, respectively. In one embodiment, the redistribution wiring structure 130 further includes a redistribution patterned conductive layer 134a, which can directly electrically connect at least two circuit daughter boards 110 to transmit signals. Furthermore, the chip components 51 can also be electrically connected to each other via the redistribution wiring structure 130 to transmit signals.

Referring to Figures 2A, 2B, and 2C, these chip components 51 and these circuit daughter boards 110 are arranged within the scope of the redistribution wiring structure 130. These circuit daughter boards 110 can be rectangular, and their lengths and widths can be equal or unequal. The rectangular dimensions of these circuit daughter boards 110 can vary. These circuit daughter boards 110 can be arranged in a plane array or in a straight line. In addition, some chip components 51 can be located on corresponding circuit daughter boards 110, while some chip components 51 can be located on multiple circuit daughter boards 110 at the same time, that is, they can span at least two adjacent circuit daughter boards 110.

Referring to FIG3 , compared to the electronic package 50 of FIG1 , the circuit daughter board 110a of the electronic package 50 of FIG3 may have a smaller thickness, meaning that there is a difference in thickness between these circuit daughter boards 110 and 110a, whereas there is no difference in thickness between these circuit daughter boards 110 in FIG1 and they may be circuit daughter boards of the same type. Referring to FIG4 , compared to the electronic package 50 of FIG1 , the circuit daughter boards 110 and 110b of the electronic package 50 of FIG4 may be of different types. For example, the circuit daughter board 110 may be a coreless type circuit board, while the circuit daughter board 110b may be a core-equipped type circuit board. In other words, in different embodiments, the thickness or type of the circuit daughter boards may be selected and combined according to different needs.

Please refer to Figure 1 again. In this embodiment, the electronic package 50 may further include a protective cover 52 or other components with heat dissipation function. The protective cover 52 may also have a heat dissipation function. The protective cover 52 is mounted on the redistribution wiring structure 130 and covers these chip components 51. In addition, please refer to Figure 5. Compared with the embodiment of Figure 1, the electronic package 50 of Figure 6 may include a chip encapsulant 52a, and the chip encapsulant 52a is configured on the redistribution wiring structure 130 and fills the gaps between these chip components 51. In one embodiment, the chip encapsulant 52a exposes the back side (non-active side) of these chip components 51. 6 , compared to the embodiment of FIG. 1 , the circuit carrier 100 of the electronic package 50 of FIG. 6 may include a circuit substrate 150. The circuit daughter boards 110 are mounted on the circuit substrate 150. For example, the circuit daughter boards 110 may be mounted on the circuit substrate 150 via a plurality of daughter board conductive balls 140. Furthermore, the circuit substrate 150 may be mounted to a next-level electronic component, such as a motherboard or module board, via a plurality of substrate conductive balls 160.

7A to 7F are used to illustrate a method for manufacturing an electronic structure according to another embodiment of the present invention.

7A , a plurality of circuit daughter boards 110 are fixed to a temporary carrier 204 via a temporary bonding layer 202. In this embodiment, the circuit daughter board 110 has a plurality of conductive pads P. In one embodiment, the conductive pads P are made of copper and include a copper pad at the bottom and a copper column at the top.

Referring to FIG. 7B , an encapsulation layer 120 is formed to cover the temporary bonding layer 202 and the circuit daughter boards 110. The encapsulation layer 120 fills the gaps between the circuit daughter boards 110. In other words, the circuit daughter boards 110 in the encapsulation layer 120 are insulated from each other and cannot be directly electrically connected at the encapsulation layer 120. In this embodiment, the encapsulation layer 120 also covers the conductive pads P.

7C , a portion of the encapsulant layer 120 is removed to expose a portion of each of the conductive pads P, such as the top surface of the conductive pads P. This step can flatten the surface of the electronic structure to facilitate subsequent steps.

Referring to FIG. 7D , a redistribution wiring structure 130 is formed on the encapsulant layer 120 , where the redistribution wiring structure 130 electrically connects to the circuit daughter boards 110 . In this embodiment, a plurality of redistribution conductive vias 136 and a redistribution patterned conductive layer 134 are formed on the top surface of the conductive pads P to electrically connect to the circuit daughter boards 110 . In one embodiment, the redistribution wiring structure 130 further includes a redistribution patterned conductive layer 134a that can directly electrically connect to at least two circuit daughter boards 110 . Furthermore, pre-bonding pads 53a can be formed on the redistribution patterned conductive layer 134 of the redistribution wiring structure 130 , which can later be used to connect to other components. In another embodiment (not shown), the temporary bonding layer 202 and the temporary carrier 204 may be removed to form the circuit carrier 100 of Figure 8. Subsequently, the circuit daughter boards 110 may be mounted on the circuit substrate 150 of Figure 6 to form the circuit carrier 100 of Figure 9.

Referring to FIG7E , a plurality of chip components 51 are mounted on the redistribution wiring structure 130 so that the chip components 51 are electrically connected to the circuit daughter boards 110 via the redistribution wiring structure 130. Furthermore, the chip components 51 can also be electrically connected to each other via the redistribution wiring structure 130. In this embodiment, the chip components 51 can be connected to the pre-bonded pads 53a of the redistribution wiring structure 130 via a plurality of conductive bumps 53. In another embodiment not shown, a protective cover 52 as shown in FIG1 can be mounted on the redistribution wiring structure 130 of FIG7E to cover the chip components 51. In another embodiment (not shown), a chip encapsulant 52a as shown in FIG. 5 may be formed on the redistribution wiring structure 130 in FIG. 7E to cover the chip components 51 and expose the back surfaces of the chip components 51.

7F , the temporary bonding layer 202 and the temporary carrier 204 of FIG. 7E are removed to expose the circuit daughter boards 110. In another embodiment (not shown), the circuit daughter boards 110 may be mounted on the circuit substrate 150 of FIG. 6 .

In summary, multiple circuit daughter boards are encapsulated with a layer of encapsulant, and a redistribution wiring structure is placed on the encapsulant to electrically connect these circuit daughter boards. Compared to the low yield of large-scale circuit carrier boards traditionally used for chip packaging, small-scale circuit carrier boards have significantly higher layout utilization and yield. Therefore, in this case, small-scale circuit carrier boards are used as circuit daughter boards to construct a large-scale circuit carrier board, which can reduce production costs.

50: Electronic package 51: Chip component 52: Protective cover 52a: Chip encapsulation 53: Conductive bumps 53a: Pre-pads 100: Circuit carrier 110, 110a, 110b: Circuit daughterboard 112: Daughterboard dielectric layer 114: Daughterboard patterned conductive layer 116: Daughterboard conductive vias 120: Encapsulation layer 130: Relay wiring structure 132: Relay dielectric layer 134, 134a: Relay patterned conductive layer 136: Relay conductive vias 140: Daughterboard conductive balls 150: Circuit substrate 160: Substrate conductive balls 202: Temporary bonding layer 204: Temporary carrier P: Conductive pad

Figure 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the present invention. Figure 2A is a schematic top view of one arrangement of a chip component, a circuit daughterboard, and a redistribution wiring structure of the electronic package of Figure 1. Figure 2B is a schematic top view of another arrangement of a chip component, a circuit daughterboard, and a redistribution wiring structure of the electronic package of Figure 1. Figure 2C is a schematic top view of yet another arrangement of a chip component, a circuit daughterboard, and a redistribution wiring structure of the electronic package of Figure 1. Figure 3 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 4 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 5 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 6 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figures 7A to 7F illustrate a method for fabricating an electronic structure according to another embodiment of the present invention. Figure 8 is a schematic cross-sectional view of a circuit carrier according to another embodiment of the present invention. Figure 9 is a schematic cross-sectional view of a circuit carrier according to another embodiment of the present invention.

50: Electronic package

51: Chip components

52: Protective cover

53: Conductive bumps

100: Line carrier board

110: Circuit board

112: Sub-board dielectric layer

114: Daughterboard patterned conductive layer

116: Conductive vias on daughterboard

120: Sealant layer

130: Re-routing wiring structure

132:Redistribution of dielectric layer

134, 134a: Re-patterned conductive layer

136: Re-arrange the conductive vias

140: Sub-board conductive ball

Claims (32)

A circuit carrier suitable for mounting multiple chip components, comprising: a plurality of circuit daughter boards; an encapsulation layer covering the circuit daughter boards and filling gaps between the circuit daughter boards, wherein one side of the encapsulation layer exposes one side of each of the circuit daughter boards; and a redistribution wiring structure seamlessly disposed on a side of the encapsulation layer farther from the circuit daughter boards and suitable for mounting the chip components thereon, such that the chip components are electrically connected to the circuit daughter boards via the redistribution wiring structure. A circuit carrier as described in claim 1, wherein the chip components are electrically connected to each other via the redistribution wiring structure. A circuit carrier as described in claim 1, wherein the circuit daughter boards are electrically connected to each other via the redistribution wiring structure. The circuit carrier as described in claim 3, wherein the redistribution wiring structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit daughter boards. The circuit carrier as described in claim 1, wherein the rectangular sizes of the circuit daughter boards are different. The circuit carrier as described in claim 1, wherein the thicknesses of the circuit daughter boards are different. The circuit carrier as described in claim 1, wherein the circuit daughter boards in the encapsulation layer are insulated from each other. The circuit carrier of claim 1 further comprises: A circuit substrate, the circuit daughter boards being mounted on the circuit substrate to be electrically connected to the circuit substrate. An electronic package includes: a plurality of chip components; and a circuit carrier including: a plurality of circuit daughter boards; an encapsulation layer covering the circuit daughter boards and filling gaps between the circuit daughter boards, wherein one side of the encapsulation layer exposes one side of each of the circuit daughter boards; and a redistribution wiring structure seamlessly disposed on a side of the encapsulation layer farther from the circuit daughter boards and having the chip components mounted thereon, such that the chip components are electrically connected to the circuit daughter boards via the redistribution wiring structure. An electronic package as described in claim 9, wherein the chip components are electrically connected to each other via the redistribution wiring structure. An electronic package as described in claim 9, wherein one of the chip components is a bare chip or a chip package. An electronic package as described in claim 11, wherein the chip components are electrically connected to each other via the redistribution wiring structure. The electronic package of claim 9, wherein the circuit daughter boards are electrically connected to each other via the redistribution wiring structure. The electronic package of claim 13, wherein the redistribution wiring structure comprises a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit daughter boards. The electronic package of claim 9, wherein the rectangular sizes of the circuit daughter boards are different. The electronic package as described in claim 9, wherein the thicknesses of the circuit daughter boards vary. The electronic package as described in claim 9, wherein the circuit daughter boards in the encapsulation layer are insulated from each other. The electronic package of claim 9 further comprises: A protective cover mounted on the redistribution wiring structure and enclosing the chip components. The electronic package as described in claim 18, wherein the protective cover has a heat dissipation function. The electronic package of claim 9 further comprises: A chip encapsulant disposed on the redistribution circuit structure and filling gaps between the chip components. The electronic package of claim 9, wherein the circuit carrier further comprises: A circuit substrate, the circuit daughter boards being mounted on the circuit substrate. A method for fabricating an electronic structure includes: Securing a plurality of circuit daughter boards to a temporary carrier via a temporary bonding layer; Forming an encapsulation layer covering the temporary bonding layer and the circuit daughter boards, wherein the encapsulation layer fills gaps between the circuit daughter boards; and Seamlessly forming a redistribution wiring structure on the encapsulation layer, wherein the redistribution wiring structure electrically connects the circuit daughter boards. The method for manufacturing an electronic structure as described in claim 22, wherein each of the circuit daughter boards has a plurality of conductive pads, and in the step of forming the encapsulation layer, the encapsulation layer covers the conductive pads. The method further comprises: Removing a portion of the encapsulation layer to expose a portion of each of the conductive pads, wherein in the step of forming the redistribution wiring structure, the plurality of redistribution conductive vias and at least one redistribution patterned conductive layer of the redistribution wiring structure are electrically connected to the circuit daughter boards. The method for manufacturing an electronic structure as described in claim 22, wherein the circuit daughter boards in the encapsulation layer are insulated from each other. A method for manufacturing an electronic structure as described in claim 22, wherein the redistribution wiring structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit daughter boards. The method for manufacturing an electronic structure as described in claim 22 further comprises: Mounting a plurality of chip components on the redistribution wiring structure such that the chip components are electrically connected to the circuit daughter boards via the redistribution wiring structure. A method for manufacturing an electronic structure as described in claim 26, wherein the chip components are electrically connected to each other via the redistribution wiring structure. The method for manufacturing the electronic structure of claim 26 further comprises: Installing a protective cover on the redistribution circuit structure to cover the chip components. A method for manufacturing an electronic structure as described in claim 28, wherein the protective cover has a heat dissipation function. The method for manufacturing an electronic structure as described in claim 26 further comprises: Forming a chip sealant on the redistribution circuit structure to fill the gaps between the chip components. The method for fabricating an electronic structure as described in claim 22 further comprises: Removing the temporary bonding layer and the temporary carrier. The method for manufacturing an electronic structure as described in claim 31 further comprises: Mounting the circuit daughter boards on a circuit substrate.