TWI889507B - Memory device, operation method of the same and memory system - Google Patents

Abstract

A memory device is provided in the present disclosure. The memory device comprises a memory array, a voltage generator and an array control circuit. The memory array comprises a first array and a second array. The voltage generator is coupled to the memory array. The array control circuit is coupled to the memory array and the voltage generator, and is configured to: in a programming stage of the memory array, control the voltage generator to generate a first control voltage to the memory array, and generate a temporary address to control the first array to store a storage data and an address data in a first programming step according to the temporary address and the first control voltage; in an idle stage of the memory array, control the voltage generator to generate a second control voltage to the memory array, control the second array to store the storage data in a second programming step according to the address data and the second control voltage, and control the first array to perform an erasing operation. The voltage of the first programming step is greater than the voltage of the second programming step.

Description

Memory device, operation method thereof, and memory system

The present disclosure relates to storage technology of a memory device, and more particularly to a memory device that uses multiple sub-blocks to store/temporarily store data at different stages, an operation method thereof, and a memory system.

With the development of the Internet of Things and 5G technology, the amount of data involved in computing is getting larger and larger, so the storage speed required by memory devices is also gradually increasing. In order to optimize the storage speed of memory devices, in some practices, the writing speed of memory devices is designed by gradually increasing the pulse writing (Incremental Step Pulse Programming, ISPP).

However, the step size of the ISPP of a memory device will affect the distribution of the output voltage of the memory array, and thus affect the reliability of the memory device during operation. This phenomenon also requires the memory device to make a trade-off between the ISPP step and reliability. Therefore, how to reduce the correlation between the ISPP step and reliability is one of the topics in this field.

The present disclosure provides a memory device, including a memory array, a voltage generator and an array control circuit. The memory array includes a first array and a second array. The voltage generator is coupled to the memory array. The array control circuit is coupled to the memory array and the voltage generator, and is used to: in the read and write phase of the memory array, control the voltage generator to generate a first control voltage to the memory array, and generate a temporary address to control the first array to store storage data and address data in a first write step according to the temporary address and the first control voltage; in the idle phase of the memory array, control the voltage generator to generate a second control voltage to the memory array, control the second array to store storage data in a second write step according to the address data and the second control voltage, and control the first array to perform a clear operation. The voltage value of the first writing step is greater than the voltage value of the second writing step.

In some embodiments of the memory device, the memory device further comprises an input circuit coupled to the memory array and the array control circuit for splitting input data into storage data and address data.

In some embodiments of the memory device, the memory device further comprises a detection adjustment circuit coupled to the voltage generator and the array control circuit for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter in the read/write phase and the idle phase.

In some embodiments of the memory device, the memory array is used to generate a plurality of first output voltages based on a first control voltage, the plurality of first output voltages forming a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram. The memory array is used to generate a plurality of second output voltages based on a second control voltage, the plurality of second output voltages forming a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram.

In some embodiments of the memory device, the spacing between two adjacent ones in the first subsets is negatively correlated with the voltage value of the first writing step, and the spacing between two adjacent ones in the second subsets is negatively correlated with the voltage value of the second writing step.

In some embodiments of the memory device, a memory array is divided into a plurality of sub-blocks according to a plurality of word lines, one of the plurality of sub-blocks is used at least partially as a first array, and at least one of the remaining plurality of sub-blocks is used as a second array.

In some embodiments of the memory device, a memory array is divided into a plurality of sub-blocks according to a plurality of word lines, a first block of each of the plurality of sub-blocks is used as a first array, and a second block of each of the plurality of sub-blocks is used as a second array.

In some embodiments of the memory device, the voltage value of the first writing step is between 1 volt and 3 volts.

The present disclosure provides an operation method applicable to a memory device, comprising: receiving storage data and address data through a memory array of the memory device; in the read/write phase of the memory array, activating a voltage generator of the memory device through an array control circuit of the memory device to generate a first control voltage to the memory array; in the read/write phase, generating a temporary address through the array control circuit to control the first array of the memory array according to the temporary address and the first control voltage; The control voltage stores the storage data and the address data in a first write step; in an idle phase of the memory array, the array control circuit activates the voltage generator to generate a second control voltage to the memory array; in the idle phase, the array control circuit controls the second array of the memory array to store the storage data in a second write step according to the address data and the second control voltage; and in the idle phase, the array control circuit controls the first array to perform a clear operation. The voltage value of the first write step is greater than the voltage value of the second write step.

In some embodiments of the operating method, receiving storage data and address data by a memory array of a memory device includes: receiving input data by an input circuit of the memory device; splitting the input data into storage data and address data by the input circuit; and transmitting the storage data and address data to the memory array by the input circuit.

In some embodiments of the operating method, the operating method further includes: in the read-write phase, adjusting the voltage value of the first write step according to at least one adjustment parameter by the detection adjustment circuit of the memory device; and in the idle phase, adjusting the voltage value of the second write step according to at least one adjustment parameter by the detection adjustment circuit.

In some embodiments of the operating method, the operating method further includes: generating a plurality of first output voltages based on a first control voltage by the memory array, wherein the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram; and generating a plurality of second output voltages based on a second control voltage by the memory array, wherein the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram.

In some embodiments of the method of operation, the spacing between two adjacent ones in the plurality of first subsets is negatively correlated with the voltage value of the first writing step, and the spacing between two adjacent ones in the plurality of second subsets is negatively correlated with the voltage value of the second writing step.

In some embodiments of the operating method, the operating method further includes: dividing a memory array into a plurality of sub-blocks by a plurality of word lines of the memory device; configuring at least partially one of the plurality of sub-blocks as a first array by an array control circuit; and configuring at least one of the remaining plurality of sub-blocks as a second array by the array control circuit.

In some embodiments of the operating method, the operating method further includes: dividing a memory array into a plurality of sub-blocks by a plurality of word lines of the memory device; configuring a first block of each of the plurality of sub-blocks into a first array by an array control circuit; and configuring a second block of each of the plurality of sub-blocks into a second array by the array control circuit.

In some embodiments of the operating method, the voltage value of the first writing step is between 1 volt and 3 volts.

The present disclosure provides a memory system, comprising a plurality of memory devices. Each of the plurality of memory devices comprises a memory array, a voltage generator, and an array control circuit. The voltage generator is coupled to the memory array. The array control circuit is coupled to the memory array and the voltage generator. The memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array. In the read/write phase of the memory system, the array control circuit of the at least one first memory device is used to control the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and to generate a temporary address to the first array, so as to control the first array to store storage data and address data in a first write step according to the temporary address and the first control voltage. In the read/write phase of the memory system, the array control circuit of the at least one second memory device is used to control the voltage generator of the at least one second memory device to generate a second control voltage to the second array, so as to control the second array to store storage data in a second write step according to address data and the second control voltage, and the array control circuit of the at least one first memory device is used to control the first array to perform a clear operation. The voltage value of the first write step is greater than the voltage value of the second write step.

In some embodiments of the memory system, each of the plurality of memory devices further comprises an input circuit coupled to the memory array and the array control circuit for splitting input data into storage data and address data.

In some embodiments of the memory system, each of the plurality of memory devices further comprises a detection adjustment circuit coupled to the voltage generator and the array control circuit for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter in the read/write phase and the idle phase.

In some embodiments of the memory system, the memory array is used to generate a plurality of first output voltages based on a first control voltage, and the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram. The memory array is used to generate a plurality of second output voltages based on a second control voltage, and the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram. The spacing between two adjacent ones in the plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between two adjacent ones in the plurality of second subsets is negatively correlated with the voltage value of the second write step.

Through the memory device, its operation method and memory system of the disclosed document, the memory array responsible for executing temporary data and storing data can be divided, and ISPP can be executed with different step sizes, thereby effectively improving the speed of storing data under the condition of maintaining reliability.

The following will be used in conjunction with the relevant drawings to illustrate the embodiments of the present disclosure. In the drawings, the same reference numerals represent the same or similar elements or method flows.

In this disclosure document, when an element is referred to as "connected", it may refer to "electrically connected" or "optically connected", and when an element is referred to as "coupled", it may refer to "electrically coupled" or "optically coupled". "Connected" or "coupled" may also be used to indicate the coordinated operation or interaction between two or more elements. Unless the text specifically limits the articles, "one" and "the" may refer to one or more. It will be further understood that the words "include", "including", "have" and similar words used herein specify the features, regions, integers, steps, operations, elements and/or components described therein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components and/or groups thereof described therein or in addition.

FIG. 1 is a functional block diagram of a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 includes an input circuit 110, a memory array 120, a voltage generator 130, a logic circuit 140, an array control circuit 150, and a detection adjustment circuit 160.

The input circuit 110 is coupled to the memory array 120 and the array control circuit 150 to receive input data IN, split the input data IN into storage data DATA and address data ADD, and transmit the split storage data DATA and address data ADD to the memory array 120. In some embodiments, after receiving the input data IN, the input circuit 110 transmits a signal to the array control circuit 150 to instruct the array control circuit 150 to perform a corresponding operation (which will be described in detail in the following paragraphs).

The memory array 120 is coupled to the input circuit 110, the voltage generator 130 and the array control circuit 150, and is used to receive the storage data DATA and the address data ADD from the input circuit 110, receive the control voltages V1 and V2 from the voltage generator 130, receive the temporary address (not shown) from the array control circuit 150, and temporarily store and read the storage data DATA according to the address data ADD, the control voltages V1 and V2 and the temporary address.

In some embodiments, the memory array 120 can be implemented by a two-dimensional memory array, a three-dimensional memory array, or a combination thereof. In addition, it should be noted that in some embodiments, the memory array 120 further includes a word line decoder and a bit line decoder. For the sake of simplicity of the diagram, these components are omitted in FIG. 1.

In some embodiments, the memory array 120 includes a first array T1 and a second array T2 for temporarily storing/storing storage data DATA in different operation phases of the memory array 120 .

In detail, first, the memory array 120 is used to perform incremental step pulse programming (ISPP) based on a first write step in the read/write phase to temporarily store the storage data DATA in the first array T1, so that the first array T1 is used as a buffer; then, when the memory array 120 enters the idle phase, the memory array 120 performs ISPP based on a second write step to store (i.e., transfer) the storage data DATA temporarily stored in the first array T1 to the second array T2, so that the second array T2 operates in the background. In addition, the memory array 120 will also clear the storage data DATA temporarily stored in the first array T1. In some embodiments, the first write step and the second write step are voltage values of specific magnitudes.

The voltage generator 130 is coupled to the memory array 120 , the logic circuit 140 , the array control circuit 150 , and the detection and adjustment circuit 160 , and is used to generate control voltages V1 and V2 to the memory array 120 based on the control of the logic circuit 140 , the array control circuit 150 , and the detection and adjustment circuit 160 .

The logic circuit 140 is coupled to the voltage generator 130 , the array control circuit 150 and the detection and adjustment circuit 160 , and is used to control the magnitude of the voltage generated by the voltage generator 130 based on activation of the array control circuit 150 and adjustment of the detection and adjustment circuit 160 .

The array control circuit 150 is coupled to the input circuit 110, the memory array 120, the voltage generator 130, the logic circuit 140 and the detection adjustment circuit 160, and is used to receive a signal from the input circuit 110 to generate a temporary address, and to activate the voltage generator 130 and the logic circuit 140 to control the voltage generator 130 to generate a voltage. In some embodiments not shown, the array control circuit 150 can be disposed in the logic circuit 140.

The detection and adjustment circuit 160 is coupled to the voltage generator 130, the logic circuit 140 and the array control circuit 150 to detect adjustment parameters (e.g., temperature, pressure, number of use cycles, interference during reading, etc.) of the memory device 100, and adjust the step size of the memory array 120 when performing incremental step pulse programming (ISPP) according to these adjustment parameters. In some embodiments, the detection and adjustment circuit 160 can be omitted.

In some embodiments, the classification of the data stored in the memory array 120 can be distinguished by its output voltage. In other words, the voltage output by the memory array 120 can be grouped to correspond to different data. FIG. 2 is a schematic diagram of the output voltage Vt-quantity of the subset G1~G4 of the output voltage Vt of the memory array 120 according to some embodiments of the present disclosure.

First, please see the upper part of FIG. 2. In some embodiments, by counting the types and quantities of the output voltage Vt of the memory array 120, the output voltage Vt can be divided into multiple non-overlapping subsets (e.g., subsets G1-G4), and each subset corresponds to a type of data. Therefore, the subsets G1-G4 in FIG. 2 can be used to distinguish four types of data.

However, the output voltage Vt may change its distribution state due to various factors (e.g., an increase in device temperature, an increase in the number of use cycles, interference during reading, etc.). Specifically, please see the lower half of Figure 2. Under the influence of the above factors, the output voltage Vt of the memory array 120 will gradually become dispersed, that is, the width of the subsets G1 to G4 will increase. As the width of each subset increases, the distance between adjacent subsets will decrease (e.g., from the distance W1 to the distance W2). When adjacent subsets overlap, the memory device 100 may experience data resolution errors because the same output voltage Vt may correspond to two subsets.

In order to avoid overlapping of adjacent subsets under the influence of the above factors, a larger distance between subsets is required. In some embodiments, the step size of the memory array 120 when performing the step-by-step pulse programming (ISPP) is negatively correlated with the distance between multiple subsets of the output voltage Vt. In other words, the smaller the step size of the ISPP, the larger the distance between adjacent subsets, and the higher the reliability of the memory device.

FIG. 3 is a diagram showing the relationship between adjustment parameters, incremental pulse write (ISPP) size, and total execution time according to some embodiments of the present disclosure. As shown in FIG. 3, the step size of ISPP can be adjusted along with the adjustment parameters (e.g., the aforementioned device temperature, number of use cycles, interference during reading, etc.). However, when the step size of ISPP is reduced, the time required to complete ISPP will increase, thereby lengthening the total execution time of the memory device.

In order to optimize the relationship between the ISPP step size (ie, reliability) and the execution efficiency of the memory device, the memory device 100 disclosed in this disclosure divides the memory array 120 into two different arrays and executes ISPP with different step sizes to achieve improved benefits.

FIG. 4 is a flow chart of a method 400 for operating a memory device according to some embodiments of the present disclosure. In some embodiments, the method 400 is applicable to a memory device (e.g., the memory device 100 of FIG. 1 ), and includes steps S410, S420, S430, S440, S450, S455, S460, S470, S480, and S490.

In step S410, input data is received by an input circuit (e.g., input circuit 110 of FIG. 1), the input data is split into storage data and address data and transmitted to a memory array (e.g., memory array 120 of FIG. 1), and then a signal is transmitted to an array control circuit (e.g., array control circuit 150 of FIG. 1). Then, step S420 is executed.

In step S420, the array control circuit receives a signal from the input circuit and generates a temporary address to the memory array. Then, step S430 is executed.

In step S430, at least one adjustment parameter (e.g., temperature, pressure, number of use cycles, interference during reading, etc.) is detected by a detection adjustment circuit (e.g., detection adjustment circuit 160 of FIG. 1 ), and the voltage value of the first writing step is adjusted according to the detected adjustment parameter. Then, step S440 is executed.

In step S440, the array control circuit activates the voltage generator (eg, the voltage generator 130 in FIG. 1) and the logic circuit so that the voltage generator generates a first control voltage (eg, the control voltage V1 in FIG. 1) to the memory array. Then, step S450 is executed.

In step S450, the first array of the memory array (e.g., the first array T1 of FIG. 1 ) performs ISPP in a first write step according to the temporary address and the first control voltage to temporarily store the storage data and the address data. Then, step S455 is performed. In some embodiments, the phase from step S410 to step S450 can be referred to as the read-write phase of the memory array.

In step S455, the array control circuit determines whether the memory array has completed the read and write phase (i.e., temporarily storing the storage data and address data in the first array). If the array control circuit determines that the memory array has completed the read and write phase, step S460 is executed; if the array control circuit determines that the memory array has not completed the read and write phase, step S455 is repeated.

In step S460, the array control circuit restarts the voltage generator and the logic circuit so that the voltage generator generates a second control voltage (eg, the control voltage V2 in FIG. 1) to the memory array. Then, step S470 is executed.

In step S470, the adjustment parameter is detected again by the detection adjustment circuit, and the voltage value of the second writing step is adjusted according to the detected adjustment parameter. Then, step S480 is executed.

In step S480, the second array of the memory array (eg, the second array T2 in FIG. 1) performs ISPP in a second write step according to the address data and the second control voltage to store the storage data. Then, step S490 is performed.

In step S490, the array control circuit controls the first array to perform a clear operation to clear the storage data and address data temporarily stored in the first array. In some embodiments, the phase from step S460 to step S490 can be referred to as an idle phase of the memory array.

It is worth noting that since the storage data and address data are only temporarily stored in the first array during the read and write phase, and will not be stored for a long time or read and written multiple times, the stress caused to the first array is relatively small. Therefore, a higher voltage can be used in the first write step to increase the write speed. In some embodiments, the voltage value of the first write step is between 1 volt and 3 volts.

In contrast, since the second array is used for long-term data storage, it has a greater pressure. Therefore, in some embodiments, the voltage value of the second write step is smaller than the voltage value of the first write step (ie, a lower voltage is used in the idle phase) to increase the reliability of the memory device.

It should be noted that the number and order of the steps in the operating method 400 of the present disclosure are only examples and are not intended to limit the present disclosure. The number and order of other steps are within the scope of the present disclosure. In some embodiments, step S430 and step S470 may be omitted. In some embodiments, step S456 may be included between step S455 and step S460: returning the stored data and address data to the array control circuit via the first array.

By dividing the memory array into two arrays and executing ISPP on the two arrays at different writing steps, the memory device 100 of the present disclosure can maintain stable reliability while increasing the writing speed. In addition, by using one array as a buffer to temporarily store data and the other array to store data in the background, the memory device 100 of the present disclosure can also improve the efficiency of storing data.

5A to 5F are schematic diagrams showing the distribution of the first array and the second array in a memory array according to some embodiments of the present disclosure. In the embodiments of FIG. 5A to 5F, the memory array is implemented by a three-dimensional memory array, and the memory array is divided into a plurality of sub-blocks by a plurality of word lines (not shown) therein.

In the embodiments of FIGS. 5A to 5C , at least a portion of one sub-block of a memory array is configured as a first array, and the remaining portion of the sub-block and other sub-blocks are configured as a second array. For example, in the embodiment of FIG. 5A , a complete subblock is configured as a first array, and other subblocks are configured as a second array; in the embodiment of FIG. 5B , a specific layer in a subblock is configured as the first array, and other layers and other subblocks of the subblock are configured as the second array; in the embodiment of FIG. 5C , a plurality of memory cells in a specific layer in a subblock that share the same specific bit line (not shown) are configured as the first array, and other memory cells and other subblocks of the subblock are configured as the second array.

In the embodiments of FIGS. 5D to 5F , at least a portion of each sub-block of the memory array is configured as a first array, and the remaining portions of the sub-blocks are configured as a second array. For example, in the embodiment of FIG. 5D, a plurality of memory cells in each sub-block that share the same specific bit line (not shown) are configured as a first array, and other memory cells in the sub-block are configured as a second array; in the embodiment of FIG. 5E, a specific layer in each sub-block is configured as a first array, and other layers of the sub-block are configured as a second array; in the embodiment of FIG. 5F, a plurality of memory cells in a specific layer in each sub-block that share the same specific bit line (not shown) are configured as a first array, and other memory cells in the sub-block are configured as a second array.

It should be noted that the configuration of the first array and the second array in FIGS. 5A to 5F is only an example and is not intended to limit the present disclosure. Other configurations of the first array and the second array are within the scope of the present disclosure. In some embodiments, the first array may be configured to be located at the lower layer or the right side of the sub-block. In other embodiments, the first array may be configured to surround the second array.

FIG. 6 is a schematic diagram showing the distribution of the first array and the second array in a memory system 600 according to some embodiments of the present disclosure. In some embodiments, the memory system 600 may be implemented by a chip including planes P1 to P4, wherein each of the planes P1 to P4 may be implemented by a memory device (e.g., the memory device 100 in FIG. 1 ), and thus the structure of the planes P1 to P4 will not be repeated below.

Compared to the memory devices in FIGS. 5A to 5F in which at least a portion of the memory devices are configured as the first array and the rest are configured as the second array, in the embodiment of FIG. 6 , at least one plane (e.g., plane P2) is configured as the first array, and the other planes (e.g., planes P1, P3, and P4) are configured as the second array. In other words, in the embodiment of FIG. 6 , the memory system 600 includes a plurality of memory devices, and the entire memory array of at least one memory device is configured as the first array, and the entire memory arrays of the other memory devices are configured as the second array. Therefore, the memory system 600 including multiple memory devices can play a similar role as the memory device 100 described above.

The above is only the preferred embodiment of the present disclosure. Without departing from the scope or spirit of the present disclosure, the structure of the present disclosure can be modified and equivalently changed in various ways. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

100: memory device 110: input circuit 120: memory array 130: voltage generator 140: logic circuit 150: array control circuit 160: detection adjustment circuit 400: operation method S410, S420, S430, S440: steps S450, S455, S460, S470: steps S480, S490: steps 600: memory system ADD: address data DATA: storage data G1~G4: subset IN: input data P1~P4: plane T1: first array T2: second array V1, V2: control voltage Vt: output voltage W1, W2: spacing

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure document more clearly understandable, the attached drawings are described as follows: Figure 1 is a functional block diagram of a memory device according to some embodiments of the present disclosure document; Figure 2 is a schematic diagram of output voltage-quantity of multiple subsets of output voltages according to some embodiments of the present disclosure document; Figure 3 is a schematic diagram of the relationship between adjustment parameters and the gradually increasing pulse write (ISPP) size and total execution time according to some embodiments of the present disclosure document; Figure 4 is a flow chart of the operation method of the memory device according to some embodiments of the present disclosure document; Figures 5A to 5F are schematic diagrams of the configuration of the first array and the second array in the memory array according to some embodiments of the present disclosure document; and Figure 6 is a schematic diagram of the configuration of the first array and the second array in the memory system according to some embodiments of the present disclosure document.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Memory device

110: Input circuit

120:Memory array

130: Voltage generator

140:Logic circuit

150: Array control circuit

160: Detection and adjustment circuit

ADD: Address data

DATA:Store data

IN: Enter data

T1: First array

T2: Second Array

V1, V2: control voltage

Claims (20)

A memory device comprises: A memory array, comprising a first array and a second array; A voltage generator, coupled to the memory array; and An array control circuit, coupled to the memory array and the voltage generator, for: In a read/write phase of the memory array: Control the voltage generator to generate a first control voltage to the memory array; and Generate a temporary address to control the first array to store a storage data and an address data in a first write step according to the temporary address and the first control voltage, In an idle phase of the memory array: Control the voltage generator to generate a second control voltage to the memory array; Control the second array to store the storage data in a second write step according to the address data and the second control voltage; and Control the first array to perform a clear operation, wherein a voltage value of the first write step is greater than a voltage value of the second write step. The memory device as described in claim 1 further includes an input circuit coupled to the memory array and the array control circuit, for splitting an input data into the storage data and the address data. The memory device as described in claim 1 further includes a detection adjustment circuit coupled to the voltage generator and the array control circuit, for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter in the read/write phase and the idle phase. A memory device as described in claim 1, wherein the memory array is used to generate a plurality of first output voltages based on the first control voltage, the plurality of first output voltages forming a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram, and wherein the memory array is used to generate a plurality of second output voltages based on the second control voltage, the plurality of second output voltages forming a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram. A memory device as described in claim 4, wherein the distance between two adjacent ones in the multiple first subsets is negatively correlated with the voltage value of the first write step, and the distance between two adjacent ones in the multiple second subsets is negatively correlated with the voltage value of the second write step. A memory device as described in claim 1, wherein the memory array is divided into a plurality of sub-blocks according to a plurality of word lines, one of the plurality of sub-blocks is used at least partially as the first array, and at least one of the remaining plurality of sub-blocks is used as the second array. A memory device as described in claim 1, wherein the memory array is divided into a plurality of sub-blocks according to a plurality of word lines, a first block of each of the plurality of sub-blocks is used as the first array, and a second block of each of the plurality of sub-blocks is used as the second array. The memory device as claimed in claim 1, wherein the voltage value of the first writing step is between 1 volt and 3 volts. An operation method, applicable to a memory device, comprises: Receiving a storage data and an address data by a memory array of the memory device; In a read-write phase of the memory array, activating a voltage generator of the memory device by an array control circuit of the memory device to generate a first control voltage to the memory array; In the read-write phase, generating a temporary address by the array control circuit to control a first array of the memory array to store the storage data and the address data in a first write step according to the temporary address and the first control voltage; In an idle phase of the memory array, the array control circuit activates the voltage generator to generate a second control voltage to the memory array; In the idle phase, the array control circuit controls a second array of the memory array to store the storage data in a second write step according to the address data and the second control voltage; and In the idle phase, the array control circuit controls the first array to perform a clear operation, wherein a voltage value of the first write step is greater than a voltage value of the second write step. The operating method as described in claim 9, wherein receiving the storage data and the address data by the memory array of the memory device comprises: receiving an input data by an input circuit of the memory device; splitting the input data into the storage data and the address data by the input circuit; and transmitting the storage data and the address data to the memory array by the input circuit. The operating method as described in claim 9 further includes: In the read-write phase, a detection adjustment circuit of the memory device adjusts the voltage value of the first write step according to at least one adjustment parameter; and In the idle phase, the detection adjustment circuit adjusts the voltage value of the second write step according to the at least one adjustment parameter. The operating method as described in claim 9 further includes: Generating a plurality of first output voltages based on the first control voltage by the memory array, wherein the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram; and Generating a plurality of second output voltages based on the second control voltage by the memory array, wherein the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram. An operating method as described in claim 12, wherein the spacing between two adjacent ones in the multiple first subsets is negatively correlated with the voltage value of the first write step, and the spacing between two adjacent ones in the multiple second subsets is negatively correlated with the voltage value of the second write step. The operating method as described in claim 9 further includes: dividing the memory array into multiple sub-blocks by multiple word lines of the memory device; configuring one of the multiple sub-blocks at least partially as the first array by the array control circuit; and configuring the remaining at least one of the multiple sub-blocks as the second array by the array control circuit. The operating method as described in claim 9 further includes: dividing the memory array into multiple sub-blocks by multiple word lines of the memory device; configuring a first block of each of the multiple sub-blocks as the first array by the array control circuit; and configuring a second block of each of the multiple sub-blocks as the second array by the array control circuit. The operating method as described in claim 9, wherein the voltage value of the first write step is between 1 volt and 3 volts. A memory system includes a plurality of memory devices, wherein each of the plurality of memory devices includes: a memory array; a voltage generator coupled to the memory array; and an array control circuit coupled to the memory array and the voltage generator, wherein the memory array of at least one first memory device among the plurality of memory devices is configured as a first array, and the memory array of at least one second memory device among the plurality of memory devices is configured as a second array, In a read/write phase of the memory system, the array control circuit of the at least one first memory device is used to control the voltage generator of the at least one first memory device to generate a first control voltage to the first array, and to generate a temporary address to the first array, so as to control the first array to store a storage data and an address data in a first write step according to the temporary address and the first control voltage. In an idle phase of the memory system, the array control circuit of the at least one second memory device is used to control the voltage generator of the at least one second memory device to generate a second control voltage to the second array, so as to control the second array to store the storage data in a second write step according to the address data and the second control voltage, and the array control circuit of the at least one first memory device is used to control the first array to perform a clear operation, wherein a voltage value of the first write step is greater than a voltage value of the second write step. A memory system as described in claim 17, wherein each of the plurality of memory devices further comprises an input circuit coupled to the memory array and the array control circuit for splitting an input data into the storage data and the address data. A memory system as described in claim 17, wherein each of the multiple memory devices further includes a detection adjustment circuit coupled to the voltage generator and the array control circuit, for adjusting the voltage value of the first write step and the voltage value of the second write step according to at least one adjustment parameter in the read and write phase and the idle phase. A memory system as described in claim 17, wherein the memory array is used to generate a plurality of first output voltages based on the first control voltage, and the plurality of first output voltages form a plurality of first subsets that do not overlap with each other in an output voltage-quantity diagram, wherein the memory array is used to generate a plurality of second output voltages based on the second control voltage, and the plurality of second output voltages form a plurality of second subsets that do not overlap with each other in the output voltage-quantity diagram, and wherein the spacing between two adjacent ones in the plurality of first subsets is negatively correlated with the voltage value of the first write step, and the spacing between two adjacent ones in the plurality of second subsets is negatively correlated with the voltage value of the second write step.