TWI888799B - Biofet sensing chip - Google Patents

Abstract

A biofield effect (BioFET) sensing chip is provided, which includes a substrate, a field effect transistor is disposed on the first region of the substrate, an insulation layer is encapsulated the field effect transistor and the first region of the substrate, and disposed on the surface of the second region of the substrate to expose the surface of the second region of the substrate, a multilayer interconnection structure is disposed on the substrate of the second region. The multilayer interconnection structure is located in the opening of the insulation layer and the multilayer interconnection structure in the opening sequentially from the surface of the second region of the substrate includes a bottom conductive layer, an upper conductive layer and a dielectric layer with conductive plug disposed between the bottom conductive layer and the upper conductive layer, and the bottom conductive layer of the multilayer interconnection structure is electrically connected to the field effect transistor; and a receptor is arranged on the surface of the upper conductive layer of the multilayer interconnection structure to capture the target(s) of the sample.

Description

Bio-field effect sensor chip

The present invention relates to a detection technology field, in particular to a biological field effect sensing chip that can detect proteins, bacteria, and viruses.

Biosensors are devices that operate based on electrical, electrochemical, optical and mechanical detection principles to sense and detect biomolecules. Biosensors with transistors can electrically sense the charge, photons and mechanical properties of biomolecules or bioentities. This detection behavior can be achieved through direct detection sensing, or through specific reactants reacting or interacting with biomolecules/bioentities. These biosensors can be manufactured using semiconductor processes, can quickly convert electronic signals, and are easily applied to integrated circuits (ICs) and microelectromechanical systems (MEMs).

A biochip is essentially a miniature laboratory that can perform hundreds or thousands of biochemical reactions simultaneously. Biochips can detect specific biomolecules, measure their properties, process signals computationally, and even directly analyze data, so biochips allow researchers to quickly screen large numbers of biological analytes for a variety of purposes, from disease diagnosis to detection of bioterrorism attacks. Advanced biochips use many biosensors alongside fluid channels for reaction integration, sensing, and sample management. BioFETs (biological field-effect transistors, or bio-organic field-effect transistors) are a type of biosensor containing transistors that can electrically sense biomolecules or biological entities. Although bio-FETs have advantages in many aspects, there are also some challenges in their manufacturing and/or operation, such as: issues based on compatibility with semiconductor processes, biological restrictions and/or limitations, and many challenges in large-scale integration (LSI) processes, such as: integration of electronic signals and biological applications.

In addition, the existing biosensor chips can only detect the presence/absence of bacteria, viruses or suspended particles, and the detection area is limited, and its concentration cannot be estimated. In addition, the high-sensitivity nanowires designed by the chip method are prone to noise interference, which can easily lead to misjudgment. The nanowires are exposed to the outside with polysilicon, which is a special process. However, most chip factories are unwilling to provide special and customized processes to cooperate with production and manufacturing, so the yield cannot be improved and production cannot be effective.

The main purpose of the present invention is to disclose a biological field effect sensing chip, which can be manufactured according to the complementary metal oxide semiconductor (CMOS) process currently available in semiconductor chip factories.

Another purpose of the present invention is to place the multi-layer interconnect structure on the same plane as the field effect transistor and to keep a distance therefrom. In the process of forming the multi-layer interconnect structure, the bottom conductor layer is electrically connected to the field effect transistor by using semiconductor process technology, without the need for additional processes, thereby simplifying the process and reducing costs.

Another purpose of the present invention is that since there is good airtightness between the bottom conductor layer and the isolation layer of the multi-layer interconnect structure, the entire biofield effect sensing chip can be used for the detection of liquid samples to be tested, and there will be no problem of liquid overflowing from the bottom conductor layer and the isolation layer to cause a short circuit in the biofield effect sensing chip.

According to the above purpose, the present invention discloses a bio-field effect sensing chip, comprising: a substrate having a first region and a second region; a field effect transistor disposed in the first region of the substrate; an isolation layer covering the field effect transistor in the first region of the substrate and disposed in the second region of the substrate, and having an opening to expose the surface of the second region of the substrate; a multi-layer internal connection structure disposed on the surface of the second region of the substrate and located in the opening of the isolation layer, wherein the multi-layer internal connection structure in the opening is The structure includes, from the surface of the second area of the substrate upward, a bottom conductor layer, an upper conductor layer, and at least one dielectric layer having a plurality of conductive pillars disposed between the bottom conductor layer and the upper conductor layer, the bottom conductor layer and the upper conductor layer are electrically connected through the conductive pillars, and the bottom conductor layer of the multi-layer interconnect structure is electrically connected to the field effect transistor in the first area of the substrate; and a plurality of receivers disposed on the surface of the upper conductor layer for capturing at least one target in the sample to be tested.

1: Bio-field effect sensor chip

10:Substrate

10A: First Area

10B: Second area

110: Dashed line

20: Field effect transistor

201: Gate oxide layer

202: Gate

204:Source

206:Jiji

30: Isolation layer

302: Open mouth

40:Multi-layer internal connection structure

402: Insulation layer

410: Bottom conductor layer

412: First dielectric layer

414: Intermediate conductor layer

416: Second dielectric layer

418: Upper conductor layer

510: First conductive pillar

512: Second conductive pillar

60: Receiver

90: Samples to be tested

902: Target (target molecule)

Figure 1 is a schematic diagram of a bio-field effect sensing chip according to the technology disclosed in the present invention.

Figure 2 is a schematic diagram showing the detection of a sample by a bio-field effect sensing chip according to the technology disclosed in the present invention.

First, please refer to Figure 1. Figure 1 shows a cross-sectional schematic diagram of a biofield effect sensing chip. In Figure 1, the biofield effect sensing chip 1 is composed of a field effect transistor (FET) 20 and a multilayer interconnection structure 40, wherein the field effect transistor 20 and the multilayer interconnection structure 40 are respectively arranged in the first region 10A and the second region 10B of the substrate 10, and the two are in the same plane. It should be noted that in Figure 1, the substrate 10 is divided into the first region 10A and the second region 10B by a dotted line 110 for easy understanding of the subsequent explanation. In fact, there is no such dotted line 110 on the substrate 10.

The field effect transistor 20 may be, for example, an N-type metal oxide semiconductor (NMOS), and its structure at least includes a gate oxide layer 201, a gate 202, a source 204, and a drain 206, wherein the source 204 and the drain 206 are disposed in the first region 10A of the substrate 10, the gate oxide layer 201 is located on the substrate 10, the gate 202 is disposed on the gate oxide layer 201, and is located between the source 204 and the drain 206, and is disposed on the substrate 10, and an isolation layer (or field oxide layer) is further disposed in the first region 10A and the second region 10B of the substrate 10, respectively. It should be noted that the isolation layer 30, gate oxide layer 201, gate 202, source 204 and drain 206 are formed by using a suitable complementary metal oxide semiconductor (CMOS) process. The formation steps are not the main technical features of the present invention and will not be described in detail here.

Next, an insulating layer 402 is provided on the surface of the substrate 10 in the second region 10B. It should be noted that the insulating layer 402 is formed simultaneously with the gate oxide layer 201 of the field effect transistor 20, and then a portion of the insulating layer 402 is removed by an etching process. For the sake of distinction, the insulating layer on the first region 10A is defined as the gate oxide layer 201, and the insulating layer on the second region 10B is defined as the insulating layer 402. Next, a multi-layer interconnect structure 40 is formed on the insulating layer 402 by a semiconductor process, and the steps include: first, a bottom conductor layer 410 is formed on the insulating layer 402, and the bottom conductor layer 410 extends toward the field effect transistor 20 on the same plane and is electrically connected to the gate 202 of the field effect transistor 20. It should be noted that the bottom conductor layer 410 on the second region 10B of the substrate 10 serves as the first metal layer (metal 1) of the multi-layer interconnect structure 40, and the bottom conductor layer 410 extending toward the field effect transistor 20 serves as a connection layer electrically connected to the gate 202. It should be noted that the material of the bottom conductor layer 410 can be gold or copper.

Next, an isolation layer 30 is disposed on the substrate 10, wherein the isolation layer 30 on the first region 10A of the substrate 10 is used to cover the field effect transistor 20, and the isolation layer 30 on the second region 10B of the substrate 10 is partially removed by a semiconductor etching process to form an opening 302, thereby exposing the bottom conductor layer 410 on the second region 10B of the substrate 10. In addition, the isolation layer 30 also covers the portion of the bottom conductor layer 410 extending toward the field effect transistor 20. Next, a first dielectric layer 412 is formed on the bottom conductor layer 410 using semiconductor process technology. Then, an etching process is used to remove part of the first dielectric layer 412, so that a plurality of first via holes (not shown in the figure) are formed in the first dielectric layer 412. Subsequently, a semiconductor process technology is used to deposit or electroplating a conductive material such as copper, tungsten, titanium or tantalum or a metal compound thereof in the first via hole (not shown in the figure) to form a first conductive plug 510.

Next, an intermediate conductive layer 414 is formed on the first dielectric layer 412 having the plurality of first conductive pillars 510, so that the intermediate conductive layer 414 is electrically connected to the bottom conductive layer 410 through the plurality of conductive pillars 510 in the first dielectric layer 412. Then, another deposition step is performed on the intermediate conductive layer 414 to form a second dielectric layer 416. Similar to the step of forming the plurality of first vias (not shown in the figure), an etching step is used to remove a portion of the second dielectric layer 416 to form a plurality of second vias (not shown in the figure) in the second dielectric layer 416. Similarly, a conductive material such as copper, tungsten, titanium or tantalum or a metal compound thereof is deposited or electroplated in a second via hole (not shown in the figure) using semiconductor process technology to form a second conductive plug 512. Finally, an upper conductive layer 418 is deposited on the second dielectric layer 416 having a plurality of second conductive plugs 512, wherein the upper conductive layer 418 is electrically connected to the middle conductive layer 414 through the plurality of second conductive plugs 512. Specifically, the upper conductive layer 418 and the bottom conductive layer 410 can be electrically connected to each other through the second conductive plugs 512, the middle conductive layer 414 and the first conductive plugs 510.

A plurality of receptors 60 are disposed on the upper conductor layer 418 of the multi-layer interconnect structure 40. These receptors 60 are used to capture targets (not shown in the figure) in the sample to be tested (not shown in the figure). It should be noted that the above-mentioned multi-layer interconnect structure 40 is composed of a bottom conductor layer 410, a first dielectric layer 412 having a plurality of first conductive pillars 510, an intermediate conductor layer 414, a first dielectric layer 416 having a plurality of second conductive pillars 512, and an upper conductor layer 418. In one embodiment, the multi-layer interconnect structure 40 may be composed of the bottom conductor layer 410 and the upper conductor layer 418, and the first dielectric layer 412 having a plurality of first conductive pillars 510 between the bottom conductor layer 410 and the upper conductor layer 418. In another embodiment, the multi-layer interconnect structure 40 may be formed by stacking four, five or more layers of conductor layers and dielectric layers with a plurality of conductive pillars between the conductor layers. No matter how many layers of conductor layers and dielectric layers with a plurality of conductive pillars are stacked, the multi-layer interconnect structure 40 extends toward the gate 202 of the field effect transistor 20 and serves as a gate. The bottom conductor layer 410 of the connection layer is electrically connected, and the top layer of the multi-layer internal connection structure 40, that is, the surface of the upper conductor layer 418, is provided with multiple receptors 60 for capturing the target of the sample to be tested. These receptors 60 are fixed on the upper conductor layer 418 in a fixed manner during the antibody processing process after the production of the biofield effect sensor chip 1. Therefore, in the present invention, the multi-layer internal connection structure 40 with multiple receptors 60 on the second area 10B of the substrate 10 is defined as a detection area or a sensing area.

Please continue to refer to FIG. 2. FIG. 2 is a schematic diagram showing the detection of a sample by a bio-field effect sensing chip according to the technology disclosed in the present invention. In FIG. 2, when a sample 90 having multiple targets (or target molecules) 902 is placed in the detection area, the sample 90 is allowed to fully contact with multiple receptors 60 for a period of time. During the contact process, the multiple receptors 60 on the upper conductive layer 418 are used to capture the target (or target molecule) 902 in the sample 90. When the receptors 6 After capturing the target object (or target molecule) 902, the voltage value is transmitted to the gate 202 of the field effect transistor 20 through the upper conductive layer 418, multiple second conductive pillars 512, the middle conductive layer 414 and multiple first conductive pillars 510 through the bottom conductive layer 410, and then the current value (I _out ) corresponding to the voltage value is output to the external processing unit (not shown in the figure) through the gate 202 of the field effect transistor 20 to obtain the concentration value (or quantity) of the target object 902 in the fluid 60 to be tested.

For example, the sample 90 to be tested may be a BTP buffer solution containing an unknown target concentration, whole blood, or plasma. When the sample 90 to be tested is whole blood or plasma, the sample 90 to be tested may be diluted with the BTP buffer solution. Then, the diluted sample 60 to be tested is dropped into the detection area (i.e., the second area 10B of the multi-layer interconnect structure 40 having a plurality of receivers 60), and the diluted sample 90 to be tested is left to stand for a period of time, so that the plurality of receivers 60 are in full contact with the diluted sample 90, so that the receivers 60 have sufficient time to capture the target 9 in the diluted sample 60. 02, when the multiple receptors 60 on the surface of the upper conductive layer 418 begin to capture the target 902 in the diluted test fluid 60, the voltage value of the upper conductive layer 418 will change with the amount of target 902 captured by the receptor 60, and the field effect transistor 20 will output the voltage value change corresponding to the upper conductive layer 418 in the form of current (i.e., I _out in FIG. 2) to the external processing unit (not shown in the figure) connected to the bio-field effect sensing chip 1. The external processing unit (not shown in the figure) processes the current change generated by the receptor 60 capturing the target 902 in the test sample 90, and the concentration value (or amount) of the target 902 in the test fluid 90 can be obtained. In this embodiment, the target 902 in the sample 90 to be tested can be an organism. When the sample 90 to be tested is a buffer, the target 902 in the buffer can be yeast, bacteria, virus or protein; and when the sample 90 to be tested is plasma, the target 902 in the plasma can be a cell.

Since the bottom conductive layer 410 of the multi-layer interconnect structure 40 disclosed in the present invention is airtight with the isolation layer 30, when the sample to be tested is plasma, whole blood, or other liquid sample 90 and drips into the opening 302 (i.e., the second area 10B where the multi-layer interconnect structure 40 is located), the liquid sample 90 will not be transported from the multi-layer interconnect structure 40 to the isolation layer 30. The overflow between the bottom conductor layer 410 of the structure 40 and the isolation layer 30 to the field effect transistor 20 will not cause the field effect transistor 20 to short-circuit, thereby improving the durability of the biological field effect sensing chip 1. Therefore, the biological field effect sensing chip 1 is formed by integrating the multi-layer interconnect structure 40 and the field effect transistor 20 on the substrate 10, which can achieve the purpose of liquid detection on the chip.

1: Bio-field effect sensor chip

10:Substrate

10A: First Area

10B: Second area

110: Dashed line

20: Field effect transistor

201: Gate oxide layer

202: Gate

204:Source

206:Jiji

30: Isolation layer

40:Multi-layer internal connection structure

402: Insulation layer

410: Bottom conductor layer

412: First dielectric layer

414: Intermediate conductor layer

416: Second dielectric layer

418: Upper conductor layer

510: First conductive pillar

512: Second conductive pillar

60: Receiver

Claims (5)

A bio-field effect sensing chip comprises: a substrate having a first region and a second region; a field effect transistor arranged in the first region of the substrate, wherein the field effect transistor comprises a gate oxide layer, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode are located in the substrate, the gate oxide layer is arranged on the substrate and the gate electrode is arranged on the gate oxide layer. and located between the source and the drain; an isolation layer, disposed on the first region and the second region of the substrate, covering the field effect transistor in the first region of the substrate, and having an opening to expose a surface of the second region of the substrate; a multi-layer interconnect structure, disposed on the surface of the second region of the substrate and located in the opening of the isolation layer, wherein The multi-layer interconnect structure in the opening includes, from the surface of the second region of the substrate upward, a bottom conductor layer disposed on the surface of the second region of the substrate; and an upper conductor layer disposed on the bottom conductor layer, wherein at least one dielectric layer having a plurality of conductive posts is disposed between the bottom conductor layer and the upper conductor layer. The bottom conductor layer of the multi-layer interconnect structure is electrically connected to the upper conductor layer through the conductive pillars, and the bottom conductor layer of the multi-layer interconnect structure is electrically connected to the gate of the field effect transistor in the first area of the substrate through the isolation layer from the surface of the opening in the second area; and a plurality of receivers are arranged on a surface of the upper conductor layer to capture at least one target in a sample to be tested. The biofield effect sensing chip as described in claim 1, wherein the bottom conductive layer can be gold or copper. The biofield effect sensing chip as described in claim 1 further includes an insulating layer on the surface of the second region of the substrate. The biofield effect sensing chip as described in claim 1 further includes an external processing unit electrically connected to the biofield effect sensing chip for processing a value corresponding to a current change generated when the receivers capture the target in the sample to be tested. The biofield effect sensing chip as described in claim 1, wherein the target can be yeast, bacteria, cells, viruses or proteins or DNA, RNA.

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