TWI887590B - Light-emitting device - Google Patents

Abstract

A light-emitting device includes a substrate, a first-type semiconductor layer, a second-type semiconductor layer, an active region and a stack structure. The first-type semiconductor layer is disposed on the substrate. The second-type semiconductor layer is disposed on the first-type semiconductor layer. The active region is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The stack structure is disposed between the first-type semiconductor layer and the active region. The stack structure includes a conductive area and a plurality of reflective portions distributed in the conductive area.

Description

Light-emitting element

This application relates to a light-emitting element, in particular a light-emitting element having a reflective structure.

Solid-state semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed, and good photoelectric properties, such as stable luminous wavelength, due to the characteristics of semiconductor constituent materials. Therefore, LEDs are widely used in household appliances, equipment indicator lights, and optoelectronic products.

This application discloses a light-emitting element including a substrate, a first-type semiconductor layer, a second-type semiconductor layer, an active region, and a stacking structure. The first-type semiconductor layer is located on the substrate. The second-type semiconductor layer is located on the first-type semiconductor layer. The active region is located between the first-type semiconductor layer and the second-type semiconductor layer. The stacking structure is located between the first-type semiconductor layer and the active region. The stacking structure has a conductive region and a plurality of reflective portions spaced apart in the conductive region.

100, 50: Light-emitting element

101:Substrate

102: Type I semiconductor layer

103: Type II semiconductor layer

104: Active area

105: Stacked structure

105’: Layering

106: Conductive area

107: Reflection part

108: Channel

1A: Light-emitting device

110: Type I doping layer

111: Unintentional adulteration

111a: Top floor

111b: bottom layer

112: Buffer layer

113: First electrode

114: Second electrode

115:Transparent conductive layer

116: Current blocking layer

117: First electrode pad

118: first extension electrode

119: Second electrode pad

120: Second extension electrode

121: concave part

L:Light

P: porous structure layer

P1: Protective layer

T: First channel

2P: Luminescent package

14: Wire

15: Cavity

16: Subject

23: Packaging materials

50a: First wire terminal

50b: Second wire terminal

52: Circuit board

54:Terminal

56: Transparent cover

58: Heat sink

A-A: Section line

X: Lateral

Y: Stacking direction

[Figure 1] shows a schematic top view of a light-emitting element of an embodiment of the present application.

[Figure 2] shows a schematic cross-sectional view along line A-A in Figure 1.

[Figure 3A] to [Figure 3F] show schematic diagrams of the manufacturing process of the light-emitting element of an embodiment of the present application.

[Figure 4] shows a schematic cross-sectional view of a light-emitting package of an embodiment of the present application.

[Figure 5] shows a cross-sectional schematic diagram of a light-emitting device of an embodiment of the present application.

The following embodiments will be accompanied by drawings and descriptions, in which similar or identical parts are numbered the same, and in the drawings, the shape or thickness of the elements may be enlarged or reduced. It should be noted that the elements not shown in the drawings or described in the specification may be in forms known to those skilled in the art. In addition, some elements and/or symbols may be omitted in some drawings. In the drawings, similar elements are indicated by similar symbols. The following content and the attached drawings are provided for illustration only and are not intended to be limiting. It is expected that the elements and features in one embodiment can be advantageously incorporated into another embodiment without further elaboration. In addition, other layers/structures or steps may be incorporated in the following embodiments. For example, the description of "forming a second layer/structure on a first layer/structure" may include an embodiment in which the first layer/structure directly contacts the second layer/structure, or an embodiment in which the first layer/structure indirectly contacts the second layer/structure, that is, other layers/structures exist between the first layer/structure and the second layer/structure. In addition, the spatial relative relationship between the first layer/structure and the second layer/structure may change according to the operation or use of the device, and the first layer/structure itself is not limited to a single layer or a single structure. The first layer may include multiple sublayers, and the first structure may include multiple substructures.

In addition, for the spatially related descriptive terms mentioned in this application, such as "under", "low", "down", "above", "above", "down", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another element or feature in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the light-emitting element during use and operation. With the different orientations of the semiconductor element (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

a

1；通式InGaN系列代表In_bGa_(1-b)N，其中0

b

1；通式AlInGaN系列代表Al_cIn_dGa_(1-c-d)N，其中0

c

1，0

d

1。調整元素的含量可以達到不同的目的，例如但不限於，調整能階或是調整發光元件的主發光波長。 In this application, unless otherwise specified, the general formula AlGaN series represents Al _a Ga _(1-a) N, where 0

a

1; the general formula InGaN series represents In _b Ga _(1-b) N, where 0

b

1; the general formula AlInGaN series represents Al _c In _d Ga _(1-cd) N, where 0

c

1,0

d

1. Adjusting the content of elements can achieve different purposes, such as but not limited to, adjusting the energy level or adjusting the main emission wavelength of the light-emitting element.

The composition and doping of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as secondary ion mass spectrometer (SIMS).

The thickness of each layer included in the light-emitting element disclosed in this application can be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscope (SEM), so as to match the depth position of each layer on the SIMS spectrum, for example.

FIG1 is a schematic top view of a light-emitting element of an embodiment of the present application. FIG2 is a schematic cross-sectional view along line A-A of FIG1. Referring to FIG1 and FIG2, the present embodiment discloses a light-emitting element 100, which includes a substrate 101, a first-type semiconductor layer 102, a second-type semiconductor layer 103, an active region 104, and a stacking structure 105. Along a stacking direction Y, the first-type semiconductor layer 102 is located on the substrate 101, the second-type semiconductor layer 103 is located on the first-type semiconductor layer 102, the active region 104 is located between the first-type semiconductor layer 102 and the second-type semiconductor layer 103, and the stacking structure 105 is located between the first-type semiconductor layer 102 and the active region 104. The stacking structure 105 has a conductive region 106 and a plurality of reflective portions 107. The reflective portions 107 are spaced apart in the conductive region 106 in a side direction X perpendicular to the stacking direction Y.

As shown in FIG. 2 , in one embodiment, the light emitting element 100 includes a light emitting diode or a laser light emitting element. By changing the physical and chemical composition of one or more layers in the epitaxial structure, such as the active region 104, the wavelength of the light L emitted can be adjusted. The first type semiconductor layer 102, the stacked structure 105, the active region 104 and the second type semiconductor layer 103 can include the same series of III-V semiconductor materials. When the material of the active region 104 is aluminum gallium nitride (AlGaN) series or aluminum indium gallium nitride (AlInGaN) series material, ultraviolet light with a wavelength between 400nm and 250nm can be emitted. Specifically, the material of the active region 104, the first type semiconductor layer 102 and the second type semiconductor layer 103 is aluminum gallium nitride (AlGaN) series material, which can emit deep ultraviolet light with a wavelength lower than 365nm. Specifically, the material of the active region 104 is aluminum indium gallium nitride (AlInGaN) series material, the material of the first type semiconductor layer 102 and the second type semiconductor layer 103 is aluminum indium gallium nitride (AlInGaN) series material, which can emit ultraviolet light with a wavelength higher than 365nm. The first type semiconductor layer 102 may be an n-type doped (e.g., silicon doped) aluminum gallium nitride semiconductor layer, and the second type semiconductor layer 103 may be a p-type doped (e.g., magnesium doped) aluminum gallium nitride semiconductor layer, but is not limited thereto. The material of the active region 104 may also be an InGaN series material to emit blue light with a wavelength between 400nm and 490nm, cyan light with a wavelength between 490nm and 530nm, or green light with a wavelength between 530nm and 570nm. In one embodiment, the active region 104 may include a single heterostructure, a double heterostructure, or multiple quantum wells. In one embodiment, the material of the active region 104 may be an i-type, p-type, or n-type semiconductor.

As shown in FIG. 2 , in one embodiment, the light-emitting element 100 may further include a plurality of channels 108. Each channel 108 is disposed corresponding to each reflective portion 107. Each channel 108 passes through the second semiconductor layer 103 and the active region 104 and extends into the stacked structure 105. Each reflective portion 107 surrounds the corresponding channel 108. In one embodiment, each channel 108 does not completely penetrate the stacked structure 105. The bottom of each channel 108 is a portion of the stacked structure 105. The channel 108 may be formed by dry etching such as laser, inductively coupled plasma (ICP) and/or wet etching using an etching solution.

As shown in FIG2 , in one embodiment, the stacked structure 105 includes one or more unintentionally doped layers 111 having a first region and a second region. One or more first type doped layers 110 are formed on the first region of the unintentionally doped layers 111 to form a conductive region 106; and one or more porous structure layers P are formed on the second region of the unintentionally doped layers 111 to form a reflective portion 107. Specifically, the conductive region 106 may include a semiconductor layer pair consisting of the first type doped layer 110 and the unintentionally doped layer 111. The number of pairs of semiconductor layers may be one or more pairs. In one embodiment, for example, 8 to 12 pairs of semiconductor layers composed of the first type doped layer 110 and the unintentional doped layer 111 are alternately stacked to form the conductive region 106. In one embodiment, each reflective portion 107 of the stacked structure 105 may be formed by stacking a reflective layer pair composed of a porous structure layer P and an unintentional doped layer 111. The number of pairs of reflective layer pairs may be one or more pairs. The number of pairs of reflective layer pairs is the same as the number of pairs of semiconductor layers composed of the first type doped layer 110 and the unintentional doped layer 111. In the lateral direction X, each porous structure layer P can be connected to the first type doped layer 110 of the conductive region 106, respectively. The unintentional doped layer 111 can extend from the conductive region 106 to the reflective portion 107. In one embodiment, the first type doped layer 110 and the unintentional doped layer 111 can include III-V semiconductor materials, respectively. When the light emitting element 100 emits light L with a wavelength lower than 365nm, the conductive region 106 can include a material of the aluminum gallium nitride (AlGaN) series. The first type doped layer 110 can be an n-type aluminum gallium nitride semiconductor layer, which is formed by doping n-type impurities, such as silicon (Si), to form an n-type semiconductor layer. The unintentionally doped layer 111 may be an undoped aluminum gallium nitride semiconductor layer that is not doped with impurities during the process of forming the unintentionally doped layer 111, or may have a low impurity concentration. The impurity concentration of the first type doped layer 110 may be greater than 1×10 ¹⁹ /cm ³ , and the impurity concentration of the unintentionally doped layer 111 may be less than 5×10 ¹⁷ /cm ³ . In addition, the conductive region 106 and the reflective portion 107 of the stacked structure 105 have a top layer 111a and a bottom layer 111b, respectively. In one embodiment, the unintentional doped layer 111 is used as the top layer 111a and the bottom layer 111b. In one embodiment, the top layer 111a is directly connected to the active region 104. The bottom layer 111b is directly connected to the first type semiconductor layer 102. In one embodiment, the first type doped layer 110 in the conductive region 106 may have an appropriate thickness, and the porous structure layer P in the reflective portion 107 may have an appropriate thickness. The thickness of the first type doped layer 110 is substantially the same as or different from the thickness of the porous structure layer P. The unintentional doped layer 111 may have an appropriate thickness. In one embodiment, the thickness of the unintentionally doped layer 111 should not be too thick so that the conductive region 106 remains conductive and the porous structure layer P is separated in the reflective portion 107. Specifically, the first type doped layer 110 and the unintentionally doped layer 111 may have a thickness between 1 and 100 nanometers, respectively. In addition, the thickness of the first type doped layer 110 may be greater than the thickness of the unintentionally doped layer 111, for example, the ratio of the thickness of the first type doped layer 110 to the unintentionally doped layer 111 may be between 3 and 10. Under the above appropriate thickness, when the light-emitting device 100 is driven, carriers therein can pass through the unintentionally doped layer 111 by tunneling, so that current can be conducted.

The pores in the porous structure layer P may be sponge-shaped, and the pores may be filled with a medium, such as air, to form a total reflection interface relative to the light L through the difference in refractive index between the medium and the unintentionally doped layer 111, such as a distributed Bragg reflector (DBR).

In one embodiment, the first type semiconductor layer 102 can be formed on the substrate 101 by epitaxial growth, and then the stacked structure 105, the active region 104 and the second type semiconductor layer 103 are epitaxially grown. The substrate 101 can include a sapphire (Al ₂ O ₃ ) substrate, a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate or an aluminum nitride (AlN) substrate. In one embodiment, the substrate 101 can be a patterned substrate, that is, the substrate 101 can have a patterned structure (not shown) on the surface used for epitaxial growth. Methods for performing epitaxial growth include but are not limited to metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), physical vapor deposition (PVD), and liquid-phase epitaxy (LPE).

Please continue to refer to FIG. 2 . In one embodiment, the light emitting device 100 may further include other layers between the stacked structure 105 and the active region 104. For example, in order to reduce the lattice difference between the stacked structure 105 and the active region 104 to reduce epitaxial defects, a stress release structure (not shown) may be formed between the stacked structure 105 and the active region 104. The stress release structure may be, for example, a superlattice structure, which is formed by overlapping two semiconductor layers composed of different materials. The two semiconductor layers may be, for example, an indium gallium nitride layer (InGaN) and a gallium nitride (GaN) layer, or an aluminum gallium nitride layer (AlGaN) and a gallium nitride (GaN) layer. The stress release structure can also be composed of a semiconductor stack composed of multiple layers of different materials with the same effect, such as a multi-layer structure with a gradient composition of group III elements. In one embodiment, before forming the first type semiconductor layer 102, a buffer layer 112 can be formed on the substrate 101. The buffer layer 112 can reduce the misalignment caused by lattice mismatch between the substrate 101 and the semiconductor stack including the first type semiconductor layer 102, thereby improving the epitaxial quality. In the embodiment of FIG. 2, the buffer layer 112 may include an unintentionally doped gallium nitride (GaN) semiconductor layer, but is not limited thereto.

When the light L emitted by the active region 104 is ultraviolet light with a main wavelength less than 365 nanometers, since the epitaxial material of the first type semiconductor layer 102 and/or the buffer layer 112 has a lower energy gap relative to the material of the active region 104, the light L generated by the active region 104, such as light with a wavelength below 365 nanometers, has a higher absorption rate, for example, the absorption rate is approximately between 0.42 and 0.55. However, when a stacking structure 105 is provided between the first type semiconductor 102 and the active region 104, most of the light L emitted by the active region 104 is reflected back by the reflective portion 107 in the stacking structure 105, thereby preventing the light L from being absorbed by the first type semiconductor layer 102 or the buffer layer 112, thereby improving the external quantum efficiency of the light-emitting element 100.

i

1。在又另一實施例中，緩衝層112的材料包含AlN。緩衝層112形成的方式可以為MOCVD、MBE、HVPE或PVD。PVD包含濺鍍或是電子束蒸鍍。當緩衝層112包含多個子層(圖未示)時，子層包括相同材料或不同材料。在一實施例中，緩衝層112包括兩個子層，其中第一子層的生長方式為濺鍍，第二子層的生長方式為MOCVD。在一實施例中，緩衝層112另包含第三子層。其中第三子層的生長方式為 MOCVD，第二子層的生長溫度高於或低於第三子層的生長溫度。在一實施例中，第一、第二及第三子層包括相同材料，例如AlN，或不同材料，例如AlN、GaN及AlGaN的組合。在其它實施例中，以PVD-氮化鋁(PVD-AlN)做為緩衝層，用以形成PVD-氮化鋁的靶材係由氮化鋁所組成，或者使用由鋁組成的靶材並於氮源的環境下反應性地形成氮化鋁。在另一實施例中，緩衝層112可以包含摻雜物例如矽、碳、氫、氧或其組合，且此摻雜物在緩衝結構中的濃度不小於1×10¹⁷/cm³。 In one embodiment, the buffer layer 112 may include a single layer or multiple layers. In another embodiment, the buffer layer 112 includes Al _i Ga _(1-i) N, wherein 0

i

1. In yet another embodiment, the material of the buffer layer 112 includes AlN. The buffer layer 112 may be formed by MOCVD, MBE, HVPE or PVD. PVD includes sputtering or electron beam evaporation. When the buffer layer 112 includes a plurality of sublayers (not shown), the sublayers include the same material or different materials. In one embodiment, the buffer layer 112 includes two sublayers, wherein the growth method of the first sublayer is sputtering, and the growth method of the second sublayer is MOCVD. In one embodiment, the buffer layer 112 further includes a third sublayer. The growth method of the third sublayer is MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second and third sublayers include the same material, such as AlN, or different materials, such as a combination of AlN, GaN and AlGaN. In other embodiments, PVD-aluminum nitride (PVD-AlN) is used as the buffer layer, and the target material used to form the PVD-aluminum nitride is composed of aluminum nitride, or a target composed of aluminum is used and aluminum nitride is reactively formed in an environment of a nitrogen source. In another embodiment, the buffer layer 112 may contain dopants such as silicon, carbon, hydrogen, oxygen or a combination thereof, and the concentration of the dopant in the buffer structure is not less than 1×10 ¹⁷ /cm ³ .

As shown in FIG. 1 and FIG. 2 , in one embodiment, the light-emitting element 100 may further have a recess 121. The recess 121 passes through the second type semiconductor layer 103, the active region 104 and the stacked structure 105 to expose the first type semiconductor layer 102. The recess 121 may have a pattern. The first electrode 113 may be disposed on the first type semiconductor layer 102 exposed through the recess 121, and the second electrode 114 may be disposed on the second type semiconductor layer 103. In one embodiment, the first electrode 113 may include a first electrode pad 117 and a first extended electrode 118 extending from the first electrode pad 117, and the shape of the first electrode 113 may roughly correspond to the pattern of the recess 121. The second electrode 114 may include a second electrode pad 119 and a second extension electrode 120 extending from the second electrode pad 119. To avoid short circuit or other electrical problems, the formation position of the channel 108 may be misplaced with the configuration area of the second electrode 114, so that the orthographic projection of the second electrode 114 toward the substrate 101 and the reflective portion 107 are located in different areas. The first electrode 113 and the second electrode 114 shown in FIG. 1 form a pattern that covers each other in a top view, but are not limited to this. Depending on the size of the light-emitting element 100, the device used, or other considerations, the first electrode 113 and the second electrode 114 may also have different shapes and distributions.

The first electrode 113 and the second electrode 114 are used to connect to an external power source or other electronic components and conduct current therebetween. The materials of the first electrode 113 and the second electrode 114 include metal materials. The metal materials include chromium (Cr), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh), platinum (Pt), germanium-gold-nickel (GeAuNi), titanium (Ti), benzene-gold (BeAu), germanium-gold (GeAu) or zinc-gold (ZnAu). In some embodiments, the first electrode 113 and the second electrode 114 are a single layer, or a structure including multiple layers such as a Ti/Au layer, a Ti/Al layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, a Ni/Pt/Au layer, a Ti/Al/Ti/Au layer, a Cr/Ti/Al/Au layer, a Cr/Al/Ti/Au layer, a Cr/Al/Ti/Au layer, a Cr/Al/Ti/Pt layer, or a Cr/Al/Cr/Ni/Au layer, or a combination thereof.

In one embodiment, the light emitting element 100 may further include a transparent conductive layer 115 and a current blocking layer 116. The transparent conductive layer 115 is located between the second type semiconductor layer 103 and the second electrode 114. The current blocking layer 116 is disposed on the second type semiconductor layer 103, below the second electrode 114, and covered by the transparent conductive layer 115. The material of the transparent conductive layer 115 may include a transparent conductive oxide or a light-transmissive thin metal. The transparent conductive oxide may be, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (Zn ₂ SnO ₄ , ZTO), gallium doped zinc oxide (GZO), tungsten doped indium oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO). The light-transmitting thin metal may be, for example, chromium (Cr), gold (Au), aluminum (Al), copper (Cu), silver (Ag), tin (Sn), nickel (Ni), rhodium (Rh), platinum (Pt) or titanium (Ti). The material of the current blocking layer 116 may include insulating oxide, nitride, silicon oxide, titanium oxide, aluminum oxide, magnesium fluoride or silicon nitride.

FIG. 3A to FIG. 3F are schematic diagrams showing the manufacturing process of the light-emitting element of an embodiment of the present application. As shown in FIG. 3A and FIG. 3B, first, a semiconductor stack including a buffer layer 112, a first-type semiconductor layer 102, a stack 105' including a first-type doped layer 110 and an unintentional doped layer 111, an active region 104, and a second-type semiconductor layer 103 are sequentially epitaxially grown on a substrate 101. The substrate 101 may be a portion of a wafer substrate (not shown). The stack 105' is formed by alternately growing a plurality of first-type doped layers 110 and a plurality of unintentional doped layers 111. When the first type doped layer 110 is epitaxially grown, n-type dopants, such as silicon (Si), may be doped to make the first type doped layer 110 have n-type conductivity. The unintentional doped layer 111 of the stack 105' includes a bottom layer 111b and a top layer 111a. The bottom layer 111b is epitaxially grown after the first type semiconductor layer 102, and the active region 104 is epitaxially grown after the top layer 111a. The first type doped layer 110 and the unintentional doped layer 111 of the stack 105' may include materials of the aluminum gallium nitride (AlGaN) series, and specifically, may be aluminum gallium nitride.

When growing the stack 105', the first type doped layer 110 and the unintentional doped layer 111 can have appropriate thicknesses. Specifically, the first type doped layer 110 and the unintentional doped layer 111 can have thicknesses between 1 and 100 nanometers. Specifically, the thickness of the first type doped layer 110 can be greater than the thickness of the unintentional doped layer 111, for example, the thickness ratio of the first type doped layer 110 to the unintentional doped layer 111 can be between 3 and 10. The thickness of the unintentional doped layer 111 allows carriers to tunnel to conduct current.

Next, a channel 108 is formed. There may be multiple channels 108, for example, multiple channels 108 are formed as shown in FIG. 2. In one embodiment, the method of forming the channel 108 includes directly removing part of the semiconductor stack in one step to form the channel 108. In another embodiment, the method of forming the channel 108 includes two-step removal, and the first step of removal includes forming the first channel T. The removal method includes penetrating the active region 104 and the second semiconductor layer 103 by dry etching such as laser, inductively coupled plasma (ICP) and/or wet etching using an etching liquid to form the first channel T and expose part of the upper surface of the stack 105'. In this embodiment, the first channel T is formed by a non-wet etching method, for example, by a dry etching method such as laser or inductively coupled plasma.

As shown in FIG. 3B to FIG. 3D , the second stage of removal includes removing part of the stack 105′ by dry or wet etching to form the channel 108. In this embodiment, the method of removing part of the stack 105′ in the second stage is different from the method of forming the first channel T, for example, wet etching is selected to remove part of the stack 105′. Since the first type doped layer 110 and the unintentional doped layer 111 are formed of different materials, by selecting a suitable etching solution and controlling the conditions of wet etching, such as time, the channel 108 does not penetrate the stack 105′ and stays at a depth of at least retaining the bottom layer 111b. However, in other embodiments not shown, the channel 108 can also be formed by dry etching such as laser or inductively coupled plasma or a combination of different etching methods. Before performing the second stage removal, a protective layer P1 can be formed on the side surface of the second type semiconductor layer 103 and the active region 104 and the upper surface of the second type semiconductor layer 103 in the first channel T, and part of the upper surface of the stack 105' is not covered by the protective layer P1. When wet etching is performed, the protective layer P1 can protect the second type semiconductor layer 103 and the active region 104 from being corroded by the etching solution. The protective layer P1 is, for example, an insulating oxide.

Next, referring to FIG. 3D , a stacked structure 105 is formed, which includes a conductive region 106 and a plurality of reflective portions 107 spaced apart in the conductive region 106. In this embodiment, an etching solution, such as a nitride acidic etching solution, can be introduced through the channel 108, and by controlling etching conditions, such as reaction time, the stacked layer 105' forms a reflective portion 107 in the surrounding area of the channel 108. Since the first type doped layer 110 and the unintentional doped layer 111 have different doping conditions, during the electrochemical etching process, the nitride acid etchant tends to etch a specific doped layer, for example, the first type doped layer 110, while the unintentional doped layer 111 is not substantially etched. Within a predetermined reaction time, the nitride acid etching solution used in the electrochemical etching selectively etches the first type doped layer 110, thereby forming a porous structure layer P in the first type doped layer 110, and the unintentionally doped layer 111 is not etched or only slightly etched to a negligible extent, so as to stack one or more pairs of reflective layers with different refractive indices, thereby forming the reflective portion 107. In the electrochemical etching process of forming the reflective portion 107, the bottom layer 111b and the top layer 111a which are not doped with n-type are not easily etched, and thus can be used as a protective layer to prevent the active region 104 and the first type semiconductor layer 102 from being infiltrated by the nitride acid etching solution, so as to avoid damage to the active region 104 and the first type semiconductor layer 102. The size of the pores in the porous structure layer P can be determined by the material of the stack 105'. For example, when the first type doped layer 110 and the unintentionally doped layer 111 of the stack 105' are aluminum gallium nitride, the aluminum content ratio can be adjusted during the epitaxial growth process. In one embodiment, when the aluminum content of the first type doped layer 110 is higher, the pore size of the porous structure layer P formed by electrochemical etching is smaller, and the etching speed is slower. On the contrary, the larger the pore size of the porous structure layer P, the faster the etching speed. Specifically, the aluminum content of the aluminum-gallium nitride in the first type doped layer 110 can be between 5% and 15%. In one embodiment, the aluminum content ratio of each first type doped layer 110 in the stack 105' can be the same or different. When the aluminum content ratio of each first type doped layer 110 is different, the pore size of the porous structure layer P can be adjusted by changing the aluminum content ratio of each first type doped layer 110, and then the refractive index of the porous structure layer P can be adjusted to change the reflectivity of the reflective portion 107. For example, the aluminum content ratio of the multiple first type doped layers 110 gradually changes along the stacking direction, and the refractive index of the multiple porous structure layers P after etching also gradually changes accordingly.

Since the first type doped layer 110 and the unintentional doped layer 111 have appropriate thicknesses respectively when growing the stack 105', during the electrochemical etching process, the first type doped layer 110 has sufficient thickness to form the porous structure layer P, and air can be filled in the porous structure layer P after the etching is completed. The unintentional doped layer 111 of the conductive region 106 has an appropriate thickness for carrier tunneling to conduct current.

As shown in FIG. 3D to FIG. 3F, after forming the reflective portion 107, the protective layer P1 is removed, and then the first type semiconductor layer 102 is exposed outside the recess 121 by dry etching or wet etching. Then in FIG. 3E, a current blocking layer 116 and a transparent conductive layer 115 are sequentially formed on the second type semiconductor layer 103. In FIG. 3F, a second electrode 114 is formed on the transparent conductive layer 115 and a first electrode 113 is formed on the first type semiconductor layer 102 exposed by the recess 121. When the substrate 101 is a wafer substrate, the epitaxial structure can be electrically separated and the wafer substrate can be cut to complete a plurality of light-emitting elements 100, i.e., light-emitting dies.

FIG. 3A to FIG. 3F are a method for manufacturing the light-emitting element 100 of the present application, but the present invention is not limited thereto. For example, before forming the first channel T of FIG. 3B or before forming the recess 121, the current blocking layer 116 and the transparent conductive layer 115 may be formed first. In addition, the stack 105' may be epitaxially grown between the second semiconductor layer 103 and the active region 104 to form the channel 108 and the stack 105' may be electrochemically etched to form the reflective portion 107. After selectively forming the transparent conductive layer 115, the semiconductor stack may be transferred to a conductive substrate (not shown) and the substrate 101 and the buffer layer 112 may be removed. Electrodes (not shown) may be formed on the first semiconductor layer 102 to form a vertical element. Alternatively, the stack 105' is similarly disposed between the second type semiconductor layer 103 and the active region 104, and after completing the process similar to FIG. 3B to FIG. 3E, an insulating structure (not shown) is covered on the semiconductor stack, and then an electrode pad (not shown) is formed on the insulating structure, which is respectively conductive to the first type semiconductor layer 102 and the second type semiconductor layer 103, so as to form a flip-chip device that can emit light from the substrate 101 after power is applied.

FIG4 shows a schematic cross-sectional view of a light-emitting package 2P of an embodiment of the present application. As shown in FIG4 , the light-emitting package 2P includes a main body 16 having a cavity 15, a first lead terminal 50a and a second lead terminal 50b disposed under the main body 16, a light-emitting element 100, a lead 14, and a packaging material 23. The cavity 15 may include an opening structure that is recessed from the top surface of the main body 16. The light-emitting element 100 may include a light-emitting element of any of the above-mentioned embodiments. In one embodiment, the side wall of the main body 16 may include a reflective structure (not shown). The first lead terminal 50a is disposed in a first area of the bottom area of the cavity 15, and the second lead terminal 50b is disposed in a second area of the bottom area of the cavity 15, and the first lead terminal 50a and the second lead terminal 50b are separated from each other in the cavity 15. The light-emitting element 100 is disposed on at least one of the first lead terminal 50a and the second lead terminal 50b. For example, the light-emitting element 100 can be disposed on the first lead terminal 50a, and the light-emitting element 100 is electrically connected to the first lead terminal 50a and the second lead terminal 50b by using the wire 14. The packaging material 23 is disposed in the cavity 15 and covers the light-emitting element 100. The packaging material 23 includes, for example, silicon or epoxy resin, and its structure can be a single layer or multiple layers. In one embodiment, the packaging material 23 can further include a wavelength conversion material for changing the wavelength of the light generated by the light-emitting element 100, such as a fluorescent powder, and/or a scattering material. The light-emitting package 2P can be applied to a backlight unit, a lighting unit, a display device, an indicator, a lamp, a street lamp, a lighting device for a vehicle, a display device for a vehicle, or a smart watch, but is not limited thereto.

FIG5 shows a schematic cross-sectional view of a light-emitting device 1A of an embodiment of the present application. The light-emitting device 1A includes a light-emitting element 50 mounted on a circuit board 52, and the circuit board is in the shape of a long flat plate. The light-emitting element 50 can be any of the light-emitting elements in the above-mentioned embodiments. In addition, the light-emitting element 50 can also be the light-emitting package 2P shown in the embodiment of FIG4. A plurality of light-emitting elements 50 are arranged on one side of the circuit board 52, and are arranged spaced apart from each other along the longitudinal direction of the circuit board 52. A heat sink 58 is provided on the other side of the circuit board 52 to dissipate the heat generated by the light-emitting element 50, and a transparent cover 56 is provided on the side where the light-emitting element 50 is provided, which is made of a material that allows the light emitted by the light-emitting element 50 to easily penetrate. In addition, terminals 54 are provided at both ends of the light-emitting device 1A to connect to a power source to provide power to the circuit board 52.

It should be noted that the embodiments listed in this application are only used to illustrate this application and are not used to limit the scope of this application. Any obvious modifications or changes made to this application by anyone do not deviate from the spirit and scope of this application. The same or similar components in different embodiments, or components with the same number in different embodiments, all have the same physical or chemical properties. In addition, the above embodiments in this application can be combined or replaced with each other under appropriate circumstances, rather than being limited to the specific embodiments described. The connection relationship between a specific component and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of the scope of protection of the rights of this application as described below.

100: Light-emitting element

101:Substrate

102: Type I semiconductor layer

103: Type II semiconductor layer

104: Active area

105: Stacked structure

106: Conductive area

107: Reflection part

108: Channel

110: Type I doping layer

111: Unintentional adulteration

111a: Top floor

111b: bottom layer

112: Buffer layer

113: First electrode

114: Second electrode

115:Transparent conductive layer

116: Current blocking layer

121: concave part

L:Light

P: porous structure layer

X: Lateral

Y: Stacking direction

Claims (10)

A light-emitting element comprises: a first-type semiconductor layer; a second-type semiconductor layer located on the first-type semiconductor layer along a stacking direction; an active region located between the first-type semiconductor layer and the second-type semiconductor layer along the stacking direction; and a stacking structure located between the first-type semiconductor layer and the active region along the stacking direction and having a conductive region and a plurality of reflective portions; wherein the reflective portions are spaced and distributed in the conductive region upward on a side perpendicular to the stacking direction. The light-emitting element as described in claim 1 further includes a plurality of channels corresponding to the reflective portions, each of the channels passes through the second type semiconductor layer and the active region and enters the stacked structure, and each of the reflective portions surrounds each of the channels. A light-emitting element as described in claim 2, wherein the channel does not penetrate the stacked structure. The light-emitting element as described in claim 1, wherein the conductive region of the stacked structure is formed by stacking a pair of semiconducting layers consisting of a plurality of first-type doped layers and a plurality of unintentionally doped layers, and each of the reflective portions is formed by stacking a pair of reflective layers consisting of a plurality of porous structure layers and the unintentionally doped layers. The light-emitting element as described in claim 4, wherein the first-type doped layers are n-type aluminum-gallium nitride series semiconductor layers, and the unintentionally doped layers are aluminum-gallium nitride series semiconductor layers. The light-emitting element as described in claim 5, wherein the aluminum-gallium nitride series semiconductor layers corresponding to the first-type doped layers and the unintentionally doped layers are aluminum-gallium nitride semiconductor layers, and the first-type doped layers have an aluminum content ratio between 5% and 15%. The light-emitting element as described in claim 4, wherein the stacked structure is connected to the active region with a top layer of the unintentional doping layers, and is connected to the first type semiconductor layer with a bottom layer of the unintentional doping layers. The light-emitting element as described in claim 4, wherein the porous structure layers are respectively connected to the first type doped layers of the conductive region on the side. The light-emitting element as described in claim 1 further includes a substrate and a buffer layer, the first type semiconductor layer is located on the substrate, and the buffer layer is located between the substrate and the first type semiconductor layer. The light-emitting element as described in claim 9, wherein the active region is suitable for emitting light with a main wavelength less than 365 nanometers, and the absorption rate of the first type semiconductor layer and/or the buffer layer for the light is between 0.42 and 0.55.

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