TWI887572B - Circuit path simplifying method and system thereof - Google Patents

Abstract

A circuit path simplifying method and a system thereof are proposed. An initial path sequence obtaining step is performed to obtain a plurality of initial path sequences. Each of the initial path sequences includes a plurality of component labels and a plurality of path labels, and the component labels and the path labels are alternately arranged with each other. A path label searching step is performed to search for the same path label to generate a path label confirming result. A component label comparing step is performed to compare whether two component labels adjacent to the same path label are identical according to the path label confirming result. In response to determining that the two component labels are identical, a merging step is performed to generate a merged component label and a merged path label. In response to determining that the two component labels are not identical, the arranging step is performed to generate an arranged component label and the merged line label. Therefore, the initial path sequences are simplified into a simplified path sequence.

Description

Circuit path simplification method and system

The present invention relates to an electronic digital data processing technology, and more particularly to a circuit path simplification method and system thereof.

As circuits become more complex, it is inconvenient to determine whether two electronic components are connected in a circuit diagram, or to determine the bias voltage or current flowing through a certain electronic component. The above process is not only time-consuming, but may also lead to human errors. If computer software is used to assist in the judgment, the circuit diagram needs to be converted into text data for computer calculation and processing. Although commercial computer software has data conversion formats and internal processing procedures, they are usually trade secrets and cannot be disclosed to the public. Academic circuit representation methods, such as the Simulation Program with Integrated Circuit Emphasis (SPICE), can show the connection relationship between the various electronic components on the circuit diagram, but the connection relationship is not intuitive and cannot be quickly identified during the search process.

When the line search between two electronic components is completed, multiple paths usually appear. The lines on the path sometimes appear on the paths between other electronic components. This parallel circuit relationship can be used to determine the voltage/current division or signal division on the component. However, it still takes a lot of time to manually search for parallel relationships in the circuit diagram. When the circuit is complex and the number of electronic components is large, manual search becomes difficult.

In view of this, how to develop a method and system that can display whether there is a parallel relationship between circuits and can simplify multiple paths is indeed a goal and direction that requires hard work and breakthrough research and development.

Therefore, the purpose of the present invention is to provide a circuit path simplification method and system, which uses an initial path sequence formed by component labels and line labels to simply present the connection relationship of the circuit path, and then merges the line labels and arranges the component labels according to the same line labels in multiple initial path sequences, thereby simplifying multiple initial path sequences into simplified path sequences.

According to an embodiment of the present invention, a circuit path simplification method is provided, which is used to simplify a plurality of initial path sequences corresponding to a circuit diagram, and the circuit diagram includes a plurality of electronic components and a plurality of circuits. The circuit path simplification method includes an initial path sequence acquisition step, a circuit label search step, and a component label matching step. The initial path sequence acquisition step is to drive an operation processing unit to obtain these initial path sequences corresponding to the circuit diagram from a storage unit. Each initial path sequence includes a plurality of component labels corresponding to a portion of these electronic components and a plurality of circuit labels corresponding to a portion of these circuits, and these component labels and these circuit labels are arranged alternately with each other. The circuit label search step drives the operation processing unit to search for the same circuit label in these initial path sequences to generate a circuit label confirmation result. The component label comparison step drives the operation processing unit to compare whether two component labels in adjacent columns of one of the circuit labels in two of the initial path sequences are the same according to the circuit label confirmation result, so as to simplify these initial path sequences. When the two component labels are the same, the operation processing unit is driven to execute a merging step. The merging step merges the two component labels of two of the initial path sequences to generate a merged component label, and merges one of the circuit labels of two of the initial path sequences to generate a merged circuit label. The merged component label and the merged line label are arranged to form a simplified path sequence. When the two component labels are different, the operation processing unit is driven to execute an arrangement step. The arrangement step arranges the two component labels of the two initial path sequences to generate an arranged component label, and merges one line label of the two initial path sequences to generate a merged line label. The arranged component label and the merged line label are arranged to form another simplified path sequence.

According to another embodiment of the present invention, a circuit path simplification system is provided, which is used to simplify a plurality of initial path sequences corresponding to a circuit diagram, and the circuit diagram includes a plurality of electronic components and a plurality of circuits. The circuit path simplification system includes a storage unit and an operation processing unit. The storage unit stores these initial path sequences corresponding to the circuit diagram. Each initial path sequence includes a plurality of component labels corresponding to a portion of these electronic components and a plurality of circuit labels corresponding to a portion of these circuits, and these component labels and these circuit labels are arranged alternately with each other. The operation processing unit is connected to the storage unit and obtains these initial path sequences, and the operation processing unit is configured to implement a circuit label search step and a component label comparison step. The line label search step is to search for the same one of the line labels in these initial path sequences to generate a line label confirmation result. The component label comparison step is to compare whether the two component labels in the adjacent line labels in two of the initial path sequences are the same based on the line label confirmation result, so as to simplify these initial path sequences. When the two component labels are the same, the operation processing unit executes a merging step. The merging step is to merge the two component labels of two of the initial path sequences to generate a merged component label, and merge one of the line labels of two of the initial path sequences to generate a merged line label. The merged component label and the merged line label are arranged to form a simplified path sequence. When the two component labels are different, the operation processing unit executes an arrangement step. The arrangement step arranges the two component labels of the two initial path sequences to generate an arranged component label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The arranged component label and the merged line label are arranged to form another simplified path sequence.

Thus, the circuit path simplification method and system of the present invention finds the same line labels in all initial path sequences, then merges the same component labels to generate merged component labels, or arranges different component labels to generate arranged component labels, and merges the same line labels to generate merged line labels, thereby simplifying multiple initial path sequences into simplified path sequences.

Please refer to FIG. 1 and FIG. 2 together, wherein FIG. 1 is a schematic diagram showing the process of the circuit path simplification method 100 according to the first embodiment of the present invention; and FIG. 2 is a schematic diagram showing the circuit path simplification method 100 of the present invention applied to a plurality of initial path sequences I ₁ , I ₂ , I ₃ , I ₄ , I _5. As shown in the figure, the circuit path simplification method 100 includes an initial path sequence acquisition step S02, a line label search step S04 and a component label comparison step S06, and is used to simplify the initial path sequences I ₁ , I ₂ , I ₃ , I ₄ , I ₅ of the corresponding circuit diagram into a simplified path sequence S ₁ .

The initial path sequence acquisition step S02 is to drive the operation processing unit to acquire the initial path sequence I ₁ , I ₂ , I ₃ , I ₄ , I ₅ corresponding to the circuit diagram from the storage unit. The circuit diagram includes a plurality of electronic components and a plurality of circuits. The initial path sequence I ₁ , I ₂ , I ₃ , I ₄ , I ₅ includes a plurality of component labels E ₁ , E ₂ , E ₃ , E ₄ , E ₅ , E ₆ , E ₇ corresponding to the aforementioned electronic components and a plurality of circuit labels P ₁ , P ₂ , P ₃ corresponding to the aforementioned circuits. Specifically, the initial path sequence _I1 in FIG. 2 includes component labels _E1 , _E2 , _E3 and circuit labels _P1 , _P2 , _P3 , and the component labels _E1 , _E2 , _E3 and circuit labels _P1 , _P2 , _P3 are arranged alternately from front to back (i.e., from left to right). The adjacently arranged component label _E1 and circuit label _P1 can indicate that the electronic component corresponding to the component label _E1 is electrically connected to the circuit corresponding to the circuit label _P1 , and other initial path sequences are similar. In addition, the aforementioned circuit diagram can be drawn by drawing software (Allegro) and converted into an XML data file through the drawing software, which can include all electronic component data and circuit data connecting two electronic components. All the combinations of electronic components and circuits in the circuit diagram are found manually or by software, so as to rearrange the electronic component data and circuit data in the XML data file and generate digital data based on the JavaScript Object Notation (JSON) format (i.e., the initial path sequence I ₁ , I ₂ , I ₃ , I ₄ , I ₅ ).

The circuit label search step S04 drives the operation processing unit to search for the same circuit label in all initial path sequences I ₁ , I ₂ , I ₃ , I ₄ , I ₅ to generate at least one circuit label confirmation result 110. As shown in FIG. 2 , since the initial path sequences I ₁ , I ₂ , I ₃ , I ₄ , I ₅ all have the same circuit labels P ₁ , P ₂ , P ₃ , the operation processing unit generates a plurality of circuit label confirmation results 110 corresponding to the circuit labels P ₁ , P ₂ , P ₃ , respectively.

The component label comparison step S06 is to drive the operation processing unit to compare the two component labels E1 adjacent to the circuit label _P1 in the two initial path sequences _I1 and _I2 according to the circuit label confirmation result 110 corresponding to the circuit label _P1 to see whether _they are the same. It should be noted that the operation processing unit includes all initial path sequences with the line label _P1 in the comparison process; in other words, the operation processing unit can also phase-by-phase compare whether multiple component labels _E1 , _{E2 , E3} , E4, _E5 , E6, _E7 adjacent to the line labels _P1 , _P2 , _P3 in all initial path sequences _I1 , _I2 , _I3 , _I4 , _I5 are the same according to all _the line label confirmation results 110. When two component labels are the same, the operation processing unit is driven to execute the merging step S062. The merging step S062 is to merge the two component labels of the two initial path sequences to generate a merged component label, and merge the line labels of the two initial path sequences to generate a merged line label. When the two component labels are different, the operation processing unit is driven to execute the arrangement step S064. The arrangement step S064 is to arrange the two component labels of the two initial path sequences to generate an arranged component label, and merge the line labels of the two initial path sequences to generate a merged line label.

For example, the multiple component labels _E1 located before the line label _P1 in all the initial path sequences _I1 , _I2 , _I3 , _I4 , and _I5 are the same, and the operation processing unit executes the merging step S062. The merging step S062 drives the operation processing unit to merge the multiple component labels _E1 located before the line label _P1 to generate a merged component label _ME1 , and merge the line labels _P1 of all the initial path sequences _I1 , _I2 , _I3 , _I4 , and _I5 to generate a merged line label _MP1 . The operation processing unit lists the merged component label _ME1 before the merged line label _MP1 . Similarly, in all initial path sequences I ₁ , I ₂ , I ₃ , I ₄ , and I ₅ , the multiple component labels E ₂ located after the line label P ₁ are the same, and the operation processing unit also executes the merging step S062. The merging step S062 drives the operation processing unit to merge the multiple component labels E ₂ located after the line label P ₁ to generate a merged component label _ME2 . The operation processing unit lists the merged component label _ME2 after the merged line label _MP1 .

If the multiple component labels E2 located before the line label _P2 in all the initial path sequences _I1 , _I2 , _I3 , _I4 , _I5 are the same, the operation processing unit generates a merged component label _ME2 , and merges the line labels _P2 of all the initial path sequences _I1 , _I2 , _I3 , _{I4 , I5} to generate a merged line label _MP2 . The operation processing unit lists the _merged component label _ME2 before the merged line label _MP2 .

In particular, the component labels _E3 , E4, _E5 , _E6 , and _E7 after the line label _P2 in all the initial path sequences _I1 , _I2 , _I3 , _I4 , and _I5 are different from each other, and the operation processing unit executes the arrangement step S064. The arrangement step S064 drives the operation processing unit to arrange the component _{labels E3} , _E4 , _E5 , _E6 , and _E7 in sequence to generate the arranged component label A _E1 . The operation processing unit arranges the arranged component label A _E1 after the merged line label _MP2 .

If the component labels _E3 , _E4 , _E5 , _E6 , and E7 before the line label _P3 in all the initial path sequences _I1 , _I2 , _I3 , _I4 , and _I5 are different from each other, the operation processing unit executes the arrangement step S064. _The arrangement step S064 drives the operation processing unit to arrange the component labels _E3 , _E4 , _E5 , _E6 , and _E7 in sequence to generate the arranged component label A _E1 , and merge the line label _P3 of all _the initial path sequences _I1 , _I2 , _I3 , _I4 , and _I5 to generate the merged line label _MP3 . The operation processing unit arranges the arranged component label A _E1 before the merged line label _MP3 . Finally, the operation processing unit arranges the merged component label _ME1 , the merged line label _MP1 , the merged component label _ME2 , the merged line label _MP2 , the arranged component label A _E1 and the merged line label _MP3 in sequence to form a simplified path sequence _S1 .

Furthermore, the operation processing unit introduces the first symbol Q ₁ in the merged circuit label _MP1 . The first symbol Q ₁ is located before the circuit label P _1. The first symbol Q ₁ represents a series connection, that is, the circuit corresponding to the circuit label P ₁ is connected in series with the electronic component corresponding to the component label E ₁ , and at the same time represents that the electronic component corresponding to the component label E ₁ is connected in series with the electronic component corresponding to the component label E ₂ via the circuit corresponding to the circuit label P _1. The operation processing unit introduces the second symbol Q ₂ in the merged circuit label _MP2 . The second symbol Q ₂ is located before the circuit label P ₂ . The second symbol _Q2 represents parallel connection, that is, the circuit corresponding to the circuit label _P2 is connected in parallel with the electronic components corresponding to the component labels _E3 , _E4 , _E5 , _E6 , and _E7 , and at the same time, it represents that the electronic component corresponding to _the component label _E2 is connected in parallel with the electronic components corresponding to the component labels _E3 , _E4 , _E5 , _E6 , and _E7 corresponding to the circuit label _P2 , and the same applies to the merged circuit label MP3.

It is worth noting that the digital data of the aforementioned merged component label is equivalent to the digital data of the component label before the merge; that is, the JSON data corresponding to the merged component label _ME1 is equivalent to the JSON data corresponding to the component label _E1 , and the other merged component labels are similar and will not be elaborated on. Therefore, the operation processing unit can convert the simplified path sequence _S1 of the corresponding circuit diagram into a simplified circuit diagram _C1 . From the simplified circuit diagram _C1 of Figure 2, it can be seen that the electronic component corresponding to the component label _E1 and the electronic component corresponding to the component label _E2 are connected in series through the line corresponding to the line label _P1 . The electronic component corresponding to the component label _E2 and the electronic components corresponding to the component labels _E3 , _E4 , _E5 , _E6 , and _E7 are connected in parallel to each other via the circuit corresponding to the circuit label _P2 . All component labels _E3 , _E4 , _E5 , _E6 , and _E7 are connected in parallel to the circuit corresponding to the circuit label _P3 . Thus, the circuit path simplification method 100 of the present invention can find the same line labels _P1 , _P2 , P3 in all initial path sequences _I1 , _I2 , _I3 , _I4 , _I5 , and then generate the merged component labels _ME1 , _ME2 respectively by merging the same component labels _E1 , _E2 , or generate _the arranged component label A _E1 by arranging different component labels _E3 , _E4 , _E5 , _E6 , _E7 , and merge the same line labels _P1 , _P2 , _P3 to generate the merged line labels _MP1 , _MP2 , _MP3 respectively, and then all the initial path sequences _I1 , _I2 , _I3 , _I4 , I5 are combined. ₅ is simplified to a simplified path sequence S ₁ , so that the user can more easily understand the connection relationship between each component and each circuit in the simplified circuit diagram C _1. Therefore, when the circuit in the circuit diagram is more complicated, the user can still use the simplified path sequence S ₁ to easily view and judge the voltage division/current division or signal division on the electronic component.

Please refer to FIG. 1 and FIG. 3 together, wherein FIG. 3 is another schematic diagram showing the circuit path simplification method 100 of the present invention applied to multiple initial path sequences I ₆ and I _7. As shown in the figure, the circuit label search step S04 drives the operation processing unit to search for the same circuit label in two initial path sequences I ₆ and I ₇ corresponding to another circuit diagram to generate a circuit label confirmation result 110. As can be seen from FIG. 3, since the initial path sequences I ₆ and I ₇ both list the same circuit labels P ₁ and P ₂ , the operation processing unit generates circuit label confirmation results 110 corresponding to the circuit labels P ₁ and P ₂ respectively. The following only introduces in detail the line label confirmation result 110 corresponding to the line label _P1 , and other line label confirmation results 110 are not described separately.

The component label comparison step S06 drives the operation processing unit to compare whether the two component labels _E1 in the two initial path sequences _I6 and _I7 that are adjacent to the line label _P1 are the same according to the line label confirmation result 110 corresponding to the line label _P1 , and compare whether the two component labels _E2 and _E3 in the two initial path sequences _I6 and _I7 that are adjacent to the line label _P1 are the same. If the two component labels E1 in the two initial path sequences _I6 and _I7 that are located before _the line label _P1 are the same, the operation processing unit executes the merging step S062. The merging step S062 drives the operation processing unit to merge the two component labels _E1 located before the line label _P1 to generate a merged component label _ME1 , and merge the line label _P1 of the two initial path sequences _I6 and _I7 to generate a merged line label _MP4 . The operation processing unit arranges the merged component label _ME1 before the merged line label _MP4 . The component labels _E2 and _E3 located after the line label _P1 in the two initial path sequences _I6 and _I7 are different, and the operation processing unit executes the arrangement step S064. The arrangement step S064 drives the operation processing unit to arrange the component label _E2 and the circuit label _P2 in sequence to generate the arranged component label A _E2 , and to arrange the component label _E3 , the circuit label _P3 , the component label _E4 and the circuit label _P2 in sequence to generate the arranged component label A _E3 . The operation processing unit arranges the arranged component label A _E2 after the merged circuit label _MP4 , and arranges the arranged component label A _E3 after the arranged component label A _E2 to form a simplified path sequence S ₂ .

In addition, the operation processing unit introduces the second symbol Q ₂ in the merged circuit label _MP4 . The second symbol Q ₂ is located before the circuit label P _1. The second symbol Q ₂ represents parallel connection, that is, the electronic component corresponding to the component label E ₁ is connected in parallel with the electronic components corresponding to the component labels E ₂ and E ₃ via the circuit corresponding to the circuit label P _1. The operation processing unit introduces the first symbol Q ₁ before the circuit label P ₃ , which represents series connection, that is, the electronic component corresponding to the component label E ₃ is connected in series with the electronic component corresponding to the component label E ₄ via the circuit corresponding to the circuit label P _3. Therefore, the operation processing unit can convert the simplified path sequence S ₂ corresponding to another circuit diagram into the simplified circuit diagram C ₂ . From the simplified circuit diagram _C2 of FIG. 3, it can be seen that the electronic component corresponding to the component label _E1 is connected in parallel to the electronic components corresponding to the component labels _E2 and _E3 after the circuit corresponding to the circuit label _P1 . The electronic component corresponding to the component label _E3 is connected in series to the electronic component corresponding to the component label _E4 after the circuit corresponding to the circuit label _P3 , and the electronic components corresponding to the component labels _E2 and _E4 are connected in series to the circuit corresponding to the circuit label _P2 .

Please refer to FIG. 1 and FIG. 4 together, wherein FIG. 4 is another schematic diagram showing the circuit path simplification method 100 of the present invention applied to multiple initial path sequences I ₈ , I ₉ , I ₁₀ , I _11. As shown in the figure, the circuit label search step S04 drives the operation processing unit to search for the same circuit label in the initial path sequence I ₈ , I ₉ , I ₁₀ , I ₁₁ corresponding to another circuit diagram to generate a circuit label confirmation result 110. As can be seen from FIG. 4, since the initial path sequences _I8 , _I9 , _I10 , and _I11 all have the same line labels _P1 , _P2 , and _P3 , the operation processing unit generates line label confirmation results 110 corresponding to the line labels _P1 , _P2 , and _P3, respectively. The following only introduces the line label confirmation results 110 corresponding to the line labels _P1 and _P2 in detail, and the line label confirmation result 110 corresponding to the line label _P3 is not described separately.

If the circuit label P ₁ is taken as the center, the component label comparison step S06 drives the operation processing unit to compare the four component labels E ₁ adjacent to the circuit label P ₁ in the initial path sequence I ₈ , I ₉ , I ₁₀ , and I ₁₁ according to the circuit label confirmation result 110 corresponding to the circuit label P ₁ to see if they are the same, and to compare the two component labels E ₂ and the two component labels E ₃ adjacent to the circuit label P ₁ to see if they are the same. If the four component labels E ₁ in the initial path sequence I ₈ , I ₉ , I ₁₀ , and I ₁₁ before the circuit label P ₁ are all the same, the operation processing unit executes the merging step S062. The merging step S062 drives the operation processing unit to merge the four component labels _E1 located before the circuit label _P1 to generate a merged component label _ME1 , and the operation processing unit merges the circuit labels _P1 of the initial path sequence _I8 , _I9 , _I10 , and _I11 to generate a merged circuit label _MP4 , wherein the operation processing unit introduces the second symbol _Q2 into the merged circuit label _MP4 , and lists the merged circuit label _MP4 after the merged component label _ME1 .

In the initial path sequence I ₈ , I ₉ , I ₁₀ , I ₁₁ , the two component labels E ₂ and the two component labels E ₃ located after the line label P ₁ are the same, and the operation processing unit executes the merging step S062. The merging step S062 drives the operation processing unit to merge the two component labels E ₂ to generate a merged component label M _E2 , and merge the two component labels E ₃ to generate a merged component label M _E3 . Then, since the merged component label M _E2 and the merged component label M _E3 are different from each other, the operation processing unit executes the arrangement step S064. The arrangement step S064 is to drive the operation processing unit to arrange the merged component label _ME2 and the merged component label _ME3 to generate an arranged component label _AE4 .

If the circuit label P ₂ is taken as the center, the component label comparison step S06 drives the operation processing unit to compare the two component labels E ₂ and the two component labels E ₃ adjacent to the circuit label P ₂ in the initial path sequence I ₈ , I ₉ , I ₁₀ , and I ₁₁ according to the circuit label confirmation result ₁₁₀ corresponding to the circuit label P 2 to see if they are the same, and to compare the two component labels E ₄ and the two component labels E ₅ adjacent to the circuit label P ₂ to see if they are the same. The simplified process for the two component labels E ₂ and the two component labels E ₃ is as described above, so it will not be described separately.

In the initial path sequence _I8 , _I9 , _I10 , _I11 , the two component labels _E4 and the two component labels _E5 after the line label _P2 are the same, and the operation processing unit executes the merging step S062. The merging step S062 drives the operation processing unit to merge the two component labels _E4 to generate a merged component label _ME4 , and merge the two component labels _E5 to generate a merged component label _ME5 . The operation processing unit merges the line label _P2 of the initial path sequence _I8 , _I9 , _I10 , _I11 to generate a merged line label _MP2 , wherein the operation processing unit introduces the second symbol _Q2 into the merged line label _MP2 . Then, since the merged component label _ME4 and the merged component label _ME5 are different from each other, the operation processing unit executes the arrangement step S064. The arrangement step S064 drives the operation processing unit to arrange the merged component label _ME4 and the merged component label _ME5 to generate an arranged component label A _E5 , and the operation processing unit arranges the merged line label _MP2 between the arranged component labels A _E4 and A _E5 . Finally, the operation processing unit sequentially arranges the merged component label _ME1 , the merged line label _MP4 , the arranged component label _AE4 , the merged line label _MP2 , the arranged component label _AE5 , the merged line label _MP3 and the merged component label _ME6 to form a simplified path sequence _S3 .

Therefore, the operation processing unit can convert the simplified path sequence _S3 corresponding to another circuit diagram into a simplified circuit diagram _C3 . From the simplified circuit diagram _C3 of Figure 4, it can be seen that the electronic component corresponding to the component label _E1 is connected in parallel to the electronic components corresponding to the component labels _E2 and _E3 after the line corresponding to the line label _P1 . The electronic components corresponding to the component labels _E2 and _E3 are connected in parallel to the electronic components corresponding to the component labels _E4 and _E5 through the line corresponding to the line label _P2 . The electronic components corresponding to the component labels _E4 and _E5 are connected in parallel to the line corresponding to the line label _P2 , and the electronic component corresponding to the component label _E6 is connected in series through the line corresponding to the line label _P3 .

Please refer to FIG. 1 and FIG. 5 together, wherein FIG. 5 is a schematic diagram of a circuit path simplification system 200 according to a second embodiment of the present invention. As shown in the figure, the circuit path simplification system 200 is used to simplify a plurality of initial path sequences 212 corresponding to a circuit diagram 211, and includes a storage unit 210 and an operation processing unit 220. The storage unit 210 stores the circuit diagram 211 and these initial path sequences 212 corresponding to the circuit diagram 211. The operation processing unit 220 is electrically connected to the storage unit 210 and obtains these initial path sequences 212. The operation processing unit 220 is configured to implement the circuit label search step S12, the component label comparison step S14, the merging step S142 and the arranging step S144, which are the same as the corresponding steps of the circuit path simplification method 100 in the first embodiment and are not further described. In addition, the operation processing unit 220 can be a digital signal processor (DSP), a microprocessor (MPU), a central processing unit (CPU) or other electronic processors, but the present invention is not limited thereto.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100: Circuit path simplification method 110: Circuit label confirmation result 200: Circuit path simplification system 210: Storage unit 220: Operation processing unit 211: Circuit diagram 212, I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ , I ₇ , I ₈ , I ₉ , I ₁₀ , I ₁₁ : Initial path sequence E ₁ , E ₂ , E ₃ , E ₄ , E ₅ , E ₆ , E ₇ : Component label P ₁ , P ₂ , P ₃ : Circuit label _ME1 , _ME2 , _ME3 , _ME4 , _ME5 , _ME6 : Merged component label _MP1 , _MP2 , _MP3 , MP4 _P4 : Merged circuit labels A _E1 , A _E2 , A _E3 , A _E4 , A _E5 : Arranged component labels Q ₁ : First symbol Q ₂ : Second symbol S ₁ , S ₂ , S ₃ : Simplified path sequence C ₁ , C ₂ , C ₃ : Simplified circuit diagram S02: Initial path sequence acquisition step S04, S12: Circuit label search step S06, S14: Component label comparison step S062, S142: Merge step S064, S144: Arrangement step

FIG. 1 is a schematic diagram showing a flow chart of a circuit path simplification method according to the first embodiment of the present invention; FIG. 2 is a schematic diagram showing the circuit path simplification method of the present invention applied to multiple initial path sequences; FIG. 3 is another schematic diagram showing the circuit path simplification method of the present invention applied to multiple initial path sequences; FIG. 4 is another schematic diagram showing the circuit path simplification method of the present invention applied to multiple initial path sequences; and FIG. 5 is a schematic diagram showing a circuit path simplification system according to the second embodiment of the present invention.

100: Circuit path simplification method

110: Line label confirmation result

S02: Initial path sequence acquisition step

S04: Line label search steps

S06: Component label comparison step

S062: Merge steps

S064: Arrangement steps

Claims (8)

A circuit path simplification method is used to simplify a plurality of initial path sequences corresponding to a circuit diagram, wherein the circuit diagram includes a plurality of electronic components and a plurality of circuits. The circuit path simplification method includes the following steps: an initial path sequence acquisition step, which drives an operation processing unit to acquire the initial path sequences corresponding to the circuit diagram from a storage unit, wherein each of the initial path sequences includes a plurality of component labels corresponding to a portion of the electronic components and a plurality of circuit labels corresponding to a portion of the circuits, wherein the component labels and the circuit labels are arranged alternately with each other; a circuit label search step, which drives the operation processing unit to search for the same circuit labels in the initial path sequences. and generating a circuit label confirmation result according to one of the circuit labels; and a component label comparison step, which drives the operation processing unit to compare whether the two component labels of the adjacent ones of the circuit labels in the two initial path sequences are the same, so as to simplify the initial path sequences; wherein, when the two component labels are the same, the operation processing unit is driven to execute a merging step, which is to merge the two component labels of the two initial path sequences to generate a merged component label, and merge the one of the circuit labels of the two initial path sequences to generate a merged circuit label, the merged circuit label The component label and the merged circuit label are arranged to form a simplified path sequence; wherein, when the two of the component labels are different, the operation processing unit is driven to execute an arrangement step, the arrangement step is to arrange the two of the component labels of two of the initial path sequences to generate an arranged component label, and merge the one of the circuit labels of two of the initial path sequences to generate the merged circuit label, the arranged component label and the merged circuit label are arranged to form another simplified path sequence; wherein, the operation processing unit introduces one of a first symbol and a second symbol into the merged circuit label, the first symbol and the second symbol are The first symbol indicates that one of the electronic components corresponding to one of the component labels listed before the one of the circuit labels is connected in series with one of the electronic components corresponding to another component label listed after the one of the circuit labels via one of the circuits corresponding to the one of the circuit labels, and the second symbol indicates that one of the electronic components corresponding to the one of the component labels listed before the one of the circuit labels is connected in parallel with at least two electronic components corresponding to at least two component labels listed after the one of the circuit labels via the one of the circuits corresponding to the one of the circuit labels. A circuit path simplification method as described in claim 1, wherein one of the component labels and one of the circuit labels arranged adjacently indicate that one of the electronic components corresponding to the component labels is electrically connected to one of the circuits corresponding to the circuit labels. The circuit path simplification method as described in claim 1, wherein in the component label comparison step, when two of the component labels located before one of the line labels in two of the initial path sequences are the same, the merging step is to drive the operation processing unit to merge the two of the component labels located before the one of the line labels; and when two of the component labels located after the one of the line labels in two of the initial path sequences are the same, the merging step is to drive the operation processing unit to merge the two of the component labels located after the one of the line labels. The circuit path simplification method as described in claim 1, wherein in the component label comparison step, when two of the component labels located before one of the line labels in two of the initial path sequences are the same, the merging step is to drive the operation processing unit to merge the two of the component labels located before the one of the line labels; and when two of the component labels located after the one of the line labels in the two initial path sequences are different, the arranging step is to drive the operation processing unit to arrange the two of the component labels located after the one of the line labels. The circuit path simplification method as described in claim 1, wherein in the component label comparison step, when the two component labels located before the one of the circuit labels in two of the initial path sequences are different, the arrangement step is to drive the operation processing unit to arrange the two component labels located before the one of the circuit labels; and when the two component labels located after the one of the circuit labels in the two initial path sequences are the same, the merging step is to drive the operation processing unit to merge the two component labels located after the one of the circuit labels. The circuit path simplification method as described in claim 1, wherein in the component label comparison step, when two of the component labels located before one of the circuit labels in two of the initial path sequences are different, the arrangement step is to drive the operation processing unit to arrange the two of the component labels located before the one of the circuit labels; and when two of the component labels located after the one of the circuit labels in two of the initial path sequences are different, the arrangement step is to drive the operation processing unit to arrange the two of the component labels located after the one of the circuit labels. A circuit path simplification system is used to simplify a plurality of initial path sequences corresponding to a circuit diagram, wherein the circuit diagram includes a plurality of electronic components and a plurality of circuits. The circuit path simplification system includes: a storage unit, storing the initial path sequences corresponding to the circuit diagram, wherein each of the initial path sequences includes a plurality of component labels corresponding to a portion of the electronic components and a plurality of circuit labels corresponding to a portion of the circuits, wherein the component labels and the circuit labels are arranged alternately with each other; and an operation processing unit, connected to the storage unit and obtaining the initial path sequences, and the operation processing unit is configured to implement the following steps: a circuit label search step, which is performed on the initial path sequences; The method comprises the steps of searching for one of the identical circuit labels in the path sequence to generate a circuit label confirmation result; and a component label comparison step, which compares the two component labels of the adjacent circuit labels in two of the initial path sequences according to the circuit label confirmation result to determine whether the two component labels are identical, so as to simplify the initial path sequences; wherein, when the two component labels are identical, the operation processing unit executes a merging step, wherein the merging step is to merge the two component labels of the two initial path sequences to generate a merged component label, and merge the one of the circuit labels of the two initial path sequences to generate a merged circuit label, wherein the The merged component label and the merged circuit label are arranged to form a simplified path sequence; wherein, when the two of the component labels are different, the operation processing unit executes an arrangement step, the arrangement step is to arrange the two of the component labels of two of the initial path sequences to generate an arranged component label, and merge the one of the circuit labels of two of the initial path sequences to generate the merged circuit label, the arranged component label and the merged circuit label are arranged to form another simplified path sequence; wherein, the operation processing unit introduces one of a first symbol and a second symbol into the merged circuit label, the first symbol and the second symbol The first symbol indicates that one of the electronic components corresponding to one of the component labels listed before the one of the circuit labels is connected in series with one of the electronic components corresponding to another component label listed after the one of the circuit labels through one of the circuits corresponding to the one of the circuit labels, and the second symbol indicates that one of the electronic components corresponding to the one of the component labels listed before the one of the circuit labels is connected in parallel with at least two electronic components corresponding to at least two component labels listed after the one of the circuit labels through the one of the circuits corresponding to the one of the circuit labels. A circuit path simplification system as described in claim 7, wherein one of the component labels and one of the circuit labels arranged adjacently indicate that one of the electronic components corresponding to the component labels is electrically connected to one of the circuits corresponding to the circuit labels.

Images