TWI882699B - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separated conductive structure and a source metal layer. The silicon carbide substrate has a first region and has a first conductivity type. The epitaxial layer is disposed on a top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is disposed in the epitaxial layer in the first region and extends along the first direction. The separated conductive structure is disposed in the epitaxial layer in the first region. The separated conductive structure includes a first conductive feature and a second conductive feature separated from each other. The first conductive feature and the second conductive feature are located on opposite sidewalls of the first electrode. The source metal layer is disposed on the epitaxial layer in the first region. The source metal layer covers and is electrically connected to the first conductive feature, the second conductive feature and the first electrode.

Description

Semiconductor device and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a power transistor device of a Schottky diode and a method for forming the same.

The semiconductor industry continues to improve the integration density of different electronic components by continuously reducing the minimum component size so that more components can be integrated in a given area. For example, the trench gate metal-oxide-semiconductor field effect transistor (MOSFET), which is widely used in power switch components, uses a vertical structure design to reduce the cell pitch to improve functional density. It uses the back of the chip as the drain, and the source and gate of multiple transistors are made on the front of the chip. Therefore, the driving current develops from the flow in the planar direction to the flow in the vertical direction, which can also enable the semiconductor device to achieve high reverse withstand voltage and low on-resistance.

However, as the functional density requirements for semiconductor devices continue to increase, the complexity of the components integrated into semiconductor devices and their formation methods has also increased, and there are some electronic characteristics that trade off performance that need to be considered. Therefore, although existing semiconductor devices are generally suitable and sufficient to meet their intended purposes, they are not completely satisfactory in all aspects.

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a separated conductive structure, and a source metal layer. The silicon carbide substrate has a first region and has a first conductivity type. The epitaxial layer is disposed on the top surface of the silicon carbide substrate. The epitaxial layer has a first conductivity type. The first electrode is disposed in the epitaxial layer of the first region and extends along a first direction. The separated conductive structure is disposed in the epitaxial layer of the first region. The separated conductive structure includes a first conductive component and a second conductive component separated from each other and located on opposite side walls of the first electrode. The source metal layer is disposed on the epitaxial layer of the first region. The source metal layer covers and electrically connects the first conductive component, the second conductive component and the first electrode.

Some embodiments of the present invention provide a method for forming a semiconductor device. The method for forming a semiconductor device includes providing a silicon carbide substrate, the silicon carbide substrate having a first region and a first conductivity type; forming a first trench in an epitaxial layer of the first region along a first direction; forming a first electrode in the first trench, wherein the first electrode extends along the first direction; forming a separated conductive structure on opposite side walls of the first electrode, wherein the separated conductive structure includes first conductive components separated from each other. and a second conductive component; forming an interlayer dielectric layer throughout; removing the interlayer dielectric layer on the top surface of the epitaxial layer in the first region to expose at least one of the first conductive component and the second conductive component and the first electrode from the remaining interlayer dielectric layer; and forming a source metal layer on the epitaxial layer in the first region, wherein the source metal layer covers and electrically connects the first electrode, the first conductive component and the second conductive component.

The present disclosure is more fully described below with reference to the drawings of embodiments of the present invention. However, the present disclosure may be implemented in a variety of different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements. It is understood that additional steps may be provided before, during, or after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

Various different embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When a first component is formed on a second component, the description may include embodiments in which the first and second components are directly in contact with each other, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact with each other. In addition, the embodiments of the present invention may use repeated component symbols in many examples. Such repetition is only for the purpose of simplification and clarity, and does not represent a specific relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below", "beneath", "below", "above", "upper" and other similar terms may be used in the following description to simplify the description of the relationship between one element or component and other elements or components as shown in the figures. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

In a shielded gate trench MOSFET (SGT MOSFET) cell array, a Schottky diode can be provided to bypass the reverse current flowing through the SGT MOSFET to the Schottky diode to improve the switching characteristics of the semiconductor device. However, the forward voltage drop (V _F ) of the known Schottky diode still needs to be further reduced. Therefore, it is necessary to seek a semiconductor device of a shielded gate trench MOSFET and a method for forming the same, which can solve or improve the above-mentioned problems.

FIG. 1A and FIG. 1B are cross-sectional schematic diagrams of a semiconductor device 500 according to some embodiments of the present invention. Specifically, FIG. 1A is a cross-sectional schematic diagram of different regions of the semiconductor device 500 according to some embodiments of the present invention. FIG. 1B is a cross-sectional schematic diagram of a cell region and a trench MOS barrier Schottky (TMBS) region of the semiconductor device 500 (FIG. 1A) according to some embodiments of the present invention, showing the device configuration at the boundary between the cell region and the trench MOS barrier Schottky (TMBS) region. In some embodiments, the semiconductor device 500 includes a power MOSFET and a Schottky diode, such as an isolated-gate trench MOSFET (SGT MOSFET) integrated with a trench Schottky diode region and having a split-gate structure. As shown in FIGS. 1A and 1B , the semiconductor device 500 includes a silicon carbide (SiC) substrate 100, an epitaxial layer 200, an electrode 220F1, an electrode 220F2, a split gate structure 230AG, a split conductive structure 230BG, and a source metal layer 254S. In FIG. 1 and subsequent figures, directions 300 and 310 are substantially parallel to the top surface 100T of the silicon carbide substrate 100, and can also be regarded as lateral directions; direction 320 is substantially perpendicular to the top surface 100T of the silicon carbide substrate 100, and can also be regarded as a longitudinal direction (or can be regarded as a channel length direction). In addition, direction 300 is perpendicular to directions 310 and 320, direction 310 is perpendicular to directions 300 and 320, and direction 320 (can also be regarded as a channel width direction) is perpendicular to directions 300 and 310.

As shown in FIGS. 1A and 1B, the silicon carbide substrate 100 has a top surface 100T and a bottom surface 100B. In addition, the silicon carbide substrate 100 has a first region 400, a second region 410, a third region 420, and a fourth region 430. In some embodiments, the first region 400 may be a cell region in which a power metal oxide semiconductor field effect transistor array is formed. The second region 410 may be a trench Schottky diode region (TMBS region), which may be connected in parallel with an isolation gate trench metal oxide semiconductor field effect transistor unit of the cell region to reduce the on-resistance of the semiconductor device, thereby reducing power loss. The third region 420 may be a gate pickup region in which a gate contact is formed. In addition, the fourth region 430 may be a termination region, which is used to surround the cell region and serve as a buffer region for the doped region in the cell region to prevent the device breakdown voltage at the cell region boundary from dropping sharply. In the following embodiments, in the cell region (first region 400), the structure of two isolated gate trench MOSFET units is used for illustration. In the trench Schottky diode region (second region 410), the gate connection region (third region 420) and the termination region (fourth region 430), the structure of a trench electrode (e.g., source electrode) is used for illustration. However, any number of isolated gate trench MOSFET units and trench electrodes may be disposed in the cell region, gate connection region, and terminal region, and are not limited to the embodiments described herein.

In some embodiments, the conductivity type of the silicon carbide substrate 100 can be P-type or N-type according to design requirements. In this embodiment, the silicon carbide substrate 100 can be doped to have a first conductivity type, such as N-type. In the application of vertical trench-gate MOSFET, the silicon carbide substrate 100 with the first conductivity type can be used as a drain region of the final semiconductor device 500.

The epitaxial layer 200 is disposed on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial layer 200 may be doped to have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the epitaxial layer 200 is an N-type epitaxial layer 200. In addition, the doping concentration of the epitaxial layer 200 (e.g., about 10 ¹⁵ -10 ¹⁶ atoms/cm ³ ) is less than the doping concentration of the silicon carbide substrate 100 (10 ¹⁹ -10 ²¹ atoms/cm ³ ). For example, when the silicon carbide substrate 100 is an N-type heavily doped (N+) silicon carbide substrate 100, the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200. In the application of a vertical trench-gate MOSFET, the epitaxial layer 200 having a first conductivity type can be used as a drift region of the final semiconductor device 500. In some embodiments, the epitaxial layer 200 includes silicon carbide.

The well region 234 of the semiconductor device 500 is located in the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430, and is close to the top surface 200T of the epitaxial layer 200. In other words, the epitaxial layer 200 of the trench Schottky diode region (the second region 410) does not have the well region 234. In some embodiments, the well region 234 may be doped with a dopant to have a second conductivity type opposite to the first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the well region 234 is a P-type well region 234. In addition, the above-mentioned dopant having the second conductivity type may include aluminum (Al), boron (B) or other suitable dopants. In some embodiments, the doping concentration of the well region 234 is greater than the doping concentration of the epitaxial layer 200 (e.g., about 10 ¹⁷ -10 ¹⁸ atoms/cm ³ ). In some embodiments, the well region 234 may be formed by an ion implantation process. In the application of the vertical trench gate metal oxide semiconductor field effect transistor, the well region 234 having the second conductivity type may serve as a channel region of the final semiconductor device 500.

The source region 236 of the semiconductor device 500 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. In addition, the second region 410, the third region 420, and the fourth region 430 may not have the source region 236. As shown in FIGS. 1A and 1B, the source region 236 is surrounded by the well region 234. In some embodiments, the source region 236 may be doped and have a first conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the source region 236 is an N-type source region 236. In addition, the doping concentration of the source region 236 is greater than the doping concentration of the epitaxial layer 200. For example, when the epitaxial layer 200 is an N-type lightly doped (N-) epitaxial layer 200 , the source region 236 is an N-type heavily doped (N+) source region 236 .

The semiconductor device 500 further includes a wiring doping region 238 (see also FIGS. 16 and 22 ). The wiring doping region 238 is located on the well region 234 in the first region 400 and is close to the top surface 200T of the epitaxial layer 200. Furthermore, the second region 410, the third region 420, and the fourth region 430 may not have the wiring doping region 238. As shown in FIG. 16 , the wiring doping region 238 is surrounded by the well region 234. The source region 236 and the wiring doping region 238 are adjacent to each other along the direction 310. Furthermore, in some embodiments, a plurality of source regions 236 and a plurality of wiring doping regions 238 are arranged in a staggered manner along the direction 310. The source region 236 and the wiring doping region 238 may have opposite conductivity types. For example, when the source region 236 has a first conductivity type, the wiring doping region 238 has a second conductivity type. The wiring doping region 238 and the well region 234 have the same conductivity type, for example, a P-type wiring doping region 238. In addition, the doping concentration of the wiring doping region 238 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234 , the wiring doping region 238 is a P-type heavily doped (P+) wiring doping region 238 to serve as the wiring doping region of the well region 234 .

The semiconductor device 500 further includes shielding dielectric layers 216AR, 216BR, 216CR, 216DR and electrodes 220F1, 220F2, 220F3, 220F4. As shown in FIGS. 1A and 1B, the shielding dielectric layer 216AR and the electrode 220F1 are disposed in the epitaxial layer 200 of the first region 400. The shielding dielectric layer 216AR is located below the top surface 200T of the epitaxial layer 200. The electrode 220F1 is on the shielding dielectric layer 216AR, and the shielding dielectric layer 216AR covers the bottom surface and the opposite sidewalls of the electrode 220F1. As shown in FIGS. 1A and 1B , the electrode 220F1 extends along a direction 320 toward the top surface 200T of the epitaxial layer 200 and the silicon carbide substrate 100. In some embodiments, in the direction 300, a width W1 of an upper portion (including the top portion 220F1-1) of the electrode 220F1 is smaller than a width W2 of a lower portion of the electrode 220F1.

As shown in FIG. 1A , the shielding dielectric layer 216BR and the electrode 220F2 are disposed in the epitaxial layer 200 in the second region 410. The electrode 220F2 extends from a position close to the top surface 200T of the epitaxial layer 200 toward the silicon carbide substrate 100 along the direction 320. The electrode 220F2 is located on the shielding dielectric layer 216BR, and the shielding dielectric layer 216BR covers the bottom surface and the opposite sidewalls of the electrode 220F2. In some embodiments, in the direction 300, the width W3 of the upper portion of the electrode 220F2 is smaller than the width W4 of the lower portion of the electrode 220F2. In some embodiments, width W1 may be equal to width W3, and width W2 may be equal to width W4.

As shown in FIG. 1A , the shielding dielectric layer 216CR and the electrode 220F3 are disposed in the epitaxial layer 200 in the third region 420. The electrode 220F3 extends from a position close to the top surface 200T of the epitaxial layer 200 toward the silicon carbide substrate 100 along the direction 320. The electrode 220F3 is located on the shielding dielectric layer 216CR, and the shielding dielectric layer 216CR covers the bottom surface and the opposite sidewalls of the electrode 220F3. In some embodiments, in the direction 300, the width W5 of the upper portion of the electrode 220F3 is smaller than the width W6 of the lower portion of the electrode 220F3. In some embodiments, width W5 may be equal to widths W1 and W3, and width W6 may be equal to widths W2 and W4.

As shown in FIG. 1A , the shielding dielectric layer 216DR and the electrode 220F4 are disposed in the epitaxial layer 200 in the fourth region 430. The fourth electrode 220F4 extends from a position close to the top surface 200T of the epitaxial layer 200 toward the silicon carbide substrate 100 along the direction 320. The electrode 220F4 is located on the shielding dielectric layer 216DR, and the shielding dielectric layer 216DR covers the bottom surface and the opposite sidewalls of the electrode 220F4. In some embodiments, in the direction 300, the electrode 220F4 has a uniform width W7. In some embodiments, the width W7 may be equal to the widths W1, W3, and W5.

In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, 216DR may include the same material. For example, the shielding dielectric layers 216AR, 216BR, 216CR, 216DR may include silicon oxide, other suitable semiconductor oxide materials, or a combination thereof. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, 216DR may be formed using a conformable deposition process, an oxidation process, or other suitable formation processes. In some embodiments, the oxidation process may be thermal oxidation, or other suitable processes. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma assisted chemical vapor deposition (PECVD), other suitable processes, or a combination thereof.

In some embodiments, the electrodes 220F1, 220F2, 220F3, and 220F4 may selectively include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the electrodes 220F1, 220F2, 220F3, and 220F4 are P-type electrodes 220F1, P-type electrodes 220F2, P-type electrodes 220F3, and P-type electrodes 220F4, respectively. Furthermore, the dopant of the second conductivity type may include aluminum (Al), boron (B), boron difluoride (BF ₂ ) or other suitable dopant. In some embodiments, electrodes 220F1, 220F2, 220F3, 220F4 are electrically connected to source contacts 250S1, 250S2.

In some embodiments, the electrode 220F1 of the first region 400 can not only reduce the gate-to-drain capacitance ( _Cgd ) to improve the switching characteristics of the semiconductor device 500, but also has a field plate function, so that the electric field distribution of the gate dielectric layer (such as the gate dielectric layer 224A shown in FIG. 1, which will be described below) close to the bottom of the separated gate structure 230AG is more uniform and the breakdown voltage is increased to improve the reliability of the gate dielectric layer. In some embodiments, the electrode 220F2 of the second region 410 also has a field plate function, so that the electric field distribution of the epitaxial layer (drift region) 200 is more uniform. By providing the electrodes 220F1 and 220F2, the doping concentration of the epitaxial layer (drift region) 200 can be further increased to reduce the on-resistance (R _onsp ) of the isolation gate trench MOSFET unit in the first region 400 and reduce the forward voltage (V _F ) of the trench Schottky diode in the second region 410 .

In the embodiment shown in FIGS. 1A and 1B , two separate gate structures 230AG are disposed in the epitaxial layer 200 of the first region 400 and are located above the lower portion of the electrode 220F1. The two separate gate structures 230AG are separated from each other by the epitaxial layer 200 along the direction 300. Moreover, the region of the epitaxial layer 200 between the two separate gate structures 230AG can be regarded as a mesa region 400M of the semiconductor device 500. As shown in FIGS. 1A and 1B , the separate gate structure 230AG extends along the direction 320. In some embodiments, the split gate structure 230AG includes a gate dielectric layer 224AR and gates 230AG1 and 230AG2 separated from each other along the direction 300. In some embodiments, the split gate structure 230AG can further reduce the overall gate-to-drain capacitance ( _Cgd ) and the feedback capacitance ( _Crss = _Cgd ) to improve the overall power conversion efficiency of the semiconductor device 500.

As shown in FIGS. 1A and 1B , the gate dielectric layer 224AR is disposed in the epitaxial layer 200 in the first region 400. The gate dielectric layer 224AR extends from a position close to the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along a direction 320. The top of the electrode 220F1 is exposed from the gate dielectric layer 224AR of the separation gate structure 230AG.

In some embodiments, the gate dielectric layer 224AR may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), low-k dielectric materials, and/or other suitable dielectric materials, or combinations thereof. In this embodiment, the gate dielectric layer 224AR may include silicon oxide. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR and the gate dielectric layer 224AR may be made of the same or different materials according to actual needs. In some embodiments, the gate dielectric layer 224AR may be formed by an oxidation process and a deposition process. In some embodiments, the oxidation process may include thermal oxidation or other suitable processes. In some embodiments, the deposition process may include spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), other suitable processes, or a combination thereof.

The gates 230AG1 and 230AG2 are located on opposite sidewalls 220F1S of the electrode 220F1 and extend along the direction 320. The top surfaces 230AG1T and 230AG2T of the gates 230AG1 and 230AG2 can be aligned with the top surface 200T of the epitaxial layer 200 (the top surfaces 230AG1T, 230AG2T, 200T are coplanar). In addition, the gate dielectric layer 224AR surrounds the gates 230AG1 and 230AG2. In addition, the electrode 220F1 may extend from below the gates 230AG1 and 230AG2 to the top surfaces 230AG1T and 230AG2T of the gates 230AG1 and 230AG2 along the direction 320. Furthermore, the electrode 220F1 may be inserted between the gates 230AG1 and 230AG2 along the direction 300. The opposite sidewalls 220F1S of the electrode 220F1 close to the gates 230AG1 and 230AG2 are separated from the gates 230AG1 and 230AG2 by the gate dielectric layer 224AR.

In some embodiments, the gates 230AG1 and 230AG2 may be a single-layer or multi-layer structure formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or a combination thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), and platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide ( _WSix ). In some embodiments, the gates 230AG1 and 230AG2 may selectively include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the gates 230AG1 and 230AG2 are P-type gates 230AG1 and 230AG2. In addition, the dopant having the second conductivity type may include aluminum (Al), boron (B), boron difluoride ( _BF2 ) or other suitable dopant. In some embodiments, the electrodes 220F1, 220F2, 220F3, and 220F4 may include the same or different materials as the gates 230AG1 and 230AG2.

As shown in FIGS. 1A and 1B , the separated conductive structure 230BG is disposed in the epitaxial layer 200 of the second region 410. In some embodiments, the separated gate structure 230AG and the separated conductive structure 230BG may have similar structures. However, at least one difference between the separated conductive structure 230BG and the gates 230AG1 and 230AG2 is that the separated conductive structure 230BG is not surrounded by the well region 234. For example, the well region 234 may only be adjacent to one of the two opposite sides of the separated conductive structure 230BG along the direction 300, or may not be adjacent to the two opposite sides of the separated conductive structure 230BG along the direction 300. In some embodiments, the separated conductive structure 230BG includes conductive components 230BG1 , 230BG2 separated from each other along the direction 300 .

As shown in FIGS. 1A and 1B , the semiconductor device 500 further includes a dielectric layer 224BR. The dielectric layer 224BR is disposed in the epitaxial layer 200 of the second region 410. The dielectric layer 224BR extends from a location close to the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along a direction 320. The top surface 220F2T of the electrode 220F2 is exposed from the top surface 224BRT of the dielectric layer 224BR. In detail, the top surface 220F2T of the electrode 220F2 can be aligned with the top surface 200T of the epitaxial layer 200 (the top surfaces 220F2T and 200T are coplanar).

In some embodiments, the dielectric layer 224BR and the gate dielectric layer 224AR may include the same or similar materials and processes. In this embodiment, the dielectric layer 224BR may include silicon oxide. In some embodiments, the shielding dielectric layers 216AR, 216BR, 216CR, the gate dielectric layer 224AR and the dielectric layer 224BR may be selected to be the same or different materials according to actual needs. In some embodiments, the dielectric layer 224BR and the gate dielectric layer 224AR may be formed simultaneously.

The conductive components 230BG1 and 230BG2 are located on opposite sidewalls 220F2S of the electrode 220F2 and extend along the direction 320. The top surfaces 230BG1T and 230BG2T of the conductive components 230BG1 and 230BG2 can be aligned with the top surface 200T of the epitaxial layer 200 and the top surface 220F2T of the electrode 220F2 (the top surfaces 230BG1T, 230BG2T, 200T, and 220F2T are coplanar). The dielectric layer 224BR surrounds the conductive components 230BG1 and 230BG2. Furthermore, the top surfaces 230BG1T and 230BG2T of the conductive components 230BG1 and 230BG2 are exposed from the top surface 224BRT of the dielectric layer 224BR. In addition, the electrode 220F2 may extend from below the conductive components 230BG1 and 230BG2 to the top surfaces 230BG1T and 230BG2T of the conductive components 230BG1 and 230BG2 along the direction 320. Furthermore, the electrode 220F2 may be inserted between the conductive components 230BG1 and 230BG2 along the direction 300. Opposite side walls 220F2S of the electrode 220F2 close to the conductive components 230BG1 and 230BG2 are separated from the conductive components 230BG1 and 230BG2 by the dielectric layer 224BR.

In some embodiments, the conductive components 230BG1 and 230BG2 may be a single layer or multi-layer structure, which is formed by amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide ( _WSix ). In some embodiments, the conductive components 230BG1 and 230BG2 may selectively include a dopant of the second conductivity type. For example, when the silicon carbide substrate 100 is an N-type silicon carbide substrate 100, the conductive components 230BG1 and 230BG2 are P-type conductive components 230BG1 and 230BG2. In addition, the above-mentioned dopant with the second conductivity type may include aluminum (Al), boron (B), boron difluoride ( _BF2 ) or other suitable dopant. In some embodiments, the electrodes 220F1, 220F2, 220F4 may include the same or different materials as the conductive components 230BG1 and 230BG2.

The semiconductor device 500 further includes a gate dielectric layer 224C and a gate 230G disposed in the epitaxial layer 200 in the third region 420. The gate dielectric layer 224C extends from a position close to the top surface 200T of the epitaxial layer 200 into the epitaxial layer 200 along the direction 320. Moreover, the gate dielectric layer 224C covers the top of the electrode 220F3. The gate 230G is located on the gate dielectric layer 224C and is connected to the separated gate structure 230AG. In some embodiments, the gate 230G extends from the opposite sidewalls 220F3S of the electrode 220F3 to cover the top surface 220F3T of the electrode 220F3 and the top surface 200T of the epitaxial layer 200. The portion of the gate 230G located on the opposite sidewalls 220F3S of the electrode 220F3 may extend along the direction 320. Also, the portion of the gate 230G located above the top surface 220F3T of the electrode 220F3 and the top surface 200T of the epitaxial layer 200 may extend along the direction 300.

The semiconductor device 500 further includes interlayer dielectric layers 240AR, 240CR, and 240DR. The interlayer dielectric layers 240AR, 240CR, and 240DR are disposed on the epitaxial layer 200 in the first region 400, the third region 420, and the fourth region 430. The interlayer dielectric layer 240AR covers the gate 230AG1, the gate 230AG2, the gate dielectric layer 224AR, the wiring doped region 238, and the gate 230G. The interlayer dielectric layer 240CR covers the gate dielectric layer 224C and the gate 230G. The interlayer dielectric layer 240CR covers the electrode 220F4. Furthermore, the conductive component 230BG1 and/or the conductive component 230BG2 and the electrode 220F2 may be exposed from the interlayer dielectric layer 240AR, 240CR, 240DR. As shown in FIGS. 1A and 1B, the top surface 200T of the epitaxial layer 200 in the second region 410 may not be completely covered by the interlayer dielectric layer. For example, the interlayer dielectric layer 240AR may extend from the top surface 200T of the epitaxial layer 200 in the first region 400 to cover the conductive component 230BG1 of the separated conductive structure 230BG close to the first region 400, and expose the electrode 220F2 and the conductive component 230BG2. As shown in FIG. 1B , the sidewall 240AS of the interlayer dielectric layer 240AR is located on the dielectric layer 224BR close to the electrode 220F2, for example, on the dielectric layer 224BR between the conductive component 230BG1 and the electrode 220F2. In addition, the interlayer dielectric layers 240AR, 240CR, and 240DR do not cover other separated conductive structures 230BG. In some embodiments, the interlayer dielectric layers 240AR, 240CR, and 240DR may include silicon oxide, silicon nitride, silicon oxynitride, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), or a combination thereof. In some embodiments, the interlayer dielectric layers 240AR, 240CR, and 240DR may be formed using a conformable deposition process, an oxidation process, other suitable formation processes, and a subsequent patterning process. In some embodiments, the oxidation process may be a thermal oxidation process, or other suitable processes. In some embodiments, the deposition process may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma assisted chemical vapor deposition (PECVD), other suitable processes, or a combination thereof.

The source contacts 250S1 and 250S2 are disposed on the epitaxial layer 200 of the first region 400. The source contacts 250S1 and 250S2 penetrate the interlayer dielectric layer 240AR of the first region 400. In addition, the source contact 250S1 extends into a portion of the electrode 220F1 along the direction 320, and the source contact 250S2 penetrates the source region 236 (and the wiring doping region 238) and extends into a portion of the well region 234 along the direction 320. The source contact 250S1 is electrically connected to the electrode 220F1, and the source contact 250S2 is electrically connected to the source region 236 and the wiring doping region 238. As shown in FIGS. 1A and 1B , a source contact 250S2 may be disposed in each of the source regions 236 (and the wiring doping region 238 ) on both sides of the separation gate structure 230AG and in the wiring doping region 238 (e.g., in the mesa region 400M), and a source contact 250S1 may be disposed in the upper portion of the electrode 220F1 used to separate the gates 230AG1 and 230AG2, so that the source contact 250S1 is sandwiched between the two source contacts 250S2. The source contacts 250S1 and 250S2 may be electrically connected to the conductive components 230BG1 and 230BG2 and the electrodes 220F2, 220F3, and 220F4 via other interconnects (not shown). In addition, the gates 230AG1 and 230AG2 may be separated from the source contacts 250S1 and 250S2 by a gate dielectric layer 224AR.

In some embodiments, the source contact 250S1 may include a contact barrier layer 246S and a contact conductive layer 248S1. The source contact 250S2 may include a contact barrier layer 246S and a contact conductive layer 248S2. In some embodiments, the source contacts 250S1 and 250S2 are formed simultaneously. As shown in FIG. 1B , the contact barrier layer 246S may continuously cover the top surface 200T of the epitaxial layer 200 of the first region 400 and the second region 410, and extend into a portion of the epitaxial layer 200 of the first region 400. The contact barrier layer 246S may cover and physically contact the top surface 220F2T of the electrode 220F2. Furthermore, the contact barrier layer 246S may cover and physically contact at least one of the top surface 230BG1T of the conductive component 230BG1 and the top surface 230BG2T of the conductive component 230BG2. The contact barrier layer 246S may be used to prevent the subsequently formed contact conductive layers 248S1 and 248S2 from diffusing into the gates 230AG1 and 230AG2. The material of the contact barrier layer 246S may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer 246S may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or combinations thereof.

In some embodiments, the contact conductive layers 248S1 and 248S2 of the source contacts 250S1 and 250S2 may be single-layer or multi-layer structures. The materials of the contact conductive layers 248S1 and 248S2 may include tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), other suitable metals, or combinations thereof. In some embodiments, the contact conductive layers 248S1 and 248S2 may be formed by chemical vapor deposition processes, atomic layer deposition processes, physical vapor deposition processes, other suitable processes, or combinations thereof.

The semiconductor device 500 further includes a gate contact 250G. The gate contact 250G is disposed on the epitaxial layer 200 in the third region 420. The gate contact 250G extends from above the interlayer dielectric layer 240CR, through the interlayer dielectric layer 240CR along the direction 320, and into a portion of the gate 230G to electrically connect the gate 230G. Similar to the source contacts 250S1 and 250S2, the gate contact 250G may include a contact barrier layer 246G and a contact conductive layer 248G. In some embodiments, the contact barrier layers 246S and 246G include the same or similar materials and processes and can be formed at the same time. In addition, the contact barrier layer 246S and the contact barrier layer 246G are separated from each other. The contact conductive layers 248S1, 248S2, and 248G can include the same or similar materials and processes and can be formed at the same time.

As shown in FIGS. 1A and 1B , the semiconductor device 500 further includes a source metal layer 254S and a gate metal layer 254G separated from each other. The source metal layer 254S extends from the epitaxial layer 200 of the first region 400 to cover the epitaxial layer 200 of the second region 410, and is electrically connected to the electrode 220F2, the source region 236 (and the wiring doped region 238), and the well region 234 through the source contacts 250S1 and 250S2. In addition, the source metal layer 254S is electrically connected to the conductive components 230BG1 and 230BG2 through the contact barrier layer 246S. The gate metal layer 254G covers the epitaxial layer 200 of the third region 420 and is electrically connected to the gate 230G via the gate contact 250G. The source metal layer 254S and the gate metal layer 254G can serve as the top metal layer of the final semiconductor device 500. The source metal layer 254S can electrically connect the conductive components 230BG1 and 230BG2 to the electrodes 220F1 and 220F2, the source region 236, and the well region 234. As shown in FIG. 1B , the source metal layer 254S and the contact barrier layer 246S thereunder located in the second region 410 can form a Schottky junction with the epitaxial layer 200 between two adjacent pairs of separated conductive structures 230BG. In addition, the source metal layer 254S can also be electrically connected to the electrodes 220F3 and 220F4 through other internal connections (not shown). The gate metal layer 254G can be electrically connected to the gate 230G through the gate contact 250G.

As shown in FIG. 1B , the source metal layer 254S and the contact barrier layer 246S thereunder located in the second region 410 can form a Schottky diode together with the epitaxial layer (drift region) 200 between the two adjacent pairs of separated conductive structures 230BG. The intrinsic diode at the interface between the well region 234 of different conductive types and the epitaxial layer (drift region) 200 is called a body diode, and the Schottky diode of the embodiment is connected in parallel with the body diode. Since the energy barrier of the Schottky diode is lower than that of the base diode, that is, the on-resistance (Von) is lower, when the semiconductor device is operated, carriers flow through the Schottky diode instead of the base diode. Therefore, the Schottky diode of the disclosed embodiment can disable the base diode, thereby enabling the semiconductor device to achieve the benefits of reducing the on-resistance and power loss.

In some embodiments, the source metal layer 254S and the gate metal layer 254G may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations thereof. In some embodiments, the source metal layer 254S, the gate metal layer 254G and the source contacts 250S1, 250S2 and the gate contact 250G may include the same material or different materials. In some embodiments, the source metal layer 254S and the gate metal layer 254G may be formed by a deposition process and a subsequent patterning process. In some embodiments, the deposition process may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination thereof.

Next, the method of forming the semiconductor device 500 of some embodiments of the present invention is described with reference to FIGS. 2 to 22. FIGS. 2 to 22 are cross-sectional schematic diagrams of intermediate stages of forming the semiconductor device 500 of some embodiments of the present invention shown in FIGS. 1A and 1B. The same or similar element symbols as those in FIGS. 1A and 1B represent the same or similar elements.

As shown in FIG. 2 , a silicon carbide substrate 100 having a first conductivity type is provided, for example, an N-type heavily doped (N+) silicon carbide substrate 100 .

Next, an epitaxial growth process is performed to grow an epitaxial layer 200 having a first conductivity type, such as an N-type lightly doped (N-) silicon carbide epitaxial layer 200, on the top surface 100T of the silicon carbide substrate 100. In some embodiments, the epitaxial process includes metal organic chemical vapor deposition (MOCVD), plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable epitaxial growth processes, or a combination thereof.

Next, as shown in FIG. 3 , a lithography process and a subsequent ion implantation process may be performed to form a well region 234 having a second conductivity type, such as a P-type well region 234, in the epitaxial layer 200 of the first region 400, the third region 420, and the fourth region 430. The well region 234 extends from the top surface 200T of the epitaxial layer 200 of the first region 400, the third region 420, and the fourth region 430 to a portion of the epitaxial layer 200. The epitaxial layer 200 of the second region 410 does not have a well region 234.

Next, as shown in FIG. 4 , a deposition process may be performed to form a mask layer 210 on the epitaxial layer 200. In some embodiments, the mask layer 210 may be a single layer or a multi-layer structure. In some embodiments, the mask layer 210 may include an insulating material such as silicon oxide.

Next, as shown in FIG. 5 , a lithography process and a subsequent patterning process are performed. Part of the mask layer 210 is removed to form mask patterns 210P on the top surface 200T of the epitaxial layer 200 to define the formation position of the trench. Afterwards, the mask pattern 210P is used as an etching mask to perform an etching process on the epitaxial layer 200. The above etching process removes the epitaxial layer 200 not covered by the mask pattern 210P to form trenches 212A, 212B, 212C, and 212D in the epitaxial layer 200 in the first area 400, the second area 410, the third area 420, and the fourth area 430 along the direction 320. In the embodiment shown in FIG. 5 , the etching process forms two trenches 212A in the epitaxial layer 200 in the first region 400, one trench 212B in the epitaxial layer 200 in the second region 410, one trench 212C in the epitaxial layer 200 in the third region 420, and one trench 212D in the epitaxial layer 200 in the fourth region 430. Two adjacent trenches 212A are separated from each other along the direction 300 and define a mesa region 400M of the epitaxial layer 200. In some embodiments, the etching process includes dry etching. Dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), inductive coupled plasma etching or other suitable processes.

Next, as shown in FIG. 6 , a selective etching process may be performed to remove the mask pattern 210P. Thereafter, an oxidation process and a subsequent etching process may be performed to form a sacrificial oxide layer (SAC oxide layer) (not shown) on the sidewalls 212A-S, 212B-S, 212C-S, 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, 212D-B of the trenches 212A, 212B, 212C, 212D. Then, an etching process is performed to remove the sacrificial oxide layer, so that the sidewalls 212A-S, 212B-S, 212C-S, 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, 212D-B of the trenches 212A, 212B, 212C, 212D are exposed again. The oxidation process and etching process shown in FIG. 6 can remove the surface damage caused by the etching process (FIG. 5) for forming the trenches 212A, 212B, 212C, 212D.

Next, as shown in FIG. 7 , an oxidation process and a subsequent deposition process may be performed to fully form a shielding dielectric layer 216. The shielding dielectric layer 216 covers the top surface 200T of the epitaxial layer 200 and extends into the trenches 212A, 212B, 212C, and 212D, conformingly covering the sidewalls 212A-S, 212B-S, 212C-S, 212D-S and bottom surfaces 212A-B, 212B-B, 212C-B, and 212D-B of the trenches 212A, 212B, 212C, and 212D ( FIG. 6 ).

In some embodiments, a thermal process may be selectively performed on the shielding dielectric layer 216 to increase the density of the shielding dielectric layer 216 and improve the interface property between the shielding dielectric layer 216 and the epitaxial layer 200. In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

Next, as shown in FIG. 8 , a deposition process and a subsequent planarization process may be performed to form conductive materials 220A, 220B, 220C, and 220D in the trenches 212A, 212B, 212C, and 212D ( FIG. 7 ), respectively. In some embodiments, the conductive materials 220A, 220B, 220C, and 220D are formed simultaneously. The top surface 220AT of the conductive material 220A, the top surface 220BT of the conductive material 220B, the top surface 220CT of the conductive material 220C, and the top surface 220DT of the conductive material 220D are all higher than the top surface 200T of the epitaxial layer 200 and are aligned with each other. For example, the top surface 220AT of the conductive material 220A, the top surface 220BT of the conductive material 220B, the top surface 220CT of the conductive material 220C, and the top surface 220DT of the conductive material 220D are aligned with the top surface 216T of the shielding dielectric layer 216. In addition, the conductive materials 220A, 220B, 220C, and 220D include the same material. In some embodiments, the conductive materials 220A, 220B, 220C, and 220D may be formed of amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. In some embodiments, the metal may include but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, the metal nitride may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include but is not limited to tungsten silicide ( _WSix ). In some embodiments, the above-mentioned deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistive thermal evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the above-mentioned planarization process includes a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 9 , an etch-back process may be performed to remove portions of the conductive materials 220A, 220B, 220C, 220D from the top surfaces 220AT, 220BT, 220CT, 220DT of the conductive materials 220A, 220B, 220C, 220D. After the etch-back process, the remaining conductive materials 220A, 220B, 220C, 220D are labeled as conductive materials 220AR, 220BR, 220CR, 220DR. The top surfaces 220ART, 220BRT, 220CRT, 220DRT of the conductive materials 220AR, 220BR, 220CR, 220DR may be located above the top surface 200T of the epitaxial layer 200. For example, the top surfaces 220ART, 220BRT, 220CRT, 220DRT of the conductive materials 220AR, 220BR, 220CR, 220DR may be higher than the top surface 200T of the epitaxial layer 200 and lower than the top surface 216T of the shielding dielectric layer 216. In some embodiments, the etching back process may be a selective etching process, such as dry etching.

Next, as shown in FIG. 10 , a deposition process may be performed to fully form an oxide layer 222. The oxide layer 222 covers the shielding dielectric layer 216 and the conductive materials 220AR, 220BR, 220CR, and 220DR. When both the oxide layer 222 and the shielding dielectric layer 216 include silicon oxide, the interface between the oxide layer 222 and the shielding dielectric layer 216 is not obvious. In some embodiments, the oxide layer 222 includes tetraethyl orthosilicate (TEOS) oxide formed using low pressure chemical vapor deposition (LPCVD). Since the top surfaces 220ART, 220BRT, 220CRT, 220DRT of the conductive materials 220AR, 220BR, 220CR, 220DR are lower than the top surface 216T of the shielding dielectric layer 216, the upper surface 222T1 of the portion of the oxide layer 222 directly above the conductive materials 220AR, 220BR, 220CR, 220DR is lower than the upper surface 222T2 of the portion of the oxide layer 222 directly above the shielding dielectric layer 216.

Next, as shown in FIG. 11 , a lithography process may be performed to form a mask pattern PR1 such as a photoresist pattern on the epitaxial layer 200 of the fourth region 430. The mask pattern PR1 covers the conductive material 220DR and a portion of the shielding dielectric layer 216 and the oxide layer 222 of the fourth region 430, and exposes a portion of the oxide layer 222 ( FIG. 10 ) of the first region 400, the second region 410, and the third region 420 from the mask pattern PR1. Thereafter, a selective etching process may be performed to remove the oxide layer 222 and a portion of the shielding dielectric layer 216 ( FIG. 10 ) from the top surface 200T of the epitaxial layer 200 and the upper portion of the trenches 212A, 212B, 212C close to the top surface 200T of the epitaxial layer 200, thereby exposing the upper portions 220AR-1, 220BR-1, 220CR-1 of the conductive materials 220AR, 220BR, 220CR. After the selective etching process, the shielding dielectric layer 216 remaining in the trenches 212A, 212B, 212C in the first region 400, the second region 410, and the third region 420 is labeled as shielding dielectric layer 216AR, 216BR, 216CR, and the shielding dielectric layer 216 and the oxide layer 222 remaining in the fourth region 430 are labeled as shielding dielectric layer 216DR and oxide layer 222DR. The shielding dielectric layers 216AR, 216BR, 216CR surround the lower portion of the conductive materials 220AR, 220BR, 220CR and expose the sidewalls 212A-S, 212B-S, 212C-S at the upper portion of the trenches 212A, 212B, 212C. The top surfaces 216ART, 216BRT, 216CRT of the shielding dielectric layers 216AR, 216BR, 216CR may be below the bottom surface 234B of the well region 234. The shielding dielectric layer 216DR and the oxide layer 222DR surround the conductive material 220DR. In some embodiments, the selective etching process includes wet etching. After forming the shielding dielectric layers 216AR, 216BR, 216CR, 216DR, the mask pattern PR1 is removed.

Next, as shown in FIG. 12 , an oxidation process may be performed to form gate dielectric layers 224A and 224C in the trenches 212A and 212C, and simultaneously form a dielectric layer 224B in the trench 212B. The oxidation process includes oxidizing the sidewalls 212A-S of the upper portion of the trench 212A and the surface portion of the upper portion 220AR-1 ( FIG. 11 ) of the conductive material 220AR to form the gate dielectric layer 224A and the electrode 220F1 in the trench 212A. The top surface 220F1T of the electrode 220F1 may be aligned with the top surface 200T of the epitaxial layer 200 (the top surfaces 220F1T and 200T are coplanar).

The oxidation process further includes oxidizing the sidewall 212B-S at the upper portion of the trench 212B and the surface portion in the upper portion 220BR-1 (FIG. 11) of the conductive material 220BR to form a dielectric layer 224B and an electrode 220F2 in the trench 212B. The oxidation process further includes oxidizing the sidewall 212C-S at the upper portion of the trench 212C and the surface portion in the upper portion 220CR-1 (FIG. 11) of the conductive material 220CR to form a gate dielectric layer 224C and an electrode 220F3 in the trench 212C. The shielding dielectric layers 216AR, 216BR, 216CR surround the lower portion of the conductive materials 220AR, 220BR, 220CR, so the lower portion of the conductive materials 220AR, 220BR, 220CR will not be oxidized. When the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, and the shielding dielectric layers 216AR, 216BR, 216CR all include silicon oxide, the interface between the gate dielectric layers 224A, 224C and the shielding dielectric layers 216AR, 216CR (or the dielectric layer 224B and the shielding dielectric layer 216BR) is not obvious. Furthermore, the gate dielectric layer 224A, the dielectric layer 224B and the gate dielectric layer 224C extend to cover the top surface 200T of the epitaxial layer 200 in the first region 400, the second region 410 and the third region 420. The oxidation process further includes forming an oxide layer on the oxide layer 222DR in the fourth region 430 (not shown).

In some embodiments of the present invention, the gate dielectric layer 224A does not completely fill the trench 212A. Moreover, the gate dielectric layer 224A includes a gate dielectric layer 224A-1 conformally formed on the sidewall 212A-S ( FIG. 11 ) at the upper portion of the trench 212A, and a gate dielectric layer 224A-2 surrounding the upper portion of the electrode 220F1. Similarly, the dielectric layer 224B does not completely fill the trench 212B. Furthermore, the dielectric layer 224B includes a dielectric layer 224B-1 conformably formed on the sidewall 212B-S (FIG. 11) of the upper portion of the trench 212B, and a dielectric layer 224B-2 surrounding the upper portion of the electrode 220F2. Similarly, the gate dielectric layer 224C does not fill the trench 212C. Furthermore, the gate dielectric layer 224C includes a gate dielectric layer 224C-1 conformably formed on the sidewall 212C-S (FIG. 11) of the upper portion of the trench 212C, and a gate dielectric layer 224C-2 surrounding the upper portion of the electrode 220F3. In some embodiments, the thickness of the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1 is smaller than the thickness of the shielding dielectric layer 216AR, 216BR, and 216CR. Compared with the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1 formed by oxidation of the epitaxial layer 200 of silicon carbide, the gate dielectric layer 224A-2, the dielectric layer 224B-2, and the gate dielectric layer 224C-2 are formed by oxidation of the conductive material 220AR, 220BR, and 220CR ( FIG. 11 ) such as polysilicon, and therefore have a thicker thickness.

After the oxidation process, the unoxidized conductive material 220AR, conductive material 220BR, and conductive material 220CR in the trench 212A, trench 212B, and trench 212C respectively form electrodes 220F1, electrode 220F2, and electrode 220F3, while the unoxidized conductive material 220DR in the trench 212D forms an electrode 220F4. In some embodiments of the present invention, the electrodes 220F1, 220F2, 220F3, and 220F4 extend along the direction 320. In direction 300, since the gate dielectric layer 224A-2, the dielectric layer 224B-2, and the gate dielectric layer 224C-2 are thicker than the gate dielectric layer 224A-1, the dielectric layer 224B-1, and the gate dielectric layer 224C-1, the width W1 of the upper portion of the electrode 220F1 (the upper portion 220AR-1 of the unoxidized conductive material 220A) may be smaller than the width W2 of the lower portion of the electrode 220F1 (the portion surrounded by the shielding dielectric layer 216AR). Similarly, in direction 300, the width W3 of the upper portion of electrode 220F2 (upper portion 220BR-1 of unoxidized conductive material 220B) may be smaller than the width W4 of the lower portion of electrode 220F2 (the portion surrounded by shielding dielectric layer 216BR), and the width W5 of the upper portion of electrode 220F3 (upper portion 220CR-1 of unoxidized conductive material 220C) may be smaller than the width W6 of the lower portion of electrode 220F3 (the portion surrounded by shielding dielectric layer 216CR). In some embodiments, widths W1, W3, and W5 may be equal to each other, and widths W2, W4, and W6 may be equal to each other. In addition, in direction 300, electrode 220F4 has a uniform width W7. In some embodiments, width W7 may be equal to widths W1, W3, and W5.

In some embodiments, the oxidation process may be thermal oxidation or other suitable processes. In some embodiments, the oxidation process and subsequent deposition process may be used to form the gate dielectric layer 224A, the dielectric layer 224B, and the gate dielectric layer 224C. In some embodiments, the deposition process may be low pressure chemical vapor deposition (LPCVD) or other suitable processes.

Next, as shown in FIG. 13 , a deposition process and a subsequent planarization process may be performed to form an electrode material 230 on the epitaxial layer 200. The electrode material 230 covers the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C of the first region 400, the second region 410, and the third region 420, and the oxide layer 222DR of the fourth region 430. In addition, the electrode material 230 fills the trenches 212A, 212B, and 212C ( FIG. 12 ). In some embodiments, the electrode material 230 and the electrodes 220F1, 220F2, 220F3, and 220F4 may include the same material, such as polysilicon. In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistive thermal evaporation, electron beam evaporation, or other suitable deposition processes. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 14 , a patterning process may be performed to remove a portion of the electrode material 230 ( FIG. 13 ) above the epitaxial layer 200 in the first region 400 , the second region 410 , and the fourth region 430 . The patterning process includes a lithography process and a subsequent selective etching process. The lithography process may form a mask pattern PR2 , such as a photoresist pattern, above the epitaxial layer 200 in the third region 420 . The mask pattern PR2 covers the electrode material 230 in the third region 420 , and exposes the electrode material 230 in the first region 400 , the second region 410 , and the fourth region 430 . Thereafter, a selective etching process may be performed to remove the electrode material 230 on the top surface 200T of the epitaxial layer 200 in the first region 400 and the upper portion of the trench 212A close to the top surface 200T of the epitaxial layer 200, so as to form gates 230AG1 and 230AG2 separated from each other along the direction 300 and extending along the direction 320 on the opposite side walls 220F1S of the electrode 220F1 in the trench 212A. Furthermore, the selective etching process simultaneously removes the electrode material 230 on the top surface 200T of the epitaxial layer 200 in the second region 410 and the upper portion of the trench 212B close to the top surface 200T of the epitaxial layer 200, so as to form conductive components 230BG1 and 230BG2 separated from each other along the direction 300 and extending along the direction 320 on the opposite sidewalls 220F2S of the electrode 220F2 in the trench 212B. The conductive components 230BG1 and 230BG2 can constitute a separate conductive structure 230BG. As shown in FIG. 14 , gates 230AG1, 230AG2, conductive components 230BG1, 230BG2 may extend along direction 320 to below the bottom surface 234B of the well 234. In some embodiments, gates 230AG1, 230AG2 may fill up the trench 212A, and conductive components 230BG1, 230BG2 may fill up the trench 212B. In some embodiments, a top surface 230AG1T of the gate 230AG1, a top surface 230AG2T of the gate 230AG2, a top surface 230BG1T of the conductive component 230BG1, a top surface 230BG2T of the conductive component 230BG2, and a top surface 220F1T of the electrode 220F1 may be aligned with a top surface 200T of the epitaxial layer 200 .

As shown in FIG. 14 , the selective etching process may also remove the electrode material 230 on the oxide layer 222DR of the fourth region 430. After the selective etching process, a gate 230G may be formed above the epitaxial layer 200 and in the trench 212C ( FIG. 12 ) in the third region 420. In some embodiments, the gate 230G fills the remaining space of the trench 212B and extends to cover the electrode 220F3 and the epitaxial layer 200 outside the trench 212C. Since the electrode material 230 and the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C and the oxide layer 222DR may be made of different materials, the selective etching process will not remove the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C and the oxide layer 222DR. In some embodiments, the selective etching process includes dry etching. After forming the gate 230AG1, the gate 230AG2, the conductive component 230BG1, the conductive component 230BG2, and the gate 230G, the mask pattern PR2 is removed.

Next, the formation methods of the source region 236 and the wiring doping region 238 are respectively described with reference to FIGS. 15 and 16. Furthermore, the formation positions of the source region 236 and the wiring doping region 238 located in the first region 400 are described with reference to FIG. 23. In order to illustrate the configuration of the source region 236 and the wiring doping region 238, the gate dielectric layer 224A-1 covering the top surface 200T of the epitaxial layer 200 is not shown in FIG. 15 and 16 show cross-sectional views of the intermediate structure of the semiconductor device 500 of some embodiments of the present invention at different positions in the direction 310. FIG. 20 is a top view schematically showing an intermediate stage of forming the semiconductor device 500 of some embodiments of the present invention shown in FIG. 1, which shows the configuration of the source region 236 and the wiring doping region 238 above the well region 234. The first region 400 shown in FIGS. 15 and 16 may correspond to the cross-sectional positions of the A-A' cut line and the B-B' cut line of FIG. 20, respectively, to illustrate the formation method of the source region 236 and the wiring doping region 238 arranged alternately along the direction 310 in the epitaxial layer 200 of the first region 400.

As shown in FIG. 15 , a lithography process may be performed to form a mask pattern PR3, such as a photoresist pattern, on the epitaxial layer 200 in the second region 410, the third region 420, and the fourth region 430 to expose a predetermined formation region of the source region 236 in the first region 400 (corresponding to the formation region of the source region 236 in FIG. 23 ). Thereafter, an ion implantation process is performed to form a source region 236 of a first conductivity type (e.g., an N-type source region 236) on the well region 234 of the first region 400. After the source region 236 is formed, the mask pattern PR3 is removed.

As shown in FIG. 16 , a lithography process may be performed to form a mask pattern PR4, such as a photoresist pattern, on the epitaxial layer 200 in the second region 410, the third region 420, and the fourth region 430 to expose the predetermined formation region of the wiring doping region 238 in the first region 400 (corresponding to the formation region of the wiring doping region 238 in FIG. 23 ). It is worth noting that the source region 236 and the predetermined formation region of the wiring doping region 238 are respectively located in different regions of the epitaxial layer 200 that intersect along the direction 310 (FIG. 20 ). Thereafter, an ion implantation process is performed to form a wiring doping region 238 of a second conductivity type (e.g., a P-type wiring doping region 238) on the well region 234 of the first region 400. After forming the wiring doped region 238, the mask pattern PR4 is removed.

In some embodiments, the source region 236 and the wiring doping region 238 are disposed in the epitaxial layer 200 adjacent to the trench 212A. Furthermore, the source region 236 and the wiring doping region 238 are disposed in the epitaxial layer 200 between two adjacent pairs of gates 230AG1 and 230AG2 along the direction 300. In other words, the source region 236 and the wiring doping region 238 are disposed in the mesa region 400M. In the direction 300 , there is no other doping region between the opposite sidewalls of each source region 236 and the wiring doping region 238 and the two gates 230AG1 and 230AG2 that are close to each other in the two pairs of adjacent gates 230AG1 and 230AG2 .

In some embodiments, the process sequences shown in FIGS. 15 and 16 may be interchanged, that is, the wiring doping region 238 may be formed first, and then the source region 236 may be formed.

Next, as shown in FIG. 17 , a deposition process and a subsequent planarization process may be performed to form an interlayer dielectric layer 240 on the epitaxial layer 200. The interlayer dielectric layer 240 covers the gate 230AG1, the gate 230AG2, the conductive component 230BG1, the conductive component 230BG2, the gate 230G, the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C and the oxide layer 222DR. When the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, the oxide layer 222DR, and the interlayer dielectric layer 240 all include silicon oxide, the interface between the gate dielectric layer 224A, the dielectric layer 224B, the gate dielectric layer 224C, the oxide layer 222DR, and the interlayer dielectric layer 240 is not obvious. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process.

Next, as shown in FIG. 18 , a lithography process may be performed to form a mask pattern PR5, such as a photoresist pattern, on the epitaxial layer 200. The mask pattern PR5 has an opening 242A1 located directly above the electrode 220F1, an opening 242A2 located directly above the source region 236 and the wiring doped region 238, and an opening 242C located directly above the gate 230G. Furthermore, the mask pattern PR5 completely covers the epitaxial layer 200 and the interlayer dielectric layer 240 in the second region 410 and the fourth region 430.

Next, as shown in FIG. 19 , an etching process may be performed to remove the interlayer dielectric layer 240 and the gate dielectric layer 224A, the electrode 220F1 and a portion of the epitaxial layer 200 thereunder exposed from the openings 242A1 and 242A2 of the mask pattern PR5 ( FIG. 18 ), so as to form an opening (contact hole) 244A1 exposing the electrode 220F1 in the interlayer dielectric layer 240 of the first region 400, as well as an opening (contact hole) 244A2 exposing the well region 234, the source region 236 and the wiring doping region 238. The above etching process simultaneously removes the interlayer dielectric layer 240 and a portion of the gate 230G thereunder exposed from the opening (contact hole) 242C (FIG. 18) of the mask pattern PR5, so as to form an opening (contact hole) 244C in a portion of the interlayer dielectric layer 240 directly above the gate 230G in the third region 420, exposing the gate 230G. In some embodiments, the above etching process includes dry etching. After the above etching process, the interlayer dielectric layer 240 remaining in the first region 400 is labeled as the interlayer dielectric layer 240AR, and the remaining gate dielectric layer 224A is labeled as the gate dielectric layer 224AR. The gate dielectric layer 224AR forms a separate gate structure 230AG together with the gates 230AG1 and 230AG2. In addition, the interlayer dielectric layer 240 remaining in the second region 410, the third region 420, and the fourth region 430 is respectively labeled as the interlayer dielectric layer 240BR, the interlayer dielectric layer 240CR, and the interlayer dielectric layer 240DR. After forming the interlayer dielectric layer 240AR, the gate dielectric layer 224AR, the interlayer dielectric layer 240BR, the interlayer dielectric layer 240CR, and the interlayer dielectric layer 240DR, the mask pattern PR5 is removed.

Next, as shown in FIG. 20 , an ion implantation process may be performed to form a contact doping region 245 in the epitaxial layer 200 below the opening (contact hole) 244A2. The contact doping region 245 has the same conductivity type as the well region 234, for example, a P-type contact doping region 245. Furthermore, the doping concentration of the contact doping region 245 is greater than the doping concentration of the well region 234. For example, when the well region 234 is a P-type well region 234, the contact doping region 245 is a P-type heavily doped (P+) contact doping region 245 to serve as a wiring doping region of the well region 234. After the aforementioned ion implantation process, an annealing process may be performed to activate dopants in the well region 234, the source region 236, the wiring doped region 238, and the contact doped region 245. In some embodiments, the annealing process includes laser annealing, rapid thermal annealing (RTA), other suitable annealing processes, or a combination thereof.

Next, as shown in FIG. 21 , a lithography process may be performed to form a mask pattern PR6, such as a photoresist pattern, on the epitaxial layer 200 of the first region 400, the third region 420, and the fourth region 430. The mask pattern PR6 fills the openings (contact holes) 244A1, 244A2, 244C, and exposes the interlayer dielectric layer 240BR (FIG. 20) of the second region 410. Thereafter, an etching process is performed to remove the interlayer dielectric layer 240BR and the dielectric layer 224B (FIG. 20) on the top surface 200T of the epitaxial layer 200 of the second region 410. The dielectric layer 224B after the above process is labeled as a dielectric layer 224BR. After the above process, at least one of the conductive component 230BG1 and the conductive component 230BG2 and the electrode 220F2 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, and 240DR. In the embodiment shown in FIG. 21 , the top surface 220F2T of the electrode 220F2, the top surface 230BG1T of the conductive component 230BG1, and the top surface 230BG2T of the conductive component 230BG2 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, and 240DR. In the embodiment shown in FIG. 1B , the top surface 220F2T of the electrode 220F2 closest to the first region 400 and the top surface 230BG2T of the conductive component 230BG2 are exposed from the remaining interlayer dielectric layers 240AR, 240CR, 240DR. After removing the interlayer dielectric layer 240BR ( FIG. 20 ) on the top surface 200T of the epitaxial layer 200 of the second region 410, the mask pattern PR6 is removed.

Next, as shown in FIG. 22 , a deposition process may be performed to form a contact barrier layer 246 on the interlayer dielectric layers 240AR, 240CR, 240DR and the top surface 200T of the epitaxial layer 200 in the second region 410, and the contact barrier layer 246 is conformably deposited in the openings (contact holes) 244A1, 244A2, 244C ( FIG. 20 ). The contact barrier layer 246 in the second region 410 directly contacts the separated conductive structure 230BG and the electrode 220F2 that are not covered by the interlayer dielectric layer 240AR. In the embodiment shown in FIG. 22 , the contact barrier layer 246 of the second region 410 directly contacts the top surface 220F2T of the electrode 220F2, the top surface 230BG1T of the conductive component 230BG1, and the top surface 230BG2T of the conductive component 230BG2. In the embodiment shown in FIG. 1B , the contact barrier layer 246 of the second region 410 directly contacts the top surface 220F2T of the electrode 220F2 closest to the first region 400 and the top surface 230BG2T of the conductive component 230BG2.

Thereafter, as shown in FIG. 22 , a contact conductive layer (not shown) is deposited on the contact barrier layer 246. The contact conductive layer fills the remaining space in the openings (contact holes) 244A1, 244A2, and 244C. Next, a removal process (e.g., an etching process or a planarization process) is performed to remove excess portions of the contact conductive layer on the interlayer dielectric layers 240AR, 240CR, 240DR and on the top surface 200T of the epitaxial layer 200 in the second region 410, so as to form contact conductive layers 248S1, 248S2, and 248G in the openings (contact holes) 244A1, 244A2, and 244C. The contact conductive layers 248S1, 248S2, and 248G fill the remaining spaces of the openings (contact holes) 244A1, 244A2, and 244C. The contact barrier layer 246 in the second region 410 is not covered by the contact conductive layer. Furthermore, the removal process does not remove the contact barrier layer 246.

Next, as shown in FIGS. 1A and 1B, a deposition process and a subsequent patterning process may be performed to form a source metal layer 254S on the epitaxial layer 200 in the first region 400 and the second region 410, and a gate metal layer 254G on the epitaxial layer 200 in the third region 420. The deposition process forms a metal layer (not shown) throughout, and the metal layer covers and physically connects the contact conductive layer 248S1, the contact conductive layer 248S2, and the contact conductive layer 248G. In addition to removing the metal layer in the fourth region 430, the patterning process further includes removing the contact barrier layer 246 in the fourth region 430 to form a contact barrier layer 246S on the epitaxial layer 200 in the first region 400 and the second region 410, and to form a contact barrier layer 246G on the epitaxial layer 200 in the third region 420. The contact barrier layer 246S and the contact barrier layer 246G are separated from each other. The source metal layer 254S directly contacts the contact barrier layer 246S in the first region 400 and the second region 410. The gate metal layer 254G directly contacts the contact barrier layer 246G in the third region 420.

During the formation of the source metal layer 254S, the gate metal layer 254G, the contact barrier layer 246S and the contact barrier layer 246G, a source contact 250S1 (including the contact barrier layer 246S and the contact conductive layer 248S1) is formed on the electrode 220F1 of the first region 400, and a source contact 250S2 (including the contact barrier layer 246S and the contact conductive layer 248S2) is formed on the well region 234, the source region 236, and the wiring doped region 238 of the first region 400. , and at the same time, a gate contact 250G (including a contact barrier layer 246G and a contact conductive layer 248G) is formed on the gate 230G of the third region 420.

As shown in FIGS. 1A and 1B , the source metal layer 254S is continuously distributed on the epitaxial layer 200 in the first region 400 and the second region 410 . The source metal layer 254S covers and is electrically connected to the source contacts 250S1 and 250S2 . Furthermore, the source metal layer 254S covers and is electrically connected to the separated conductive structure 230BG and the electrode 220F2 that are not covered by the interlayer dielectric layer 240AR. In the embodiment shown in FIGS. 1A and 1B , the source metal layer 254S of the second region 410 covers and electrically connects the top surface 220F2T of the electrode 220F2 and the top surface 230BG2T of the conductive component 230BG2 closest to the first region 400, as well as the separated conductive structure 230BG (including the conductive components 230BG1 and 230BG2) and the electrode 220F2 far from the first region 400. Furthermore, the source metal layer 254S directly contacts the contact barrier layer 246S of the first region 400 and the second region 410. As shown in FIG. 1B , the source metal layer 254S in the second region 410 and the contact barrier layer 246S thereunder may form a Schottky diode together with the epitaxial layer (drift region) 200 between two adjacent pairs of separated conductive structures 230BG.

As shown in FIGS. 1A and 1B , the gate metal layer 254G covers and electrically connects the gate contact 250G. Furthermore, the gate metal layer 254G directly contacts the contact barrier layer 246G in the third region.

In some embodiments, the deposition process for forming the source metal layer 254S and the gate metal layer 254G may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination thereof.

A subsequent process may be further performed to form a drain contact (not shown) on the bottom surface 100B of the silicon carbide substrate 100. The drain contact may be electrically connected to the silicon carbide substrate 100. After the above process, a semiconductor device 500 is formed.

Some embodiments of the present disclosure provide semiconductor devices and methods for forming the same. The semiconductor device includes an isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit formed in a cell region (e.g., first region 400) of an epitaxial layer. The isolated gate trench metal oxide semiconductor field effect transistor unit has a separated gate structure. Two gates (e.g., gates 230AG1 and 230AG2) of the separated gate structure are formed on opposite side walls of an electrode having a field plate function (also referred to as a source electrode, such as electrode 220F1). The split gate structure can further reduce the overall gate-to-drain capacitance (C _gd ) and feedback capacitance (C _rss = C _gd ) to improve the overall power conversion efficiency of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit. The above-mentioned source electrode can not only reduce the gate-to-drain capacitance ( _Cgd ) to improve the switching characteristics of the semiconductor device, but also make the electric field distribution of the gate dielectric layer near the bottom of the split gate structure more uniform and increase the breakdown voltage to improve the reliability of the gate dielectric layer. It can also further increase the doping concentration of the epitaxial layer (drift region) to reduce the on-resistance ( _Ronsp ) of the isolated gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) unit.

The semiconductor device of the disclosed embodiment further includes a Schottky diode formed in the trench Schottky diode region (e.g., the second region 410). The Schottky diode is composed of an epitaxial layer (e.g., the epitaxial layer 200), a contact barrier layer (e.g., the contact barrier layer 246S), and a source metal layer (e.g., the source metal layer 254S). The Schottky diode can be connected in parallel with the isolation gate trench MOSFET unit to disable the body diode, thereby reducing the on-resistance and power loss, and improving the switching characteristics of the semiconductor device.

In some embodiments, the Schottky diode is sandwiched between two adjacent pairs of trench-type separated conductive structures (e.g., separated conductive structures 230BG), and thus can be referred to as a trench-type Schottky diode (TMBS). Therefore, the reverse leakage current of the Schottky diode disclosed herein can be stopped by the trench-type separated conductive structures, and can have a lower leakage current. In some embodiments, two conductive components (e.g., conductive components 230BG1, 230BG2) of the trench-type separated conductive structures are formed on opposite side walls of another electrode (also referred to as a source electrode, such as electrode 220F2) having a field plate function. In some embodiments, the other source electrode inserted into the two conductive components also has a field plate function, so that the electric field distribution of the epitaxial layer (drift region) of the Schottky diode is more uniform. Therefore, the doping concentration of the epitaxial layer (drift region) can be further increased to further reduce the forward voltage drop (V _F ) of the trench Schottky diode. Therefore, the Schottky diode disclosed in the present invention can not only improve the switching characteristics of the semiconductor device, but also further reduce the forward voltage drop (V _F ) and reverse leakage current of the Schottky diode itself.

Although the present invention is disclosed as above by the aforementioned embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the attached patent application.

100: Silicon carbide substrate 100T, 200T, 216T, 216ART, 216BRT, 216CRT, 220AT, 220BT, 220CT, 220DT, 220ART, 220BRT, 220CRT, 220DRT, 220F1T, 220F2T, 220F3T, 224BRT, 230AG1T, 230AG2T, 230BG1T, 230BG2T, 220F3T: Top surface 100B, 212A-B, 212B-B, 212C-B, 212D-B, 234B: Bottom surface 200: Epitaxial layer 210: Mask layer 210P: Mask pattern 212A, 212B, 212C, 212D: Grooves 212A-S, 212B-S, 212C-S, 212D-S, 220F1S, 220F2S, 220F3S, 240AS: Sidewalls 216, 216AR, 216BR, 216CR, 216DR: Shielding dielectric layer 220A, 220B, 220C, 220D, 220AR, 220BR, 220CR, 220DR: Conductive material 220AR-1, 220BR-1, 220CR-1: Top 220F1, 220F2, 220F3, 220F4: Electrodes 220F1-1,220AR-1,220BR-1,220CR-1: Top 222,222DR: Oxide layer 222T1,222T2: Top surface 224A,224C,224A-1,224A-2,224C-1,224C-2,224AR,224C: Gate dielectric layer 224B,224B-1,224B-2,224BR: Dielectric layer 230: Electrode material 230AG: Separate gate structure 230BG: Separate conductive structure 230AG1,230AG2,230G: Gate 230BG1, 230BG2: Conductive component 234: Well area 236: Source area 238: Wiring doping area 240, 240AR, 240BR, 240CR, 240DR: Interlayer dielectric layer 242A1, 242A2, 242C, 244A1, 244A2, 244C: Opening 245: Contact doping area 246, 246S, 246G: Contact barrier layer 248S1, 248S2, 248G: Contact conductive layer 250G: Gate contact 250S1, 250S2: Source contact 254S: Source metal layer 254G: Gate metal layer 300,310,320: Direction 400: First area 400M: Mesa area 410: Second area 420: Third area 430: Fourth area 500: Semiconductor device PR1,PR2,PR3,PR4,PR5,PR6: Mask pattern W1,W2,W3,W4,W5,W6,W7: Width

When read in conjunction with the accompanying drawings, the following detailed description will provide a better understanding of the concepts of the embodiments of the present invention. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are provided for illustration purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present invention. Figures 1A and 1B are schematic cross-sectional views of semiconductor devices of some embodiments of the present invention. Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, and 22 are schematic cross-sectional views of intermediate stages of forming semiconductor devices of some embodiments of the present invention shown in Figures 1A and 1B. FIG. 23 is a top view schematic diagram of the intermediate stage of forming the semiconductor device of some embodiments of the present invention shown in FIGS. 1A and 1B, showing the configuration of the source region and the wiring doping region above the well region.

100: Silicon carbide substrate

100T, 200T, 224BRT, 230AG1T, 230AG2T, 230BG1T, 230BG2T: Top

100B: Bottom

200: Epitaxial layer

216AR, 216BR: shielding dielectric layer

220F1,220F2:Electrode

220F1S, 220F2S, 240AS: Side wall

224AR: Gate dielectric layer

224BR: Dielectric layer

230AG: Split gate structure

230BG: Separated conductive structure

230AG1,230AG2: Gate

230BG1,230BG2: Conductive parts

234: Well area

236: Source region

238: Wiring mixed area

240AR: Interlayer dielectric layer

245: Contact doping area

246S: Contact barrier

250S1,250S2: Source contact

254S: Source metal layer

300,310,320: Direction

400: District 1

410: District 2

Claims (20)

A semiconductor device comprises: a silicon carbide substrate having a first region and a first conductivity type; an epitaxial layer disposed on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; a first electrode disposed in the epitaxial layer of the first region and extending along a first direction, wherein the first electrode has a first upper portion and a first lower portion, and a first width of the first upper portion is smaller than a second width of the first lower portion; a separated conductive structure disposed in the epitaxial layer of the first region, wherein the separated conductive structure comprises: a first conductive component and a second conductive component separated from each other, located on opposite side walls of the first electrode; and A source metal layer is disposed on the epitaxial layer of the first region, wherein the source metal layer covers and electrically connects the first conductive component, the second conductive component and the first electrode. The semiconductor device as described in claim 1 further comprises: A contact barrier layer disposed on the epitaxial layer in the first region, wherein the contact barrier layer is in direct contact with at least one of the first electrode, the first conductive component, and the second conductive component and the source metal layer. A semiconductor device as described in claim 1, wherein the silicon carbide substrate has a second region, and the semiconductor device further includes: A well region, located in the epitaxial layer of the second region, and the well region has a second conductivity type; A second electrode, disposed in the epitaxial layer of the second region and extending along the first direction; A separate gate structure, disposed in the epitaxial layer of the second region, wherein the separate gate structure includes: A first gate and a second gate separated from each other, disposed on opposite side walls of the second electrode; An interlayer dielectric layer, disposed on the epitaxial layer of the second region; and A plurality of source contacts penetrate the inter-dielectric layer of the second region and extend into the second electrode and the well region, wherein the source metal layer covers and electrically connects the source contacts. A semiconductor device as described in claim 3, wherein the first electrode is exposed from the interlayer dielectric layer. A semiconductor device as described in claim 3, wherein at least one of the first conductive component and the second conductive component is exposed from the interlayer dielectric layer. The semiconductor device as described in claim 3 further includes: A first dielectric layer disposed in the epitaxial layer of the first region and surrounding the first conductive component and the second conductive component, wherein the first electrode, the first conductive component and the second conductive component are exposed from a top surface of the first dielectric layer, wherein the separated gate structure further includes: A first gate dielectric layer disposed in the epitaxial layer of the second region and surrounding the first gate and the second gate, wherein the interlayer dielectric layer covers the first gate dielectric layer. A semiconductor device as described in claim 6, wherein a side wall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode. The semiconductor device as described in claim 3 further includes: A plurality of source regions and a plurality of wiring doping regions, located on the well region in the second region and close to a top surface of the epitaxial layer, wherein the source regions and the wiring doping regions are arranged alternately along a third direction and have opposite conductivity types, wherein the source contacts connect the source regions and the wiring doping regions. A semiconductor device as described in claim 8, wherein the interlayer dielectric layer covers the source regions and the wiring doping regions. A semiconductor device as described in claim 3, wherein the silicon carbide substrate has a third region and a fourth region, and the semiconductor device further comprises: a third electrode disposed in the epitaxial layer of the third region and extending along the first direction, wherein the third electrode is electrically connected to the source contact; a third gate disposed in the epitaxial layer of the third region and connected to the separated gate structure, wherein the third gate extends from the opposite sidewalls of the third electrode to cover a third electrode top surface of the third electrode and a top surface of the epitaxial layer; a gate contact extending from above the epitaxial layer of the third region into the third gate and electrically connected to the third gate; A gate metal layer is disposed on the epitaxial layer of the third region, wherein the gate metal layer covers and is electrically connected to the gate contact; and A fourth electrode is disposed in the epitaxial layer of the fourth region and extends along the first direction, wherein the fourth electrode is electrically connected to the source contact, wherein the well region is located in the epitaxial layer of the third region and the fourth region, and the interlayer dielectric layer covers the third electrode and the fourth electrode. A method for forming a semiconductor device, comprising: Providing a silicon carbide substrate, the silicon carbide substrate having a first region and a first conductivity type; Growing an epitaxial layer on a top surface of the silicon carbide substrate, wherein the epitaxial layer has the first conductivity type; Forming a first trench in the epitaxial layer in the first region along a first direction; Forming a first electrode in the first trench, wherein the first electrode extends along the first direction; Forming a separate conductive structure on opposite side walls of the first electrode, wherein the separate conductive structure includes a first conductive component and a second conductive component separated from each other; Forming an interlayer dielectric layer comprehensively; Removing the inter-layer dielectric layer on a top surface of the epitaxial layer of the first region, so that at least one of the first conductive component and the second conductive component and the first electrode are exposed from the remaining inter-layer dielectric layer; and Forming a source metal layer on the epitaxial layer of the first region, wherein the source metal layer covers and electrically connects the first electrode, the first conductive component and the second conductive component. The method for forming a semiconductor device as described in claim 11 further includes: Before forming the first trench, a well region is formed in the epitaxial layer in a second region of the silicon carbide substrate, and the well region has a second conductivity type; During the formation of the first trench, a second trench is formed in the epitaxial layer in the second region along the first direction; During the formation of the first electrode, a second electrode is formed in the second trench; During the formation of the separated conductive structure, a first gate and a second gate are formed on opposite side walls of the second electrode; and A plurality of source regions and a plurality of wiring doped regions are formed on the well region of the second region, wherein the source regions and the wiring doped regions are arranged in a staggered manner along a third direction and have opposite conductivity types; A patterning process is performed on the interlayer dielectric layer to form a plurality of first openings in the interlayer dielectric layer of the second region to expose the second electrode, the source regions and the wiring doped regions respectively; and During the formation of the source metal layer, a plurality of source contacts are formed in the first openings. A method for forming a semiconductor device as described in claim 12, wherein the patterning process is performed before removing the interlayer dielectric layer on the top surface of the epitaxial layer in the first region. The method for forming a semiconductor device as described in claim 13 further includes: During the formation of the first trench, a third trench and a fourth trench are formed in the epitaxial layer in a third region and a fourth region of the silicon carbide substrate along the first direction; During the formation of the first electrode, a third electrode and a fourth electrode are formed in the third trench and the fourth trench respectively; During the formation of the separated conductive structure, a third gate is formed in the third trench; During the patterning process, a second opening is formed in the interlayer dielectric layer in the third region to expose the third gate; and Before forming the source metal layer, a gate contact is formed in the second opening. The method for forming a semiconductor device as described in claim 14 further includes: After forming the first openings and the second openings, forming a mask pattern on the epitaxial layer of the second region, the third region, and the fourth region, wherein the mask pattern fills the first openings and the second openings; and After removing the interlayer dielectric layer on the top surface of the epitaxial layer of the first region, removing the mask pattern. A method for forming a semiconductor device as described in claim 14, wherein forming the source contact and the gate contact comprises: Conformally forming a contact barrier layer on the epitaxial layer, in the first openings and the second openings, wherein the contact barrier layer directly contacts at least one of the first conductive component and the second conductive component, the first electrode, the second electrode, and the third gate; Filling a contact conductive layer in the first openings and the second openings; and Removing the contact barrier layer in the fourth region, wherein the source metal layer directly contacts the contact barrier layer in the first region and the second region. A method for forming a semiconductor device as described in claim 16, wherein forming the source metal layer comprises: forming a metal layer throughout, the metal layer covering and physically connecting the contact conductive layer; and removing the metal layer in the fourth region to form the source metal layer on the epitaxial layer in the first region and the second region, and forming a gate metal layer on the epitaxial layer in the third region, wherein the source metal layer is continuously distributed on the epitaxial layer in the first region and the second region. The method for forming a semiconductor device as described in claim 14, wherein forming the first electrode, the second electrode, the third electrode and the fourth electrode comprises: forming a first conductive material, a second conductive material, a third conductive material and a fourth conductive material in the first trench, the second trench, the third trench and the fourth trench, wherein the first conductive material, the second conductive material, the third conductive material and the fourth conductive material comprise the same material; forming an oxide layer on the fourth conductive material; and An oxidation process is performed to form a first dielectric layer, a first gate dielectric layer and a second gate dielectric layer in the first trench, the second trench and the third trench, wherein the formation of the first dielectric layer, the first gate dielectric layer and the second gate dielectric layer includes partially oxidizing a first upper portion of the first conductive material, a second upper portion of the second conductive material and a third upper portion of the third conductive material, and the unoxidized first conductive material, the second conductive material, the third conductive material and the fourth conductive material form the first electrode, the second electrode, the third electrode and the fourth electrode respectively. The method for forming a semiconductor device as described in claim 18 further includes: After forming the first electrode, the second electrode, the third electrode and the fourth electrode, forming an electrode material on the epitaxial layer in an all-round manner, wherein the electrode material fills the first trench, the second trench and the third trench; and performing a patterning process to remove a portion of the electrode material above the epitaxial layer in the first region, the second region and the fourth region to form the first conductive component and the second conductive component in the first trench, the first gate and the second gate in the second trench, and the third gate in the third trench. A method for forming a semiconductor device as described in claim 18, wherein after the patterning process, a side wall of the interlayer dielectric layer is located on the first dielectric layer close to the first electrode.

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