TWI882372B - Photonic integrated circuit structure and fabrication method thereof - Google Patents

Abstract

A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.

Description

Photonic integrated circuit structure and manufacturing method thereof

The present disclosure relates to the field of photonic integrated circuits, and more particularly to a photonic integrated circuit structure and a method for manufacturing the same, wherein the end of a waveguide has an inclined reflector.

Photonic integrated circuit (PIC) uses semiconductor manufacturing process to directly manufacture various optical components such as modulators, optical couplers, switches, etc. on an integrated circuit chip. Compared with electronic integrated circuits, which use electrons to transmit signals or perform calculations and use copper wires to connect various components, photonic integrated circuits mainly use photons for signal transmission and calculations, and use waveguides to connect various components. Compared with electrons, photons can carry wider bandwidth and faster data transmission speeds, which can provide higher transmission rates, large amounts of data transmission and better communication quality for the computing, transmission and sensing industries.

In photonic integrated circuits, optical couplers can be used to read data stored on the chip. They are generally divided into grating coupling and edge coupling. For edge coupling, its design is simple, the available bandwidth is wider than grating coupling, and the optical loss is low. However, the cleavage surface of the edge coupling element needs to be polished to have a better optical coupling efficiency, which makes the process of edge coupling elements more complicated. For grating coupling, its use bandwidth is narrower, and the optical loss may be larger. Although the process of grating coupling elements is simpler than that of edge coupling elements, grating coupling still requires the optical fiber to be set at a specific angle and position to obtain a stronger optical signal.

In view of this, the present disclosure proposes a photonic integrated circuit structure and a manufacturing method thereof, wherein the waveguide end thereof has an inclined reflector, which can replace the conventional grating coupling element, so that the bandwidth used is wider and the position of the optical fiber is more accurate, and a stronger optical signal can be obtained without adjusting the optical fiber at a specific angle. The optical coupling efficiency is high and the optical loss is low, which is conducive to providing a higher transmission rate, a larger amount of data transmission and better communication quality. In addition, the size of the inclined reflector at the end of the waveguide is much smaller than that of the grating coupling element, which is conducive to the miniaturization of the photonic integrated circuit.

According to an embodiment of the present disclosure, a photonic integrated circuit structure is provided, including a semiconductor substrate, a waveguide, a mirror coating, a cladding layer, a hole, and an optical fiber. The waveguide is disposed on the semiconductor substrate and has an inclined surface, the mirror coating is disposed longitudinally on the inclined surface, the cladding layer covers the waveguide and the mirror coating, the hole is disposed on the semiconductor substrate or the cladding layer, and the hole overlaps with the inclined surface in the vertical direction, and the optical fiber is disposed in the hole to receive reflected light from the mirror coating.

According to an embodiment of the present disclosure, a method for manufacturing a photonic integrated circuit is provided, comprising the following steps: providing a semiconductor substrate; forming a waveguide on the semiconductor substrate, wherein the waveguide has an inclined surface; forming a mirror coating on the inclined surface in a longitudinal direction; forming a cladding layer to cover the waveguide and the mirror coating layer; forming a hole in the semiconductor substrate or the cladding layer, wherein the hole overlaps with the inclined surface in a vertical direction; and providing an optical fiber to be placed in the hole to receive reflected light from the mirror coating layer.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the accompanying drawings.

100: Photonic integrated circuit structure

101:Semiconductor substrate

101B: Back side of semiconductor substrate

103: Holes

105: Insulation layer

106: Waveguide material layer

107: Waveguide

107A: Top surface of waveguide

107B: Bottom surface of waveguide

107S: Inclined surface

107P: Initial contour of the waveguide

107P-S: Predetermined formation area of inclined surface

107PW: Sidewall

108: Material layer for mirror coating

109: Mirror coating

111: Coating layer

113: Hole

120: Optical fiber

130A: Incident light

130B: Reflected light

140, 150, 160, 170: Mask

10. A, B: Section structure

θ1, θ2: angle of intersection

W: Width

S101, S103, S105, S106A, S106B, S107, S108A, S108B, S109, S110, S111, S112, S113, S114, S115, S116: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a cross-sectional schematic diagram of a photonic integrated circuit structure of an embodiment of the present disclosure.

Figure 2 is a cross-sectional schematic diagram of a photonic integrated circuit structure of another embodiment of the present disclosure.

Figures 3, 4, 5 and 6 are cross-sectional schematic diagrams and plan schematic diagrams of some stages of the method for manufacturing a photonic integrated circuit of an embodiment of the present disclosure.

Figures 7, 8, 9 and 10 are cross-sectional schematic diagrams of some stages of the method for manufacturing a photonic integrated circuit of other embodiments of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the figure. In addition to the orientation shown in the figure, these spatially related terms are also used to describe the possible orientations of the photonic integrated circuit during use and operation. As the orientation of the photonic integrated circuit is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

In the present disclosure, "compound semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element, which may also be referred to as a group III-V compound semiconductor. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Furthermore, "compound semiconductors" may be binary compound semiconductors, ternary compound semiconductors or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), their analogs or combinations of the above compounds, but not limited thereto.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a photonic integrated circuit structure and a manufacturing method thereof, wherein the waveguide end thereof has an inclined surface, and a mirror coating is disposed on the inclined surface to generate an inclined reflector. The inclined reflector can replace the grating coupling element, so that the bandwidth used is wider and there is no wavelength dependence. In the photonic integrated circuit structure of the present disclosure, the optical fiber is precisely aligned, and a strong optical signal can be obtained without adjusting the optical fiber at a specific angle, thereby improving the optical coupling efficiency and reducing light loss. Moreover, the angle of the inclined surface can be adjusted according to demand by using an etching process. In general, the photonic integrated circuit of the present disclosure can provide a higher transmission rate, a larger amount of data transmission, and a better optical transmission quality. In addition, the size of the inclined surface at the end of the waveguide is much smaller than that of the grating coupling element, which is conducive to the miniaturization of photonic integrated circuits.

FIG. 1 is a cross-sectional view of a photonic integrated circuit structure 100 according to an embodiment of the present disclosure. The photonic integrated circuit structure 100 includes a semiconductor substrate 101 having a hole 103 for placing an optical fiber 120 so that the optical fiber 120 can be precisely aligned with the inclined surface of the waveguide. In some embodiments, the semiconductor substrate 101 can be composed of silicon (Si), germanium (Ge) or a III-V compound semiconductor, such as indium phosphide (InP), gallium arsenide (GaAs), etc., but is not limited thereto. A waveguide 107 is disposed on the semiconductor substrate 101. The end of the waveguide 107 has an inclined surface 107S. The inclined surface 107S vertically corresponds to the hole 103 in a vertical direction (e.g., the Z-axis direction). The bottom surface 107B of the waveguide 107 is close to the semiconductor substrate 101, and the top surface 107A of the waveguide 107 is far from the semiconductor substrate 107. In this embodiment, the angle θ1 between the inclined surface 107S and the bottom surface 107B of the waveguide 107 can be greater than 0 degrees to about 45 degrees. Within this angle range, the light transmitted in the waveguide 107 can be reflected by the mirror coating on the inclined surface 107S and transmitted downward to the optical fiber 120. In some embodiments, the composition of the waveguide 107 can be silicon (Si), silicon nitride (SiN), germanium (Ge) or a III-V compound semiconductor, such as indium phosphide (InP), gallium arsenide (GaAs), etc., but is not limited thereto. The mirror coating 109 is disposed longitudinally on the inclined surface 107S. In some embodiments, the mirror coating 109 may be composed of metal such as aluminum (Al), silver (Ag), etc., or a distributed Bragg reflector (DBR) coating, which is a multi-layer film stacked by materials with different refractive indices. The thickness of the mirror coating 109 may be about 100 angstroms (Å) to about 10,000 angstroms (Å), but is not limited thereto, and may be adjusted according to the size requirements of the waveguide.

In addition, the photonic integrated circuit structure 100 further includes an insulating layer 105 disposed between the semiconductor substrate 101 and the waveguide 107. The refractive index of the insulating layer 105 is lower than the refractive index of the waveguide 107, so that the light in the waveguide 107 can generate total internal reflection. In some embodiments, the insulating layer 105 is, for example, a buried oxide layer (BOX), which can be composed of silicon oxide. In one embodiment, the waveguide 107, the insulating layer 105 and the semiconductor substrate 101 can be formed by a semiconductor on insulator (SOI) substrate covered with an insulating layer. In addition, the depth of the hole 103 can be controlled by an etching process for forming the hole 103, so that the bottom surface of the hole 103 is located at the interface between the semiconductor substrate 101 and the insulating layer 105, or is located in the insulating layer 105, or is located in the semiconductor substrate 101. In addition, the photonic integrated circuit structure 100 further includes a cladding layer 111 covering the waveguide 107 and the mirror coating layer 109, and the cladding layer 111 contacts the surface of the insulating layer 105. The refractive index of the cladding layer 111 is also lower than the refractive index of the waveguide 107. In one embodiment, the cladding layer 111 is, for example, an intermetal dielectric layer (IMD), and the composition of the cladding layer 111 may be silicon oxide. In this embodiment, the incident light 130A is transmitted along the X-axis direction in the waveguide 107, and the reflected light 130B reflected by the mirror coating 109 is transmitted downward along the Z-axis direction, so that the optical fiber 120 disposed in the hole 103 receives the reflected light from the mirror coating 109.

According to the embodiment of the present disclosure, the hole 103 of the semiconductor substrate 101 can be formed by photolithography and etching processes, and the inclined surface 107S of the waveguide 107 is also formed by photolithography and etching processes, so that the positions of the hole 103 and the inclined surface 107S can be accurately controlled, so that the hole 103 overlaps with the inclined surface 107S of the waveguide 107 in the vertical direction, so that the optical fiber 120 arranged in the hole 103 can be accurately aligned with the mirror coating 109 on the inclined surface 107S, thereby improving the light coupling efficiency, and the optical fiber 120 arranged in the hole 103 can also reduce light loss. In addition, the angle θ1 between the inclined surface 107S and the bottom surface 107B of the waveguide 107 can be adjusted according to the position of the optical fiber 120 through the etching process to improve the light coupling efficiency.

Compared with the grating coupling element, which is affected by the grating period and causes a large wavelength change, the optical coupling efficiency of the grating coupling element is low and the bandwidth used is narrow. According to the embodiment of the present disclosure, there is an inclined surface 107S at the end of the waveguide 107, and a mirror coating 109 is set on the inclined surface 107S to reflect the light, so that the optical coupling has no wavelength dependence and will not be affected by the wavelength, thereby improving the optical coupling efficiency, and the usable bandwidth is also wider than that of the grating coupling element. Therefore, the photonic integrated circuit structure 100 of the embodiment of the present disclosure can provide a higher transmission rate, a larger amount of data transmission and a better optical transmission quality. Furthermore, from a top view, the width of the inclined surface 107S and the width of a portion of the waveguide 107 outside the inclined surface 107S can be substantially the same. In some embodiments, the width of the inclined surface 107S in the Y-axis direction can be about 0.1 micrometers (μm) to about 2 micrometers (μm). Compared to the grating width of about 20 micrometers (μm) and the grating length of about 15 micrometers (μm) required for the grating coupling element, the size of the inclined reflector at the end of the waveguide of the embodiment disclosed in the present invention is smaller, which is conducive to the miniaturization of the photonic integrated circuit.

FIG. 2 is a cross-sectional view of a photonic integrated circuit structure 100 according to another embodiment of the present disclosure. The photonic integrated circuit structure 100 includes a semiconductor substrate 101. A waveguide 107 is disposed on the semiconductor substrate 101 and has an inclined surface 107S. A mirror coating 109 is disposed longitudinally on the inclined surface 107S. The bottom surface 107B of the waveguide 107 is close to the semiconductor substrate 101, and the top surface 107A of the waveguide 107 is far away from the semiconductor substrate 101. In this embodiment, the angle θ2 between the inclined surface 107S and the top surface 107A of the waveguide 107 can be greater than 0 degrees to about 45 degrees, so that the light transmitted in the waveguide 107 is reflected by the mirror coating 109 on the inclined surface 107S and transmitted upward to the optical fiber 120.

The photonic integrated circuit structure 100 further includes a cladding layer 111 covering the waveguide 107 and the mirror coating 109. In this embodiment, the cladding layer 111 has a hole 113 vertically corresponding to the inclined surface 107S, and the bottom surface of the hole 113 is located in the cladding layer 111. The refractive index of the cladding layer 111 is lower than the refractive index of the waveguide 107, so that the light in the waveguide 107 can generate total internal reflection. The cladding layer 111 can be an intermetallic dielectric layer (IMD). In this embodiment, the optical fiber 120 is disposed in the hole 113 of the cladding layer 111 to receive the reflected light from the mirror coating 109. In addition, the photonic integrated circuit structure 100 may further include an insulating layer 105 disposed between the semiconductor substrate 101 and the waveguide 107, the refractive index of the insulating layer 105 being lower than the refractive index of the waveguide 107, so that the light in the waveguide 107 can generate total internal reflection, the insulating layer 105 may be a buried oxide layer (BOX), and the cladding layer 111 contacts the surface of the insulating layer 105, so that the waveguide 107 and the mirror coating 109 are surrounded by the cladding layer 111 and the insulating layer 105. In some embodiments, the waveguide 107, the insulating layer 105 and the semiconductor substrate 101 may be formed by a semiconductor on an insulating layer (SOI) substrate. The composition of the semiconductor substrate 101, waveguide 107, mirror coating 109, cladding layer 111 and insulating layer 105 of the photonic integrated circuit structure 100 in FIG. 2 , as well as the width of the inclined surface 107S and the thickness of the mirror coating 109 can all be found in the relevant description of the photonic integrated circuit structure 100 in FIG. 1 above, which will not be repeated here. In this embodiment, the incident light 130A is transmitted along the X-axis direction in the waveguide 107, and the reflected light 130B reflected by the mirror coating 109 is transmitted upward along the Z-axis direction, so that the optical fiber 120 disposed in the hole 113 receives the reflected light from the mirror coating 109.

According to the embodiment of the present disclosure, the hole 113 of the cladding layer 111 can be formed by photolithography and etching processes, and the inclined surface 107S of the waveguide 107 is also formed by photolithography and etching processes, so the positions of the hole 113 and the inclined surface 107S can be accurately controlled, so that the hole 113 overlaps with the inclined surface 107S of the waveguide 107 in the vertical direction, and thus the optical fiber 120 disposed in the hole 113 can be accurately aligned with the mirror coating 109 on the inclined surface 107S to improve the light coupling efficiency. At the same time, disposing the optical fiber 120 in the hole 113 can also reduce light loss. In addition, the angle θ2 between the inclined surface 107S and the top surface 107A of the waveguide 107 can be adjusted by etching process according to the position of the optical fiber 120 to improve the light coupling efficiency. According to the embodiment of the present disclosure, the end of the waveguide 107 has an inclined surface 107S, and a mirror coating 109 is set on the inclined surface 107S to reflect the light, so that the light coupling will not be affected by the wavelength, so as to improve the light coupling efficiency, and the usable bandwidth is also wider than that of the grating coupling element. Therefore, the photonic integrated circuit structure 100 of the embodiment of the present disclosure can provide a higher transmission rate, a larger amount of data transmission and a better light transmission quality. In addition, the size of the inclined surface 107S of the embodiment disclosed herein is smaller than that of the grating coupling element, which is beneficial to the miniaturization of the photonic integrated circuit.

Figures 3, 4, 5 and 6 are cross-sectional schematic diagrams and plan schematic diagrams of some stages of a method for manufacturing a photonic integrated circuit according to an embodiment of the present disclosure, wherein Figures 3, 4 and 5 show the cross-sectional schematic diagrams and plan schematic diagrams corresponding to each step. Referring to FIG. 3, in step S101, in one embodiment, an insulating layer is first provided to cover a semiconductor (SOI) substrate, including a semiconductor substrate 101, an insulating layer 105, and a waveguide material layer 106 stacked in sequence from bottom to top, wherein the semiconductor substrate 101 is, for example, a silicon wafer, the insulating layer 105 is, for example, a buried oxide layer (BOX), and the waveguide material layer 106 is, for example, a silicon epitaxial layer, but not limited thereto, the semiconductor substrate 101 and the waveguide material layer 106 may also be other suitable semiconductor materials, and the waveguide material layer 106 may also be replaced by a silicon nitride layer.

Then, in step S101, a mask 140 is formed on the waveguide material layer 106, such as a patterned photoresist or a hard mask. The mask 140 covers a portion of the waveguide material layer 106 and exposes another portion of the waveguide material layer 106. As shown in the plan view, the portion of the waveguide material layer 106 covered by the mask 140 corresponds to the initial outline of the waveguide to be formed subsequently.

Next, still referring to FIG. 3, in step S103, an etching process is performed to pattern the waveguide material layer 106, remove another portion of the waveguide material layer 106 not covered by the mask 140, and leave a portion of the waveguide material layer 106 covered by the mask 140 to form an initial profile 107P of the waveguide. Then, a stripping process, such as an ashing or immersion process, is used to remove the mask 140.

Afterwards, referring to FIG. 4, in step S105, a mask 150 is formed on the insulating layer 105. The mask 150 is, for example, a patterned photoresist or a hard mask, which covers a portion of the initial outline 107P of the waveguide and exposes another portion of the initial outline 107P of the waveguide. As shown in the plan view, the other portion of the initial outline 107P of the waveguide not covered by the mask 150 is a predetermined formation area 107P-S for subsequently forming an inclined surface.

Next, still referring to FIG. 4 , in step S107, an etching process is performed to remove the upper portion of the initial waveguide profile 107P (also referred to as the waveguide material layer 106) located in the predetermined formation region 107P-S to form a slope 107S of the waveguide 107, wherein the angle θ1 between the slope 107S and the bottom surface 107B of the waveguide 107 is greater than 0 degrees to about 45 degrees. Then, a stripping process is used to remove the mask 150. In some embodiments, a multi-step isotropic dry etching process, such as a plasma etching process, or a grayscale lithography technique may be used to etch out the slope 107S. As shown in the plan view, in some embodiments, the width W of the inclined surface 107S can be the same as the width of other parts of the waveguide 107. The width W is, for example, about 0.1 micrometers (μm) to about 2 micrometers (μm), but is not limited thereto and can be adjusted according to the size of the waveguide 107.

Then, referring to FIG. 5 , in step S109, a mirror coating material layer 108 is conformally deposited on the insulating layer 105 and the waveguide 107, and is conformally formed on the surface, sidewalls, and inclined surface 107S of the waveguide 107. In some embodiments, the material layer 108 may be composed of a metal such as aluminum (Al), silver (Ag), etc., or a distributed Bragg reflector (DBR) coating, and the thickness of the material layer 108 is, for example, about 100 angstroms (Å) to about 10,000 angstroms (Å). Then, in step S109, a mask 170 is formed on the material layer 108, such as a patterned photoresist or a hard mask. As shown in the plan view, the mask 170 covers the material layer 108 in the inclined surface 107S area and exposes the material layer 108 outside the inclined surface 107S.

Next, still referring to FIG. 5, in step S111, an etching process is performed to remove the material layer 108 outside the inclined surface 107S to form a mirror coating 109. Then, a stripping process is used to remove the mask 170. The mirror coating 109 is formed longitudinally on the inclined surface 107S. In addition, in some embodiments, the mirror coating 109 can also cover a portion of the side wall of the waveguide 107 adjacent to the inclined surface 107S.

Then, referring to FIG. 6, in step S113, a cladding layer 111 is formed on the insulating layer 105 and covers the waveguide 107 and the mirror coating 109. The cladding layer 111 contacts the insulating layer 105 to surround the waveguide 107 and the mirror coating 109. In some embodiments, the cladding layer 111 may be an intermetallic dielectric layer (IMD), which is composed of, for example, silicon oxide.

Next, still referring to FIG. 6 , in step S115 , the structure of step S113 is turned upside down so that the back side 101B of the semiconductor substrate 101 faces upward. Then, photolithography and etching processes are used to etch from the back side 101B of the semiconductor substrate 101 to form a hole 103 in the semiconductor substrate 101 , and the position of the hole 103 vertically corresponds to the inclined surface 107S. The depth of the hole 103 is controlled by the etching process. In some embodiments, the bottom surface of the hole 103 can be located at the interface between the semiconductor substrate 101 and the insulating layer 105 to form a through substrate via hole (TSV) penetrating the semiconductor substrate 101 , or the bottom surface of the hole 103 can extend into the insulating layer 105 . In another embodiment, the bottom surface of the hole 103 can be located in the semiconductor substrate 101, and a thin layer of the semiconductor substrate 101 is retained between the bottom surface of the hole 103 and the insulating layer 105. The thickness of this thin layer does not affect the optical fiber 120 subsequently placed in the hole 103 to receive the reflected light from the mirror coating 109. Afterwards, as shown in FIG. 1, the optical fiber 120 is arranged in the hole 103 to complete the photonic integrated circuit structure 100.

Figures 7, 8, 9 and 10 are cross-sectional schematic diagrams of some stages of the manufacturing method of the photonic integrated circuit of other embodiments of the present disclosure. Referring to Figure 7, in one embodiment, in step S106A, following step S101 and step S103 of the aforementioned Figure 3, after forming the initial profile 107P of the waveguide, in this embodiment, a mask 160 is formed on the insulating layer 105. The mask 160 is, for example, a patterned photoresist or a hard mask, which covers the initial profile 107P of the waveguide and exposes a side wall 107PW of the initial profile 107P. The side wall 107PW is located in a predetermined formation area 107P-S where a slope is subsequently formed.

Next, still referring to FIG. 7, in step S108A, an etching process is performed to laterally etch the lower portion of the initial outline 107P (also referred to as the waveguide material layer 106) of the waveguide located in the predetermined formation area 107P-S to form a slope 107S, wherein the angle θ2 between the slope 107S and the top surface 107A of the waveguide 107 is greater than 0 degrees to about 45 degrees. Then, a stripping process is used to remove the mask 160.

Referring to FIG. 8 , in another embodiment, in step S106B, the inclined surface 107S of the waveguide 107 of step S107 of FIG. 4 may be formed first, and then the cross-sectional structure 10 of step S107 of FIG. 4 may be turned upside down, and then the top surface 107A of the waveguide 107 of step S107 may be transferred and bonded to another semiconductor substrate 101 and the insulating layer 105 by a reverse bonding method. Next, in step S108B, the semiconductor substrate 101 and the insulating layer 105 in the cross-sectional structure 10 of step S107 are separated from the waveguide 107, so that the top surface 107A of the waveguide 107 of step S107 becomes the bottom surface 107B of the waveguide 107 of step S108B, and the bottom surface 107B of the waveguide 107 of step S107 becomes the top surface 107A of the waveguide 107 of step S108B. In this embodiment, the angle θ2 between the top surface 107A of the waveguide 107 and the inclined surface 107S is the same as the angle θ1 of step S107, and both are greater than 0 degrees to about 45 degrees.

Then, referring to FIG. 9 , in step S110 , a mirror coating material layer 108 is sequentially deposited on the surface of the insulating layer 105 and the surface, sidewalls and inclined surface 107S of the waveguide 107 using, for example, a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD). Next, still referring to FIG. 9 , in step S112 , an etching process is performed to remove the material layer 108 outside the inclined surface 107S to form a mirror coating layer 109 . In one embodiment, in step S112, a mask (not shown) may be used to cover the surface of the waveguide 107, and the material layer 108 on the surface of the insulating layer 105 may be completely removed by a plasma etching process to form a mirror coating layer 109 as shown in the cross-sectional structure A of FIG. 9 . In another embodiment, in step S112, the inclined surface 107S of the waveguide 107 can be used as a mask, and the material layer 108 outside the vertical projection area of the inclined surface 107S can be removed by a plasma etching process to form a mirror coating 109 as shown in the cross-sectional structure B of Figure 9, wherein some material layer 108 will remain on the surface of the insulating layer 105 within the vertical projection area of the inclined surface 107S, becoming a part of the mirror coating 109.

Then, referring to FIG. 10 , in step S114, a cladding layer 111 is formed on the insulating layer 105 and covers the waveguide 107 and the mirror coating 109. The cladding layer 111 contacts the insulating layer 105 to surround the waveguide 107 and the mirror coating 109. In some embodiments, the cladding layer 111 may be an intermetallic dielectric layer (IMD) composed of, for example, silicon oxide. Next, still referring to FIG. 10, in step S116, a hole 113 is formed in the cladding layer 111 by using photolithography and etching processes. The position of the hole 113 corresponds vertically to the inclined surface 107S, and the bottom surface of the hole 113 is located in the cladding layer 111. A thin layer of the cladding layer 111 is retained between the bottom surface of the hole 113 and the waveguide 107. The thickness of this thin layer does not affect the optical fiber 120 placed in the hole 113 to receive the reflected light from the mirror coating 109. Afterwards, as shown in FIG. 2, the optical fiber 120 is arranged in the hole 113 of the cladding layer 111 to complete the photonic integrated circuit structure 100.

According to some embodiments of the present disclosure, the waveguide end included in the photonic integrated circuit structure has an inclined surface, and a mirror coating is disposed on the inclined surface to generate an inclined reflector. This inclined reflector can replace the grating coupling element, so that the bandwidth used is wider and there is no wavelength dependence. In addition, the optical fiber located in the hole of the semiconductor substrate or the hole of the cladding layer can be accurately aligned with the inclined surface of the waveguide to improve the light coupling efficiency and reduce light loss. At the same time, the angle of the inclined surface can also be adjusted according to the position of the optical fiber by using an etching process to increase the light coupling efficiency. In general, the photonic integrated circuit disclosed in the present disclosure can provide a higher transmission rate, a larger amount of data transmission, and a better light transmission quality. In addition, the size of the inclined surface at the end of the waveguide is much smaller than that of the grating coupling element, which is conducive to the miniaturization of photonic integrated circuits.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Photonic integrated circuit structure

101:Semiconductor substrate

103: Holes

105: Insulation layer

107: Waveguide

107A: Top surface of waveguide

107B: Bottom surface of waveguide

107S: Inclined surface

109: Mirror coating

111: Coating layer

120: Optical fiber

130A: Incident light

130B: Reflected light

θ1: angle of intersection

Claims (19)

A photonic integrated circuit structure includes: a semiconductor substrate; a waveguide disposed on the semiconductor substrate and having an inclined surface, wherein the width of the inclined surface is the same as the width of an end of the waveguide receiving an incident light when viewed from above; a mirror coating disposed longitudinally on the inclined surface; a cladding layer covering the waveguide and the mirror coating; a hole disposed on the semiconductor substrate or the cladding layer, and the hole overlaps with the inclined surface in a vertical direction; and an optical fiber disposed in the hole to receive reflected light from the mirror coating. The photonic integrated circuit structure as described in claim 1 further includes: An insulating layer disposed between the semiconductor substrate and the waveguide, and the cladding layer contacts the insulating layer. A photonic integrated circuit structure as described in claim 2, wherein the hole is disposed in the semiconductor substrate, and the bottom surface of the hole is located at the interface between the semiconductor substrate and the insulating layer, in the insulating layer, or in the semiconductor substrate. A photonic integrated circuit structure as described in claim 1, wherein the hole is arranged in the semiconductor substrate, the optical fiber is located directly below the mirror coating, a bottom surface of the waveguide is close to the semiconductor substrate, a top surface of the waveguide is away from the semiconductor substrate, and the angle between the inclined surface and the bottom surface is greater than 0 degrees to 45 degrees. A photonic integrated circuit structure as described in claim 1, wherein the hole is arranged in the cladding layer, the optical fiber is located directly above the mirror coating, a bottom surface of the waveguide is close to the semiconductor substrate, a top surface of the waveguide is away from the semiconductor substrate, and the angle between the inclined surface and the top surface is greater than 0 degrees to 45 degrees. A photonic integrated circuit structure as described in claim 1, wherein the waveguide is composed of silicon (Si), silicon nitride (SiN), germanium (Ge) or a Group III-V compound semiconductor, and the semiconductor substrate is composed of silicon, germanium or a Group III-V compound semiconductor. A photonic integrated circuit structure as described in claim 1, wherein the mirror coating comprises a metal or a distributed Bragg reflector coating. A photonic integrated circuit structure as described in claim 1, wherein the waveguide has a uniform width from the end receiving the incident light to the inclined surface when viewed from a top view. A photonic integrated circuit structure as described in claim 2, wherein the cladding layer includes a metal interlayer dielectric layer and the insulating layer includes a buried oxide layer. A method for manufacturing a photonic integrated circuit comprises: providing a semiconductor substrate; forming a waveguide on the semiconductor substrate, wherein the waveguide has an inclined surface, wherein the width of the inclined surface is the same as the width of an end of the waveguide receiving an incident light when viewed from above; forming a mirror coating on the inclined surface in a longitudinal direction; forming a cladding layer to cover the waveguide and the mirror coating; forming a hole in the semiconductor substrate or the cladding layer, wherein the hole overlaps with the inclined surface in a vertical direction; and providing an optical fiber to be placed in the hole to receive reflected light from the mirror coating. The method for manufacturing a photonic integrated circuit as described in claim 10 further includes: Providing an insulating layer on the semiconductor substrate; and Providing a waveguide material layer on the insulating layer. A method for manufacturing a photonic integrated circuit as described in claim 11, wherein the hole is formed in the semiconductor substrate, and forming the waveguide having the inclined surface comprises: patterning the waveguide material layer to form an initial outline of the waveguide; using a mask to cover a portion of the initial outline to expose a predetermined formation area of the inclined surface; and etching an upper portion of the waveguide material layer located in the predetermined formation area to form the inclined surface, wherein a bottom surface of the waveguide is close to the semiconductor substrate, a top surface of the waveguide is away from the semiconductor substrate, and the angle between the inclined surface and the bottom surface is greater than 0 degrees to 45 degrees. A method for manufacturing a photonic integrated circuit as described in claim 12, wherein forming the mirror coating comprises: Depositing a material layer of the mirror coating on the surface, sidewalls and inclined surface of the waveguide in a longitudinal direction; Covering the inclined surface with a mask and exposing the material layer outside the inclined surface; and Etching and removing the exposed material layer to form the mirror coating. A method for manufacturing a photonic integrated circuit as described in claim 11, wherein the cladding layer is formed in contact with the insulating layer before the hole is formed in the semiconductor substrate. A method for manufacturing a photonic integrated circuit as described in claim 11, wherein forming the hole in the semiconductor substrate includes etching from the back side of the semiconductor substrate to the interface between the semiconductor substrate and the insulating layer, in the insulating layer, or in the semiconductor substrate. A method for manufacturing a photonic integrated circuit as described in claim 11, wherein the hole is formed in the cladding layer, and forming the waveguide having the inclined surface comprises: Patterning the waveguide material layer to form an initial profile of the waveguide, the initial profile including a predetermined formation area of the inclined surface; Using a mask to cover the initial profile and expose a side wall of the initial profile located in the predetermined formation area; and Laterally etching a lower portion of the waveguide material layer located in the predetermined formation area to form the inclined surface, wherein a bottom surface of the waveguide is close to the semiconductor substrate, a top surface of the waveguide is away from the semiconductor substrate, and the angle between the inclined surface and the top surface is greater than 0 degrees to 45 degrees. A method for manufacturing a photonic integrated circuit as described in claim 16, wherein forming the mirror coating comprises: Depositing a material layer of the mirror coating on the surface, sidewalls and inclined surface of the waveguide in a longitudinal direction; and Etching away the material layer outside the inclined surface to form the mirror coating. A method for manufacturing a photonic integrated circuit as described in claim 10, wherein the hole is formed in the cladding layer, and forming the waveguide with the inclined surface comprises: Forming the waveguide with the inclined surface on another semiconductor substrate, wherein a bottom surface of the waveguide is close to the other semiconductor substrate, a top surface of the waveguide is away from the other semiconductor substrate, and the angle between the inclined surface and the bottom surface is greater than 0 degrees to 45 degrees; Bonding the top surface of the waveguide to the semiconductor substrate; and Separating the other semiconductor substrate from the waveguide. A method for manufacturing a photonic integrated circuit as described in claim 10, wherein the waveguide material layer is composed of silicon (Si), silicon nitride (SiN), germanium (Ge) or a Group III-V compound semiconductor, and the semiconductor substrate is composed of silicon, germanium or a Group III-V compound semiconductor.

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