TWI881597B - Memory device and operating method thereof - Google Patents

Abstract

A memory device includes a first memory cell, a first switch element and a second switch element. The first memory cell is configured to store a first data bit, and configured to perform a search operation to the first data bit by a first search bit to generate a first current signal. The first switch element is coupled in series with the first memory cell, and configured to be turned on in response to a clamp voltage level during the search operation, to clamp the first current signal. The second switch element is coupled in series with the first memory cell, and configured to be turned on in response to a first enable voltage level. The first enable voltage level is larger than the clamp voltage level.

Description

Memory device and operating method thereof

This disclosure relates to a memory technology, and more particularly to a memory device and a method for operating the memory device.

A memory device includes a plurality of memory cells for storing data bits. The memory cells can compare data bits and search bits to perform a search operation. During the search operation, the memory cells generate corresponding current signals according to the comparison results. However, the current signal may operate in a saturation region with a large variation, causing misunderstanding of the matching results of the search operation. Therefore, how to design to solve the above problems is an important topic in this field.

The present invention includes a memory device. The memory device includes a first memory unit, a first switch element, and a second switch element. The first memory unit is used to store a first data bit, and to perform a search operation on the first data bit through a first search bit to generate a first current signal. The first switch element is coupled in series with the first memory unit, and is used to conduct in response to a clamping voltage level during the search operation to clamp the first current signal. The second switch element is coupled in series with the first memory unit, and is used to conduct in response to a first enabling voltage level during the search operation. The first enabling voltage level is greater than the clamping voltage level.

In some embodiments, before the search operation, the first memory unit is further used to perform a write operation to write the first data bit, and during the write operation, the first switch element is turned on in response to the first enabling voltage level.

In some embodiments, the memory device further includes a second memory unit and a third switch element. The second memory unit is used to store a second data bit and to perform a search operation on the second data bit through a second search bit to generate a second current signal. The third switch element is coupled in series with the second memory unit between the first node and the second node and is turned on in response to the clamping voltage level during the search operation to clamp the second current signal. The first memory unit and the first switch element are coupled in series between the first node and the second node.

In some embodiments, the memory device further includes a third switch element and a fourth switch element. The third switch element is used to turn on in response to a second enable voltage level during a search operation. The fourth switch element is used to turn on in response to a second enable voltage level during a search operation. The first memory unit, the first switch element, and the second switch element are coupled in series between the third switch element and the fourth switch element, and the second enable voltage level is different from the first enable voltage level.

In some embodiments, the memory device further includes a third switch element. The third switch element is coupled in series with the first memory unit between the first switch element and the second switch element, and is used to turn on in response to a second enabling voltage level during a search operation. The second enabling voltage level is different from the first enabling voltage level.

In some embodiments, the memory device further includes a third switch element. The third switch element is used to conduct in response to the clamping voltage level during the search operation to clamp the second current signal. The first memory unit is further used to perform a search operation on the first data bit and the first search bit to generate a second current signal. The first memory unit includes a fourth switch element and a fifth switch element coupled in parallel to each other. The fourth switch element is coupled in series with the first switch element, and the fifth switch element is coupled in series with the third switch element.

The present invention includes an operating method of a memory device. The operating method includes: storing a first data bit by a first memory unit; comparing the first data bit and a first search bit to generate a first current signal; clamping the first current signal by a first switch element according to a clamping voltage level; and turning on a second switch element according to a first enabling voltage level. The first current signal flows through the second switch element, and the first enabling voltage level is greater than the clamping voltage level.

In some embodiments, the operating method further includes: comparing the first data bit and the first search bit to generate a second current signal; and clamping the second current signal according to the clamping voltage level by a third switching element. The third switching element is coupled in parallel with the first switching element.

In some embodiments, the operating method further includes: storing a second data bit by a second memory cell; comparing the second data bit with the first search bit to generate a second current signal; and clamping the second current signal according to a clamping voltage level by a third switching element. The third switching element is coupled in parallel with the first switching element.

In some embodiments, before comparing the first data bit and the first search bit, the first switch element is turned on according to the first enabling voltage level.

100A:Memory system

140:Encoding device

150, 159: Memory array

130, 135: Page buffer

191: Combined with sorting device

160:Data encoder

170:Search encoder

199:2D memory array

110: Data signal

111: Encoded data signal

120: Searching for signals

171: string selection line

172: word line signal

180: Bit line signal

190:Search results

100B, 200, 300, 400, 500, 600, 700: memory device

LY1~LYM: layer

BK1~BK512: Block

WL1_1, WL2_1, WL511_1, WL512_1, WL1_2, WL2_2, WL511_2, WL512_2: word line signal

SSL1~SSL512: string selection line signal

X, Y, Z: direction

CL1~CL512: memory row

N21, N22: nodes

BL1: bit line signal

I1~I512: current signal

TS1~TS512, FC1_1~FC512_M, TG1~TG512, TC1~TC512: switch components

GSL: Ground select line signal

CSL: Control Select Line Signal

MC1_1~MC512_1: memory unit

VPASS: Enable voltage level

VCLAMP: clamping voltage level

VSS: reference voltage signal

201, 301, 401: Timing diagram

P21, P22, P31, P32, P41, P42: Period

VL: Disable voltage level

800: Operation method

OP81~OP84: Operation

Figure 1A is a schematic diagram of a memory system according to one embodiment of the present invention.

Figure 1B is a schematic diagram of a memory device according to one embodiment of the present invention.

Figure 2A is a schematic diagram of a memory device according to some embodiments of the present invention.

FIG. 2B is a timing diagram of the operation of the memory device shown in FIG. 2A according to some embodiments of the present invention.

Figure 3A is a schematic diagram of a memory device according to some embodiments of the present invention.

FIG. 3B is a timing diagram of the operation of the memory device shown in FIG. 3A according to some embodiments of the present invention.

Figure 4A is a schematic diagram of a memory device according to some embodiments of the present invention.

FIG. 4B is a timing diagram of the operation of the memory device shown in FIG. 4A according to some embodiments of the present invention.

FIG. 5 is a schematic diagram of a memory device according to some embodiments of the present invention.

Figure 6 is a schematic diagram of a memory device according to some embodiments of the present invention.

Figure 7 is a schematic diagram of a memory device according to some embodiments of the present invention.

Figure 8 is a flow chart of the operation method of the memory device according to some embodiments of the present invention.

In this article, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit this case.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by persons of ordinary skill in the art to which this case belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art and this case, and will not be interpreted as idealized or overly formal meanings unless expressly so defined herein.

The terms used herein are for the purpose of describing specific embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "comprise" specify the presence of the features, regions, wholes, steps, operations, elements, and/or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts, and/or combinations thereof.

The following will disclose multiple implementations of the present invention with drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

FIG. 1A is a schematic diagram of a memory system 100A according to some embodiments of the present invention. In some embodiments, the memory system 100A can be implemented by a 3D NAND memory in-memory search system. As shown in FIG. 1A, the memory system 100A includes a coding device 140, memory arrays 150, 159, page buffers 130, 135, and a combined sorting device 191. The coding device 140 can include a data encoder 160 and a search encoder 170. The memory array 150 can include multiple 2D memory arrays 199.

In some embodiments, the data encoder 160 is used to receive the data signal 110 and generate the encoded data signal 111. The search encoder 170 is used to receive the search signal 120 and generate the string select line (SSL) signal 171 and the word line (WL) signal 172. The memory array 150 is used to receive the encoded data signal 111, the string select line signal 171 and the word line signal 172 and generate the bit line (BL) signal 180. The page buffer 130 is used to receive the bit line signal 180 and output it to the combined sorting device 191. The combined sorting device 191 is used to process the output of the bit line signal 180 to generate the search result 190.

In some embodiments, the memory system 100A may be implemented in a single integrated circuit die, multiple integrated circuits, or as a component of a system-on-a-chip (SOC). As a specific example, the memory system 100A is implemented in a single integrated circuit die and is capable of performing search and combined logic operations in the single integrated circuit die.

FIG. 1B is a schematic diagram of a memory device 100B according to some embodiments of the present invention. Referring to FIG. 1A and FIG. 1B , the memory device 100B may be an embodiment of a memory array 150 .

In some embodiments, the memory device 100B includes a plurality of memory elements. As shown in FIG. 1B , the plurality of memory elements in the memory device 100B may be arranged into M layers LY1 to LYM and 512 blocks BK1 to BK512. Where M is a positive integer. In various embodiments, 512 may also be replaced by other positive integers.

In some embodiments, the memory device 100B can be implemented by a three-dimensional (3D) memory architecture. For example, the layers LY1 to LYM are arranged in sequence in the Z direction, and each of the layers LY1 to LYM extends on the X-Y plane. The blocks BL1 to BL512 are arranged in sequence in the Y direction, and each of the blocks BL1 to BL512 extends on the X-Z plane. However, the present disclosure is not limited thereto, and in different embodiments, the memory device 100B can also be implemented by a two-dimensional (2D) memory architecture. In some embodiments, the X direction, the Y direction, and the Z direction are perpendicular to each other.

As shown in Figure 1B, layer LY1 is used to receive word line signals WL1_1~WL512_1. Layer LY2 is used to receive word line signals WL1_2~WL512_2, and so on. Layer LYM-1 is used to receive word line signals WL1_M-1~WL512_M-1. Layer LYM is used to receive word line signals WL1_M~WL512_M.

As shown in FIG. 1B , blocks BK1 to BK512 are used to receive string selection line signals SSL1 to SSL512, respectively. In some embodiments, the memory device 100B is used to store multiple data bits, and perform operations on the stored data bits according to the word line signals WL1_1 to WL512_M and the string selection line signals SSL1 to SSL512, such as performing search operations and/or comparison operations.

FIG. 2A is a schematic diagram of a memory device 200 according to some embodiments of the present invention. As shown in FIG. 2A, the memory device 200 includes 512 memory rows CL1-CL512. The memory rows CL1-CL512 are coupled in parallel between nodes N21 and N22 and are used to output the bit line signal BL1 at the node N21. In some embodiments, the memory device 200 may include various numbers of memory rows.

In some embodiments, the memory device 200 may further include other memory rows arranged in parallel with the memory rows CL1-CL512 in the X direction and used to output other bit line signals. For simplicity, other memory rows are not shown in FIG. 2A.

In some embodiments, memory rows CL1-CL512 are used to generate current signals I1-I512 respectively, so that the memory device 200 adds the current signals I1-I512 at the node N21 to generate the bit line signal BL1. The current signals I1-I512 flow through the memory rows CL1-CL512 respectively.

As shown in FIG. 2A, memory row CL1 includes switch elements TS1, FC1_1~FC1_M, TG1 and TC1 sequentially coupled in series between node N21 and node N22, where M is a positive integer. Specifically, the first end of switch element TS1 is coupled to node N21, and the second end of switch element TS1 is coupled to the first end of switch element FC1_1. The second end of switch element FC1_1 is coupled to the first end of switch element FC1_2, and so on. The second end of switch element FC1_M-1 is coupled to the first end of switch element FC1_M. The second end of switch element FC1_M is coupled to the first end of switch element TG1. The second end of switch element TG1 is coupled to the first end of switch element TC1. The second end of switch element TC1 is coupled to node N22.

In some embodiments, the switch element TS1 is used to output the current signal I1 at the node N21. The switch element TC1 is used to receive the reference voltage signal VSS at the node N22. The control end of the switch element TS1 is used to receive the string selection line signal SSL1. The control ends of the switch elements FC1_1~FC1_M are used to receive the word line signals WL1_1~WL1_M respectively. The control end of the switch element TG1 is used to receive the ground selection line signal GSL. The control end of the switch element TC1 is used to control the selection line signal CSL.

As shown in FIG. 2A, memory row CL2 includes switch elements TS2, FC2_1~FC2_M, TG2 and TC2 that are sequentially coupled in series between node N21 and node N22. Specifically, the first end of switch element TS2 is coupled to node N21, and the second end of switch element TS2 is coupled to the first end of switch element FC2_1. The second end of switch element FC2_1 is coupled to the first end of switch element FC2_2, and so on. The second end of switch element FC2_M-1 is coupled to the first end of switch element FC2_M. The second end of switch element FC2_M is coupled to the first end of switch element TG2. The second end of switch element TG2 is coupled to the first end of switch element TC2. The second end of switch element TC2 is coupled to node N22.

In some embodiments, the switch element TS2 is used to output the current signal I2 at the node N21. The switch element TC2 is used to receive the reference voltage signal VSS at the node N22. The control end of the switch element TS2 is used to receive the string selection line signal SSL2. The control ends of the switch elements FC2_1~FC2_M are used to receive the word line signals WL2_1~WL2_M respectively. The control end of the switch element TG2 is used to receive the ground selection line signal GSL. The control end of the switch element TC2 is used to control the selection line signal CSL. In some embodiments, the ground selection line signal GSL is a general term for the ground selection line signals GSL1~GSL512, and the control selection line signal CSL is a general term for the control selection line signals CSL1~CSL512.

As shown in FIG. 2A, memory row CL511 includes switch elements TS511, FC511_1~FC511_M, TG511 and TC511 sequentially coupled in series between node N21 and node N22. Specifically, the first end of switch element TS511 is coupled to node N21, and the second end of switch element TS511 is coupled to the first end of switch element FC511_1. The second end of switch element FC511_1 is coupled to the first end of switch element FC511_2, and so on. The second end of switch element FC511_M-1 is coupled to the first end of switch element FC511_M. The second end of switch element FC511_M is coupled to the first end of switch element TG511. The second end of switch element TG511 is coupled to the first end of switch element TC511. The second end of switch element TC511 is coupled to node N22.

In some embodiments, the switch element TS511 is used to output the current signal I511 at the node N21. The switch element TC511 is used to receive the reference voltage signal VSS at the node N22. The control end of the switch element TS511 is used to receive the string selection line signal SSL511. The control ends of the switch elements FC511_1~FC511_M are used to receive the word line signals WL511_1~WL511_M respectively. The control end of the switch element TG511 is used to receive the ground selection line signal GSL. The control end of the switch element TC511 is used to control the selection line signal CSL.

As shown in FIG. 2A, memory row CL512 includes switch elements TS512, FC512_1~FC512_M, TG512 and TC512 that are sequentially coupled in series between node N21 and node N22. Specifically, the first end of switch element TS512 is coupled to node N21, and the second end of switch element TS512 is coupled to the first end of switch element FC512_1. The second end of switch element FC512_1 is coupled to the first end of switch element FC512_2, and so on. The second end of switch element FC512_M-1 is coupled to the first end of switch element FC512_M. The second end of switch element FC512_M is coupled to the first end of switch element TG512. The second end of switch element TG512 is coupled to the first end of switch element TC512. The second end of switch element TC512 is coupled to node N22.

In some embodiments, the switch element TS512 is used to output the current signal I512 at the node N21. The switch element TC512 is used to receive the reference voltage signal VSS at the node N22. The control end of the switch element TS512 is used to receive the string selection line signal SSL512. The control ends of the switch elements FC512_1~FC512_M are used to receive the word line signals WL512_1~WL512_M respectively. The control end of the switch element TG512 is used to receive the ground selection line signal GSL. The control end of the switch element TC512 is used to control the selection line signal CSL.

In some embodiments, the switch elements TS1~TS512, TG1~TG512 and TC1~TC512 can be implemented by a charge trap free element (such as a transistor) or a charge trap layer (such as a cache cell). The switch elements FC1_1~FC512_M can be implemented by a cache cell.

Referring to FIG. 1B and FIG. 2A, the memory device 200 may be an embodiment of the memory device 100B. For example, the memory rows CL1 to CL512 may be included in blocks BK1 to BK512, respectively. The switch elements FC1_1 to FC512_1 may be included in layer LY1. The switch elements FC1_2 to FC512_2 may be included in layer LY2, and so on. The switch elements FC1_M-1 to FC512_M-1 may be included in layer LYM-1. The switch elements FC1_M to FC512_M may be included in layer LYM.

In some embodiments, two switch elements coupled in series among the switch elements FC1_1~FC512_M can constitute a memory cell for storing data bits.

For example, switch elements FC1_1 and FC1_2 are used to form a memory cell MC1_1 for storing data bit BT1. Switch elements FC2_1 and FC2_2 are used to form a memory cell MC2_1 for storing data bit BT2. Switch elements FC511_1 and FC511_2 are used to form a memory cell MC511_1 for storing data bit BT511. Switch elements FC512_1 and FC512_2 are used to form a memory cell MC512_1 for storing data bit BT512. Other switch elements among switch elements FC1_1 to FC512_M may also form other memory cells for storing other data bits. However, for the sake of brevity, the details of other memory units will not be repeated here.

In some embodiments, the memory device 200 can perform a write operation and a search operation in sequence. During the write operation, a data signal is applied to the memory cell to change the critical voltage level of the memory cell. For example, when the data bit BT1 has a logical value of 0, the switch elements FC1_1 and FC1_2 have critical voltage levels VTH and VTL, respectively. When the data bit BT1 has a logical value of 1, the switch elements FC1_1 and FC1_2 have critical voltage levels VTL and VTH, respectively. In some embodiments, the critical voltage level VTL is less than the critical voltage level VTH.

Similarly, when the data bit BT2 has a logic value of 0, the switch elements FC2_1 and FC2_2 have critical voltage levels VTH and VTL, respectively. When the data bit BT2 has a logic value of 1, the switch elements FC2_1 and FC2_2 have critical voltage levels VTL and VTH, respectively, and so on. When the data bit BT511 has a logic value of 0, the switch elements FC511_1 and FC511_2 have critical voltage levels VTH and VTL, respectively. When the data bit BT511 has a logic value of 1, the switch elements FC511_1 and FC511_2 have critical voltage levels VTL and VTH, respectively. When the data bit BT512 has a logic value of 0, the switch elements FC512_1 and FC512_2 have critical voltage levels VTH and VTL, respectively. When the data bit BT512 has a logic value of 1, the switch elements FC512_1 and FC512_2 have critical voltage levels VTL and VTH, respectively.

In some embodiments, word line signals may carry search bits. For example, word line signals WL1_1 and WL1_2 may carry search bit SB1 together. Word line signals WL2_1 and WL2_2 may carry search bit SB2 together. Word line signals WL511_1 and WL511_2 may carry search bit SB511 together. Word line signals WL512_1 and WL512_2 may carry search bit SB512 together.

In some embodiments, the logic value of the search bit corresponds to the voltage level of the word line signal. For example, when the search bit SB1 has a logic value of 0, the word line signals WL1_1 and WL1_2 have voltage levels VSH and VSL, respectively. When the search bit SB1 has a logic value of 1, the word line signals WL1_1 and WL1_2 have voltage levels VSL and VSH, respectively. In some embodiments, the voltage level VSH is greater than the voltage level VSL.

Similarly, when the search bit SB2 has a logic value of 0, the word line signals WL2_1 and WL2_2 have voltage levels VSH and VSL, respectively. When the search bit SB2 has a logic value of 1, the word line signals WL2_1 and WL2_2 have voltage levels VSL and VSH, respectively, and so on. When the search bit SB511 has a logic value of 0, the word line signals WL511_1 and WL511_2 have voltage levels VSH and VSL, respectively. When the search bit SB511 has a logic value of 1, the word line signals WL511_1 and WL511_2 have voltage levels VSL and VSH, respectively. When the search bit SB512 has a logic value of 0, the word line signals WL512_1 and WL512_2 have voltage levels VSH and VSL, respectively. When the search bit SB512 has a logic value of 1, the word line signals WL512_1 and WL512_2 have voltage levels VSL and VSH, respectively.

During the search operation, the memory cell receives the word line signal to compare the search bit and the data bit, and determines the current level of the corresponding current signal according to the comparison result. For example, when each of the data bit BT1 and the search bit SB1 has a logical value of 0, the switch elements FC1_1 and FC1_2 have critical voltage levels VTH and VTL respectively and the word line signals WL1_1 and WL1_2 have voltage levels VSH and VSL respectively, so that the current signal I1 has a current level ILH.

Similarly, when each of the data bit BT1 and the search bit SB1 has a logic value of 1, the switch elements FC1_1 and FC1_2 have critical voltage levels VTL and VTH, respectively, and the word line signals WL1_1 and WL1_2 have voltage levels VSL and VSH, respectively, so that the current signal I1 has a current level ILH.

On the other hand, when the data bit BT1 and the search bit SB1 have logic values 0 and 1, respectively, the switch elements FC1_1 and FC1_2 have critical voltage levels VTH and VTL, respectively, and the word line signals WL1_1 and WL1_2 have voltage levels VSL and VSH, respectively, so that the current signal I1 has a current level ILL.

Similarly, when the data bit BT1 and the search bit SB1 have logic values 1 and 0, respectively, the switch elements FC1_1 and FC1_2 have critical voltage levels VTL and VTH, respectively, and the word line signals WL1_1 and WL1_2 have voltage levels VSH and VSL, respectively, so that the current signal I1 has a current level ILL.

In summary, when the logical values of the data bit BT1 and the search bit SB1 are the same, the current signal I1 has a current level ILH. When the logical values of the data bit BT1 and the search bit SB1 are different, the current signal I1 has a current level ILL.

Similarly, when the logical values of the data bit BT2 and the search bit SB2 are the same, the current signal I2 has a current level ILH. When the logical values of the data bit BT2 and the search bit SB2 are different, the current signal I2 has a current level ILL, and so on. When the logical values of the data bit BT511 and the search bit SB511 are the same, the current signal I511 has a current level ILH. When the logical values of the data bit BT511 and the search bit SB511 are different, the current signal I511 has a current level ILL. When the logical values of the data bit BT512 and the search bit SB512 are the same, the current signal I512 has a current level ILH. When the logical values of the data bit BT512 and the search bit SB512 are different, the current signal I512 has a current level ILL.

In some embodiments, the current level ILH is greater than the current level ILL. In some embodiments, when a switch element having a critical voltage level VTH receives a word line signal having a voltage level VSL, the switch element is considered to be closed and the current level ILL is considered to be a zero current level.

When searching the memory cells MC1_1~MC512_1, the switch elements TS1~TS512, TG1~TG512, TC1~TC512, FC1_3~FC1_M, ..., FC511_3~FC511_M and FC512_3~FC512_M are turned on. At this time, the current signals I1, I2, I511 and I512 correspond to the comparison results of the memory cells MC1_1, MC2_1, MC511_1, MC512_1 respectively, so that the current level of the bit line signal BL1 can correspond to the similarity of the data bits BT1, BT2, BT511, BT512 and the search bits SB1, SB2, SB511, SB512.

For example, when data bits BT1, BT2, BT511, BT512 have logic values 1, 0, 1, 0 respectively and search bits SB1, SB2, SB511, SB512 have logic values 1, 0, 1, 0 respectively, the similarity between data bits BT1, BT2, BT511, BT512 and search bits SB1, SB2, SB511, SB512 is 100%. Correspondingly, each of current signals I1, I2, I511 and I512 has a current level ILH, making the current level of bit line signal BL1 larger.

For another example, when data bits BT1, BT2, BT511, BT512 have logic values 1, 0, 0, 1 respectively and search bits SB1, SB2, SB511, SB512 have logic values 1, 0, 1, 0 respectively, the similarity of data bits BT1, BT2, BT511, BT512 and search bits SB1, SB2, SB511, SB512 is 50%. Correspondingly, each of current signals I1 and I2 has a current level ILH and each of current signals I511 and I512 has a current level ILL, so that the current level of bit line signal BL1 is less than the current level in the above example where the similarity is 100%.

As another example, when data bits BT1, BT2, BT511, BT512 have logic values 0, 1, 0, 1 respectively and search bits SB1, SB2, SB511, SB512 have logic values 1, 0, 1, 0 respectively, the similarity between data bits BT1, BT2, BT511, BT512 and search bits SB1, SB2, SB511, SB512 is 0%. Correspondingly, each of current signals I1, I2, I511, and I512 has a current level ILL, so that the current level of bit line signal BL1 is less than the current level in the above example where the similarity is 50%.

In the embodiment shown in FIG. 2A, during the search operation, each of the ground selection line signal GSL and the control selection line signal CSL has an enable voltage level VNS, so that each of the switch elements TG1~TG512 and TC1~TC512 is turned on. Each of the word line signals WL1_3~WL1_M, ..., WL511_3~WL 511_M and WL512_3~WL512_M has an enable voltage level VPASS, so that each of the switch elements FC1_3~FC1_M, ..., FC511_3~FC511_M and FC512_3~FC512_M is turned on. In some embodiments, the enable voltage level VNS corresponds to the normal selection voltage level, and the enable voltage level VPASS corresponds to the normal pass voltage level.

On the other hand, during the search operation, each of the string selection line signals SSL1~SSL512 has a clamp voltage level VCLAMP, so that the switch elements TS1~TS512 are turned on at the same time. In some embodiments, the clamp voltage level VCLAMP is less than the enable voltage level VNS, so that the switch elements TS1~TS512 can clamp the current signals I1~I512 in the linear region instead of the saturation region. In other words, the switch elements TS1~TS512 turned on in response to the clamp voltage level VCLAMP limit the upper limit of the current level of the current signals I1~I512.

In some practices, during the search operation, the string selection signal has a higher enabling voltage level, so that the switch element receiving the string selection signal operates in the saturation region. As a result, the variation of the current signal output by the switch element is larger, causing misunderstanding of the matching result of the search operation.

Compared to the above method, in the embodiment of the present disclosure, the switch elements TS1~TS512 are turned on in response to the lower clamping voltage level VCLAMP, so that the current signals I1~I512 are clamped in the linear region with smaller changes. In this way, the error of the matching result is reduced.

In some embodiments, the switch elements TS1~TS512 can be implemented by elements without charge wells. In the above embodiments, the enabling voltage level VNS is in the voltage range of 1~3 volts, and the clamping voltage level VCLAMP is in the voltage range of 0~1 volt. For example, the enabling voltage level VNS and the clamping voltage level VCLAMP can be 2 volts and 0.5 volts, respectively.

In some embodiments, the switch elements TS1~TS512 can also be implemented by elements having a charge trap layer and have a critical voltage level in the voltage range of 3~4 volts. In the above embodiment, the enable voltage level VNS is in the voltage range of 5~8 volts, and the clamping voltage level VCLAMP is in the voltage range of 3~5 volts. For example, the enable voltage level VNS and the clamping voltage level VCLAMP can be 7 volts and 4 volts, respectively.

In some embodiments, the search operation can be performed on different memory cell layers in sequence. For example, after performing a search operation on the first memory cell layer including switch elements FC1_1~FC512_1 and FC1_2~FC512_2, a search operation can be performed on the second memory cell layer including switch elements FC1_3~FC512_3 and FC1_4~FC512_4, and so on. After performing a search operation on the second memory cell layer, a search operation can be performed on subsequent multiple memory cell layers in sequence.

Specifically, when performing a search operation on the second memory cell layer, the word line signals WL1_3~WL512_3 and WL1_4~WL512_4 carry the corresponding search bits and have the corresponding voltage levels. At the same time, the word line signals WL1_1~WL512_1 and WL1_2~WL512_2 have the enable voltage level VPASS, so that the switch elements FC1_1~FC512_1 and FC1_2~FC512_2 are turned on. In subsequent search operations, the word line signals performing the search operation carry the corresponding search bits and have the corresponding voltage levels, and the other word line signals have the enable voltage level VPASS, so that the corresponding switch elements are turned on.

FIG. 2B is a timing diagram 201 of the operation of the memory device 200 shown in FIG. 2A according to some embodiments of the present invention. As shown in FIG. 2B, the timing diagram 201 includes periods P21 and P22 arranged in sequence.

In some embodiments, the memory device 200 can perform a write operation, such as a program operation or an erase operation, during period P21. Correspondingly, during period P21, the string selection line signals SSL1~SSL512 have an enable voltage level VNS to perform a write operation.

In some embodiments, the memory device 200 can perform a read operation, such as the above-mentioned search operation, during period P22. Correspondingly, during period P22, the string selection line signals SSL1~SSL512 have a clamping voltage level VCLAMP, so that the current signals I1~I512 can be clamped in the linear region.

In some embodiments, when the memory device 200 does not perform a write operation or a read operation, the string selection line signals SSL1~SSL512 have a disable voltage level VL, so that the switch elements TS1~TS512 are closed. In some embodiments, the disable voltage level VL is less than the clamping voltage level VCLAMP. In some embodiments, the disable voltage level VL is a ground voltage level.

FIG. 3A is a schematic diagram of a memory device 300 according to some embodiments of the present invention. Referring to FIG. 3A and FIG. 2A, the memory device 300 is a variation of the memory device 200. The components of the memory device 300 are numbered in the same manner as the memory device 300. For the sake of brevity, the discussion will focus on the parts of the memory device 300 that are different from the memory device 200 rather than the similarities.

Compared to the memory device 200, when the memory device 300 performs a search operation, the ground selection line signal GSL has a clamping voltage level VCLAMP, and each of the string selection line signals SSL1~SSL512 has an enabling voltage level VNS.

In the embodiment shown in FIG. 3A , each of the switch elements TS1 to TS512 is turned on in response to the enable voltage level VNS, and the switch elements TG1 to TG512 are turned on simultaneously in response to the clamping voltage level VCLAMP. At this time, the switch elements TG1 to TG512 limit the upper limit of the current level of the current signal I1 to I512, so that the memory device 300 can clamp the current signal I1 to I512 in the linear region instead of the saturation region.

In some practices, during the search operation, the ground selection signal has a higher enabling voltage level, so that the switch element receiving the ground selection signal operates in the saturation region. As a result, the variation of the current signal output by the switch element is larger, causing misunderstanding of the matching result of the search operation.

Compared to the above method, in the embodiment of the present disclosure, the switch elements TG1~TG512 are turned on in response to the lower clamping voltage level VCLAMP, so that the current signals I1~I512 are clamped in the linear region with smaller changes. In this way, the error of the matching result is reduced.

In some embodiments, the switch elements TG1~TG512 can be implemented by elements without charge wells. In the above embodiments, the enabling voltage level VNS is in the voltage range of 1~3 volts, and the clamping voltage level VCLAMP is in the voltage range of 0~1 volt. For example, the enabling voltage level VNS and the clamping voltage level VCLAMP can be 2 volts and 0.5 volts, respectively.

In some embodiments, the switch elements TG1~TG512 can also be implemented by elements having a charge trap layer and have a critical voltage level in the voltage range of 3~4 volts. In the above embodiment, the enabling voltage level VNS is in the voltage range of 5~8 volts, and the clamping voltage level VCLAMP is in the voltage range of 3~5 volts. For example, the enabling voltage level VNS and the clamping voltage level VCLAMP can be 7 volts and 4 volts, respectively.

FIG. 3B is a timing diagram 301 of the operation of the memory device 300 shown in FIG. 3A according to some embodiments of the present invention. As shown in FIG. 3B, the timing diagram 301 includes periods P31 and P32 arranged in sequence.

In some embodiments, the memory device 300 can perform a write operation, such as a programming operation or an erase operation, during period P31. Correspondingly, during period P31, the ground selection line signal GSL has an enable voltage level VNS to write the data bit into the memory cell.

In some embodiments, the memory device 300 can perform a read operation during period P32, such as the above-mentioned search operation. Correspondingly, during period P32, the ground selection line signal GSL has a clamping voltage level VCLAMP, so that the memory device 300 can clamp the current signals I1~I512 in the linear region.

In some embodiments, when the memory device 300 is not performing a write operation or a read operation, the ground selection line signal GSL has a disable voltage level VL, so that the switch elements TG1~TG512 are turned off.

FIG. 4A is a schematic diagram of a memory device 400 according to some embodiments of the present invention. Referring to FIG. 4A and FIG. 2A, the memory device 400 is a variation of the memory device 200. The components of the memory device 400 are numbered in the same manner as the memory device 400. For the sake of brevity, the discussion will focus on the differences between the memory device 400 and the memory device 200 rather than the similarities.

Compared to the memory device 200, when the memory device 400 performs a search operation, each of the word line signals WL1_M~WL512_M has a clamping voltage level VCLAMP, and each of the string selection line signals SSL1~SSL512 has an enabling voltage level VNS.

In the embodiment shown in FIG. 4A , each of the switch elements TS1 to TS512 is turned on in response to the enable voltage level VNS, and the switch elements FC1_M to FC512_M are turned on simultaneously in response to the clamping voltage level VCLAMP. At this time, the switch elements FC1_M to FC512_M limit the upper limit of the current level of the current signal I1 to I512, so that the memory device 400 can clamp the current signal I1 to I512 in the linear region instead of the saturation region.

In some practices, during the search operation, the word line signal has a higher enabling voltage level, so that the switch element receiving the word line signal operates in the saturation region. As a result, the variation of the current signal output by the switch element is larger, causing misunderstanding of the matching result of the search operation.

Compared to the above method, in the embodiment of the present disclosure, the switch elements FC1_M~FC512_M are turned on in response to the lower clamping voltage level VCLAMP, so that the current signals I1~I512 are clamped in the linear region with smaller changes. In this way, the error of the matching result is reduced.

In some embodiments, the switch elements FC1_M~FC512_M can be implemented by a cache unit and have a critical voltage level in the voltage range of 5~6 volts. In the above embodiment, the enable voltage level VPASS is in the voltage range of 7~8 volts, and the clamp voltage level VCLAMP is in the voltage range of 5~7 volts. For example, the enable voltage level VPASS and the clamp voltage level VCLAMP can be 7 volts and 6 volts, respectively.

In various embodiments, the memory device 400 may also be clamped by a switch element other than the switch elements FC1_M~FC512_M. For example, in some variations, the memory device 400 may also be clamped by the switch elements FC1_M-1~FC512_M-1.

In the above variation, each of the word line signals WL1_M~WL512_M has an enabling voltage level VPASS, which turns on the switch elements FC1_M~FC512_M. Each of the word line signals WL1_M-1~WL512_M-1 has a clamping voltage level VCLAMP, which allows the switch elements FC1_M-1~FC512_M-1 to clamp the current signals I1~I512 in the linear region.

FIG. 4B is a timing diagram 401 corresponding to the operation of the memory device 400 shown in FIG. 4A according to some embodiments of the present invention. As shown in FIG. 4B, the timing diagram 401 includes periods P41 and P42 arranged in sequence.

In some embodiments, the memory device 400 can perform a write operation, such as a programming operation or an erase operation, during period P41. Correspondingly, during period P41, the word line signals WL1_M~WL512_M have an enable voltage level VPASS to write data bits into the memory cell.

In some embodiments, the memory device 400 can perform a read operation, such as the above-mentioned search operation, during period P42. Correspondingly, during period P42, the word line signals WL1_M~WL512_M have a clamping voltage level VCLAMP, so that the current signals I1~I512 can be clamped in the linear region.

In some embodiments, when the memory device 400 is not performing a write operation or a read operation, the word line signals WL1_M~WL512_M have a disable voltage level VL, so that the switch elements FC1_M~FC512_M are turned off.

FIG. 5 is a schematic diagram of a memory device 500 according to some embodiments of the present invention. Referring to FIG. 5 and FIG. 2A, the memory device 500 is a variation of the memory device 200. The components of the memory device 500 are numbered in the same manner as the memory device 500. For the sake of brevity, the discussion will focus on the differences between the memory device 500 and the memory device 200 rather than the similarities.

Compared to the memory device 200, in the memory device 500, a memory cell is composed of two switching elements coupled in parallel. For example, the memory cell MC1_1 can be composed of switching elements FC1_1 and FC2_1 coupled in parallel to the nodes N21 and N22. The memory cell MC256_1 can be composed of switching elements FC511_1 and FC512_1 coupled in parallel to the nodes N21 and N22. In some embodiments, the memory cells MC1_1 and MC256_1 are used to store data bits BT1 and BT256, respectively.

In some embodiments, the memory device 500 can perform a write operation and a search operation in sequence. During the write operation, a data signal is applied to the memory cell to change the critical voltage level of the memory cell. For example, when the data bit BT1 has a logical value of 0, the switch elements FC1_1 and FC2_1 have critical voltage levels VTH and VTL, respectively. When the data bit BT1 has a logical value of 1, the switch elements FC1_1 and FC2_1 have critical voltage levels VTL and VTH, respectively.

Similarly, when the data bit BT256 has a logic value of 0, the switch elements FC511_1 and FC512_1 have critical voltage levels VTH and VTL, respectively. When the data bit BT256 has a logic value of 1, the switch elements FC511_1 and FC512_1 have critical voltage levels VTL and VTH, respectively.

In the embodiment shown in FIG. 5 , word line signals WL1_1 and WL2_1 carry search bit SB1 together, and word line signals WL511_1 and WL512_1 carry search bit SB256 together.

In some embodiments, when the search bit SB1 has a logic value of 0, the word line signals WL1_1 and WL2_1 have voltage levels VSH and VSL, respectively. When the search bit SB1 has a logic value of 1, the word line signals WL1_1 and WL2_1 have voltage levels VSL and VSH, respectively.

Similarly, when the search bit SB256 has a logic value of 0, the word line signals WL511_1 and WL512_1 have voltage levels VSH and VSL, respectively. When the search bit SB256 has a logic value of 1, the word line signals WL511_1 and WL512_1 have voltage levels VSL and VSH, respectively.

During the search operation, the memory cell receives the word line signal to compare the search bit and the data bit, and determines the current level of the corresponding current signal according to the comparison result. For example, when each of the data bit BT1 and the search bit SB1 has a logical value of 0, each of the current signals I1 and I2 has a current level ILL. Similarly, when each of the data bit BT1 and the search bit SB1 has a logical value of 1, each of the current signals I1 and I2 has a current level ILL.

On the other hand, when the data bit BT1 and the search bit SB1 have logic values 0 and 1, respectively, the current signals I1 and I2 have current levels ILH and ILL, respectively. Similarly, when the data bit BT1 and the search bit SB1 have logic values 1 and 0, respectively, the current signals I1 and I2 have current levels ILL and ILH, respectively.

In summary, when the logical values of the data bit BT1 and the search bit SB1 are the same, each of the current signals I1 and I2 has a current level ILL. When the logical values of the data bit BT1 and the search bit SB1 are different, one of the current signals I1 and I2 has a current level ILH.

Similarly, when the logical values of the data bit BT256 and the search bit SB256 are the same, each of the current signals I511 and I512 has a current level ILL. When the logical values of the data bit BT256 and the search bit SB256 are different, one of the current signals I511 and I512 has a current level ILH.

When searching memory cells MC1_1 and MC256_1, current signals I1 and I2 correspond to the comparison results of memory cell MC1_1, and current signals I511 and I512 correspond to the comparison results of memory cell MC256_1, so that the current level of bit line signal BL1 can correspond to the similarity of data bits BT1, BT256 and search bits SB1, SB256.

For example, when data bits BT1 and BT256 have logic values 1 and 0 respectively and search bits SB1 and SB256 have logic values 1 and 0 respectively, the similarity between data bits BT1 and BT256 and search bits SB1 and SB256 is 100%. Correspondingly, each of current signals I1, I2, I511 and I512 has a current level ILL, making the current level of bit line signal BL1 smaller.

For another example, when data bits BT1 and BT256 have logic values 1 and 0 respectively and search bits SB1 and SB256 have logic values 0 and 0 respectively, the similarity between data bits BT1 and BT256 and search bits SB1 and SB256 is 50%. Correspondingly, current signal I2 has current level ILH and each of I1, I511 and I512 has current level ILL, so that the current level of bit line signal BL1 is greater than the current level in the above example where the similarity is 100%.

For another example, when data bits BT1 and BT256 have logic values 1 and 0 respectively and search bits SB1 and SB256 have logic values 0 and 1 respectively, the similarity between data bits BT1 and BT256 and search bits SB1 and SB256 is 0%. Correspondingly, each of current signals I2 and I511 has a current level ILH and each of I1 and I512 has a current level ILL, so that the current level of bit line signal BL1 is greater than the current level in the above example where the similarity is 50%.

In the embodiment shown in FIG. 5, during the search operation, each of the ground selection line signals GSL1~GSL512 and the control selection line signals CSL1~CSL512 has an enable voltage level VNS, so that each of the switch elements TG1~TG512 and TC1~TC512 is turned on. Each of the word line signals WL1_2~WL1_M, ..., WL511_2~WL511_M and WL512_2~WL512_M has an enable voltage level VPASS, so that each of the switch elements FC1_2~FC1_M, ..., FC511_2~FC511_M and FC512_2~FC512_M is turned on.

On the other hand, during the search operation, each of the string selection line signals SSL1~SSL512 has a clamping voltage level VCLAMP, so that the switch elements TS1~TS512 are turned on at the same time to clamp the current signals I1~I512 in the linear region instead of the saturation region.

Referring to FIG. 5 and FIG. 2B, the memory device 500 can be operated according to the timing diagram 201. The operation performed by the memory device 500 according to the timing diagram 201 is similar to the operation performed by the memory device 200 according to the timing diagram 201. Therefore, for the sake of brevity, some descriptions will not be repeated.

FIG. 6 is a schematic diagram of a memory device 600 according to some embodiments of the present invention. Referring to FIG. 6 and FIG. 5, the memory device 600 is a variation of the memory device 500. The components of the memory device 600 are numbered in the same manner as the memory device 500. For the sake of brevity, the discussion will focus on the differences between the memory device 600 and the memory device 500 rather than the similarities.

Compared to the memory device 500, when the memory device 600 performs a search operation, the ground selection line signal GSL has a clamping voltage level VCLAMP, and each of the string selection line signals SSL1~SSL512 has an enabling voltage level VNS.

In the embodiment shown in FIG. 6 , each of the switch elements TS1 to TS512 is turned on in response to the enable voltage level VNS, and each of the switch elements TG1 to TG512 is turned on in response to the clamping voltage level VCLAMP. At this time, the switch elements TG1 to TG512 limit the upper limit of the current level of the current signal I1 to I512, so that the memory device 600 can clamp the current signal I1 to I512 in the linear region instead of the saturation region.

Please refer to FIG. 6 and FIG. 3B, the memory device 600 can be operated according to the timing diagram 301. The operation performed by the memory device 600 according to the timing diagram 301 is similar to the operation performed by the memory device 300 according to the timing diagram 301. Therefore, for the sake of brevity, some descriptions will not be repeated.

FIG. 7 is a schematic diagram of a memory device 700 according to some embodiments of the present invention. Referring to FIG. 7 and FIG. 5, the memory device 700 is a variation of the memory device 500. The components of the memory device 700 are numbered in the same manner as the memory device 700. For the sake of brevity, the discussion will focus on the differences between the memory device 700 and the memory device 500 rather than the similarities.

Compared to the memory device 500, when the memory device 700 performs a search operation, each of the word line signals WL1_M~WL512_M has a clamping voltage level VCLAMP, and each of the string selection line signals SSL1~SSL512 has an enabling voltage level VNS.

In the embodiment shown in FIG. 7 , each of the switch elements TS1 to TS512 is turned on in response to the enable voltage level VNS, and the switch elements FC1_M to FC512_M are turned on simultaneously in response to the clamping voltage level VCLAMP. At this time, the switch elements FC1_M to FC512_M limit the upper limit of the current level of the current signal I1 to I512, so that the memory device 700 can clamp the current signal I1 to I512 in the linear region instead of the saturation region.

In various embodiments, the memory device 700 may also be clamped by switch elements other than the switch elements FC1_M~FC512_M. For example, in some variations, the memory device 400 may also be clamped by switch elements FC1_M-1~FC512_M-1.

In the above example, each of the word line signals WL1_M~WL512_M has an enable voltage level VPASS, which turns on the switch elements FC1_M~FC512_M. Each of the word line signals WL1_M-1~WL512_M-1 has an enable voltage level VCLAMP, which allows the switch elements FC1_M-1~FC512_M-1 to clamp the current signals I1~I512 in the linear region.

Referring to FIG. 7 and FIG. 4B, the memory device 700 can be operated according to the timing diagram 401. The operation performed by the memory device 700 according to the timing diagram 401 is similar to the operation performed by the memory device 700 according to the timing diagram 401. Therefore, for the sake of brevity, some descriptions will not be repeated.

FIG. 8 is a flow chart of an operation method 800 of a memory device according to some embodiments of the present invention. As shown in FIG. 8 , the operation method 800 may include operations OP81 to OP84. In some variations, the operation method 800 may also include a portion of operations OP81 to OP84.

In operation OP81, the memory device performs a write operation, such as a programming operation or an erase operation. At this time, the string selection line signals SSL1~SSL512 or the ground selection line signal GSL have a normal selection voltage, such as an enable voltage level VNS.

In operation OP82, the memory device performs a read operation, such as a search operation. At this time, the string selection line signal SSL1~SSL512 or the ground selection line signal GSL has a clamping voltage, such as a clamping voltage level VCLAMP.

Referring to FIG. 2A, FIG. 3A, FIG. 5, FIG. 6, and FIG. 8, operations OP81~OP82 can be performed by memory devices 200, 300, 500, and 600. Referring to FIG. 2B and FIG. 3B, operation OP81 can correspond to periods P21 and P31, and operation OP82 can correspond to periods P22 and P32.

In operation OP83, the memory device performs a write operation, such as a programming operation or an erase operation. At this time, the clamp cache unit, such as the switch elements FC1_M~FC512_M shown in FIG. 4A and FIG. 7, has a normal pass voltage, such as an enable voltage level VPASS.

In operation OP84, the memory device performs a read operation, such as a search operation. At this time, the clamp cache unit, such as the switch elements FC1_M~FC512_M shown in FIG. 4A and FIG. 7, has a clamp voltage, such as a clamp voltage level VCLAMP.

Please refer to Figures 4A, 7 and 8, operations OP83~OP84 can be performed by memory devices 400 and 700. Please refer to Figure 4B, operation OP83 can correspond to period P41, and operation OP84 can correspond to period P42.

Although the contents of this disclosure have been disclosed as above by way of embodiments, they are not intended to limit the contents of this disclosure. Any person with ordinary knowledge in the relevant technical field may make some changes and modifications within the spirit and scope of the contents of this disclosure. Therefore, the scope of protection of the contents of this disclosure shall be subject to the scope of the patent application attached hereto.

200: Memory device

SSL1, SSL2, SSL511, SSL512: string selection line signal

X, Y, Z: direction

CL1, CL2, CL511, CL512: memory row

N21, N22: nodes

BL1: bit line signal

I1, I2, I511, I512: current signal

TS1, TS2, TS511, TS512, FC1_1, FC1_M, FC512_M, TG1, TG2, TG511, TG512, TC1, TC2, TC511, TC512: switch components

GSL: Ground select line signal

WL1_1, WL2_1, WL511_1, WL512_1, WL1_2, WL2_2, WL511_2, WL512_2: word line signal

CSL: Control Select Line Signal

MC1_1, MC2_1, MC511_1, MC512_1: memory unit

VPASS: Enable voltage level

VCLAMP: clamping voltage level

VSS: reference voltage signal

Claims (8)

A memory device comprises: a first memory cell for storing a first data bit and for performing a search operation on the first data bit through a first search bit to generate a first current signal; a first switch element coupled in series with the first memory cell and for conducting in response to a clamping voltage level during the search operation to clamp the first current signal; and a second switch element coupled in series with the first memory cell and for conducting in response to a first enabling voltage level during the search operation, wherein the first enabling voltage level is greater than the clamping voltage level, before the search operation, the first memory cell is further used to perform a write operation to write the first data bit, and During the write operation, the first switch element is turned on in response to the first enabling voltage level. The memory device as described in claim 1 further comprises: a second memory unit for storing a second data bit and for performing the search operation on the second data bit by a second search bit to generate a second current signal; and a third switch element, coupled in series with the second memory unit between a first node and a second node, and for conducting in response to the clamping voltage level during the search operation to clamp the second current signal, wherein the first memory unit and the first switch element are coupled in series between the first node and the second node. The memory device as described in claim 1 further comprises: a third switch element for conducting in response to a second enabling voltage level during the search operation; and a fourth switch element for conducting in response to the second enabling voltage level during the search operation, wherein the first memory unit, the first switch element and the second switch element are coupled in series between the third switch element and the fourth switch element, and the second enabling voltage level is different from the first enabling voltage level. The memory device as described in claim 1 further comprises: A third switch element, coupled in series with the first memory unit between the first switch element and the second switch element, and configured to be turned on in response to a second enable voltage level during the search operation, wherein the second enable voltage level is different from the first enable voltage level. The memory device as described in claim 1 further comprises: a third switch element for conducting in response to the clamping voltage level during the search operation to clamp a second current signal, wherein the first memory unit is further used to perform the search operation on the first data bit and the first search bit to generate the second current signal, the first memory unit comprises a fourth switch element and a fifth switch element coupled in parallel to each other, the fourth switch element is coupled in series with the first switch element, and the fifth switch element is coupled in series with the third switch element. A method for operating a memory device includes: Storing a first data bit by a first memory cell; Comparing the first data bit with a first search bit to generate a first current signal; Clamping the first current signal by a first switch element according to a clamping voltage level; and Turning on a second switch element according to a first enabling voltage level, wherein the first current signal flows through the second switch element, the first enabling voltage level is greater than the clamping voltage level, and before comparing the first data bit with the first search bit, the first switch element is turned on according to the first enabling voltage level. The operating method as described in claim 6 further includes: Comparing the first data bit and the first search bit to generate a second current signal; and Clamping the second current signal according to the clamping voltage level by a third switching element, wherein the third switching element is coupled in parallel with the first switching element. The operating method as described in claim 6 further includes: Storing a second data bit by a second memory cell; Comparing the second data bit with a first search bit to generate a second current signal; and Clamping the second current signal according to the clamping voltage level by a third switching element, wherein the third switching element is coupled in parallel with the first switching element.

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