TWI876889B - Micro-electro-mechanical system package and fabrication method thereof - Google Patents

Abstract

A MEMS package includes a wafer with an interconnect layer thereon. A first device layer including a first MEMS device with a first thickness is disposed on the wafer and bonded to the interconnect layer. A second device layer including a second MEMS device with a second thickness thinner than the first thickness is disposed on the wafer and bonded to the interconnect layer. A raised electrode is disposed above the interconnect layer and directly below the second MEMS device. A first cap substrate with a first cavity is bonded to the first device layer, where the first MEMS device corresponds to the first cavity. A second cap substrate with a second cavity is bonded to the second device layer, where the second MEMS device corresponds to the second cavity.

Description

Micro-electromechanical package and manufacturing method thereof

The present disclosure relates to a micro-electromechanical system (MEMS) package, and more particularly to a MEMS package including different MEMS components having different component layer thicknesses and different electrode gaps and a method for manufacturing the same.

Microelectromechanical (MEMS) devices are miniature components that integrate mechanical and electrical components to sense physical quantities and/or interact with the surrounding environment. MEMS devices such as accelerometers, gyroscopes, pressure sensors and microphones have been widely used in many modern electronic products. For example, inertial measurement units (IMUs) composed of accelerometers and/or gyroscopes are commonly found in tablets, cars or smartphones. For some applications, it is necessary to integrate various MEMS components into a MEMS package. These MEMS components may require different component layer thicknesses to meet the sensitivity and performance requirements. However, in current MEMS packaging, for multiple MEMS components that require different component layer thicknesses, different component wafers are usually used to manufacture these MEMS components separately, and then these MEMS components are packaged together. Therefore, the entire manufacturing process of current MEMS packaging is relatively complicated and the manufacturing cost is also relatively high.

In view of this, the present disclosure provides a micro-electromechanical (MEMS) package and a manufacturing method thereof to overcome the shortcomings of the current MEMS package. The MEMS package disclosed herein includes different MEMS components, which have different component layer thicknesses and different electrode gaps to meet the sensitivity and performance requirements of various MEMS components. In addition, these MEMS components are manufactured simultaneously using the same component wafer and packaged simultaneously on the same wafer, which has an interconnect layer and protruding electrodes. Therefore, compared with the current MEMS package, the entire manufacturing process of the MEMS package disclosed herein is simplified, and the cost of the MEMS package is also reduced.

According to an embodiment of the present disclosure, a micro-electromechanical package is provided, including a wafer, a first component layer, a second component layer, a protruding electrode, a first cover plate, and a second cover plate. The wafer has an interconnection layer disposed thereon, the first component layer includes a first MEMS component having a first thickness, the first component layer is disposed on the wafer and bonded to the interconnection layer. The second component layer includes a second MEMS component having a second thickness thinner than the first thickness, the second component layer is laterally separated from the first component layer, the second component layer is also disposed on the wafer and bonded to the interconnection layer. The protruding electrode is disposed on the interconnection layer and is located directly below the second MEMS component. The first cover plate has a first cavity and is bonded to the first component layer, wherein the first MEMS component corresponds to the first cavity. The second cover plate has a second cavity and is bonded to the second component layer. The second cover plate is laterally spaced apart from the first cover plate, wherein the second MEMS component corresponds to the second cavity.

According to an embodiment of the present disclosure, a method for manufacturing a micro-electromechanical system package is provided, comprising the following steps: providing a cover wafer, and forming a first cavity and a second cavity in the cover wafer; providing a component wafer, and bonding the component wafer to the cover wafer, wherein the component wafer covers the first cavity and the second cavity; after the component wafer is bonded to the cover wafer and thinned, etching and thinning the component wafer to form a recessed portion corresponding to the second cavity; patterning the component wafer to form a first MEMS component and a second MEMS component, wherein the first MEMS component has a first thickness and corresponds to A first cavity, a second MEMS element having a second thickness and corresponding to the second cavity, and the second thickness is thinner than the first thickness; providing a wafer on which an interconnection layer is formed; forming protruding electrodes on the interconnection layer; bonding the element wafer to the interconnection layer on the wafer, wherein the protruding electrodes correspond to the second MEMS element; and removing a portion of the cover wafer and a portion of the element wafer located at the cutting path to form a first cover plate having a first cavity, a second cover plate having a second cavity, a first element layer having a first MEMS element, and a second element layer having a second MEMS element.

In order to make the features of the present disclosure clear and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and layouts. The purpose of providing these embodiments is only for illustration and not for any limitation. For example, the description below of "a first feature is formed on or above a second feature" may mean "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, and are not used to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in the present disclosure, such as "below", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the MEMS package during use and operation. As the orientation of the MEMS package is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or blocks, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they themselves do not mean or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupled", "coupled", and "electrically connected" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

Although the invention disclosed herein is described below by means of specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention disclosed herein, certain details will be omitted, and the omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a microelectromechanical (MEMS) package and a method for manufacturing the same, wherein the MEMS package includes different MEMS components having different component layer thicknesses and different electrode gaps. In a MEMS package, the component layer thickness of a MEMS component that generally requires a low vacuum or atmospheric pressure is relatively thick, while the component layer thickness of a MEMS component that requires a high vacuum is relatively thin. According to some embodiments of the present disclosure, these MEMS components can be manufactured simultaneously by using the same component wafer, and can be packaged simultaneously on the same wafer having an interconnect layer formed thereon. A protruding electrode is disposed above the interconnect layer, and the protruding electrode corresponds to the MEMS component having a relatively thin component layer thickness. In addition, the electrode gap of a MEMS component with a thinner component layer is smaller than the electrode gap of a MEMS component with a thicker component layer. According to some embodiments of the present disclosure, the entire manufacturing process of the MEMS package is simplified, and the manufacturing cost and time of the MEMS package are also reduced. In addition, the MEMS package disclosed in the present disclosure can meet the sensitivity and performance requirements of various MEMS components.

FIG. 1 is a cross-sectional schematic diagram of a microelectromechanical (MEMS) package 100 according to an embodiment of the present disclosure. The MEMS package 100 may include various MEMS components having different component layer thicknesses and different electrode gaps to meet different requirements for sensitivity and performance of each MEMS component. These MEMS components are laterally spaced from each other, for example, in the X-axis direction, and are packaged on the same wafer 130. The wafer 130 may include a plurality of complementary metal oxide semiconductor (CMOS) transistors or other components formed therein, and an interconnect layer 132 is disposed on the wafer 130. In one embodiment, the MEMS package 100 may include a first MEMS region 100A and a second MEMS region 100B separated by a scribe line SL, wherein a first MEMS element 121 requiring a relatively low vacuum or atmospheric pressure is located in the first MEMS region 100A, and a second MEMS element 122 requiring a relatively high vacuum is located in the second MEMS region 100B. The first MEMS element 121 has a first thickness T1 in the Z-axis direction and is formed in the first element layer 120A, and the second MEMS element 122 has a second thickness T2 thinner than the first thickness T1 and is formed in the second element layer 120B. The first MEMS element 121 and the second MEMS element 122 have different element layer thicknesses to meet the different requirements of these MEMS elements in terms of sensitivity and performance. In addition, the first device layer 120A and the second device layer 120B are laterally spaced apart from each other, for example, in the X-axis direction, and both the first device layer 120A and the second device layer 120B are bonded to the interconnect layer 132 on the wafer 130 .

The MEMS package 100 further includes a raised electrode 145 disposed on the interconnect layer 132 and directly below the second MEMS element 122. In addition, a dielectric layer 141 is disposed between the raised electrode 145 and the interconnect layer 132, and a via 143 passes through the dielectric layer 141 and the protective layer 138 and the top dielectric layer 136 of the interconnect layer 132 to electrically connect the raised electrode 145 to the top metal layer 133 of the interconnect layer 132. In the first MEMS region 100A, a portion 133P of the top metal layer 133 is exposed through an opening penetrating the protection layer 138 and the top dielectric layer 136 , and the portion 133P of the top metal layer 133 is located directly below the first MEMS element 121 .

A first gap G1 is formed between a portion 133P of the top metal layer 133 and the bottom surface of the first MEMS element 121 in the Z-axis direction, and a second gap G2 is formed between the protruding electrode 145 and the bottom surface of the second MEMS element 122 in the Z-axis direction. In some embodiments, an electrode (not shown) is formed in the first MEMS element 121, and another electrode (not shown) is formed in the second MEMS element 122. The electrode in the first MEMS element 121 can be electrically coupled to the interconnection layer 132 through the first element layer 120A and stand-off bumps formed at the bottom of the first element layer 120A, and the electrode in the second MEMS element 122 can also be electrically coupled to the interconnection layer 132 through the second element layer 120B and stand-off bumps formed at the bottom of the second element layer 120B. Since the entire first component layer 120A has high conductivity, the first component layer 120A can be regarded as an upper electrode interacting with a portion 133P of the top metal layer 133. At the same time, the entire second component layer 120B also has high conductivity, so the second component layer 120B can be regarded as another upper electrode interacting with the protruding electrode 145.

In addition, a portion 133P of the top metal layer 133 is a lower electrode that interacts with the upper electrode in the first MEMS element 121, so the first gap G1 can be regarded as the electrode gap of the first MEMS element 121. The protruding electrode 145 is a lower electrode that interacts with the upper electrode in the second MEMS element 122, so the second gap G2 can be regarded as the electrode gap of the second MEMS element 122. In the micro-electromechanical package 100, the second gap G2 is smaller than the first gap G1, thereby improving the sensitivity of the second MEMS element 122 with a thinner element layer thickness. In addition, the first MEMS element 121 and the second MEMS element 122 have different electrode gaps, thereby meeting the different requirements of sensitivity and performance of these MEMS elements. In some embodiments, the protruding electrode 145 may be located, for example, directly below the proof mass of the second MEMS element 122 to further improve the sensitivity and performance of the second MEMS element 122 .

Furthermore, the second gap G2 is adjustable and can be controlled by the thickness of the dielectric layer 141. When the dielectric layer 141 is thicker, the second gap G2 is smaller, and the thickness of the dielectric layer 141 depends on the difference between the first thickness T1 of the first MEMS element 121 and the second thickness T2 of the second MEMS element 122. In some embodiments, the difference between the first thickness T1 and the second thickness T2 can be greater than the thickness of the dielectric layer 141. In addition, in some embodiments, the protruding electrode 145 and the dielectric layer 141 can have the same pattern in a top view (e.g., in the XY plane).

In the micro-electromechanical package 100, the first MEMS element 121 and the second MEMS element 122 require different vacuum levels. In some embodiments, the first MEMS element 121 is, for example, an accelerometer that requires a relatively low vacuum level or atmospheric pressure, and the second MEMS element 122 is, for example, a gyroscope that requires a relatively high vacuum level, but is not limited thereto. In addition, the MEMS structures of the first MEMS element 121 and the second MEMS element 122 may be different from each other. The first MEMS element 121 and the second MEMS element 122 may each include components such as stand-off bumps, grooves, and proof mass, and the layout of these components in the first MEMS element 121 may be different from the layout in the second MEMS element. In order to make the diagram concise and easy to understand, the MEMS structures of the first MEMS element 121 and the second MEMS element 122 in FIG. 1 are simplified.

In addition, as shown in FIG. 1 , a first bonding seal ring 125A is disposed between the first device layer 120A and the wafer 130, and the first bonding seal ring 125A is bonded to the interconnect layer 132 through a bonding material 127. A second bonding seal ring 125B is disposed between the second device layer 120B and the wafer 130, and the second bonding seal ring 125B is bonded to the interconnect layer 132 through a bonding material 127. In some embodiments, the bonding material 127 is composed of metal, such as germanium (Ge), so that the first bonding sealing ring 125A and the second bonding sealing ring 125B can be bonded to the top metal layer 133 of the interconnect layer 132 by eutectic bonding. In addition, the first bonding sealing ring 125A and the first device layer 120A are connected to each other to form an integral structure, and the second bonding sealing ring 125B and the second device layer 120B are also connected to each other to form an integral structure.

Still referring to FIG. 1 , the MEMS package 100 further includes a first cover plate 110A having a first cavity 111 and a second cover plate 110B having a second cavity 112. The first cover plate 110A and the second cover plate 110B are formed from the same cover wafer and have the same composition, such as silicon. The first cover plate 110A and the second cover plate 110B are laterally spaced from each other, for example, in the X-axis direction. In addition, a bonding layer 115 is disposed between the first element layer 120A and the first cover plate 110A, and another bonding layer 115 is disposed between the second element layer 120B and the second cover plate 110B. The composition of the bonding layer 115 is, for example, silicon oxide. The first cover plate 110A can be bonded to the first element layer 120A by fusion bonding via the bonding layer 115, and the second cover plate 110B can also be bonded to the second element layer 120B by fusion bonding via another bonding layer 115. In some embodiments, the bonding layer 115 can further extend into the first cavity 111 and the second cavity 112, and the bonding layer 115 can be conformally disposed on the side walls and bottom surfaces of both the first cavity 111 and the second cavity 112.

As shown in FIG. 1 , the first cavity 111 is located directly above the first MEMS element 121 and corresponds to the first MEMS element 121, and the second cavity 112 is located directly above the second MEMS element 122 and corresponds to the second MEMS element 122. In some embodiments, the first MEMS element 121 is, for example, an accelerometer, and the second MEMS element 122 is, for example, a gyroscope, wherein the first cavity 111 has a first pressure, and the second cavity 112 has a second pressure lower than the first pressure. In addition, a conductive layer 117 may be provided on the back of the first cover plate 110A and the second cover plate 110B, and the composition of the conductive layer 117 is, for example, aluminum (Al). In addition, the conductive layer 117 may not be patterned, or may be formed by a patterned conductive layer, depending on the electrical requirements of the first MEMS element 121 and the second MEMS element 122. In addition, the first MEMS element 121 and the second MEMS element 122 may be electrically coupled to different portions of the conductive layer 117 , respectively, and the conductive layer 117 may also be electrically coupled to the interconnect layer 132 .

1 , the first element layer 120A may include a first element portion 121D and a first peripheral portion 121P adjacent to and surrounding the first element portion 121D. The second element layer 120B may include a second element portion 122D and a second peripheral portion 122P adjacent to and surrounding the second element portion 122D. In some embodiments, the first element portion 121D, the first peripheral portion 121P, and the second peripheral portion 122P all have a first thickness T1, and the second element portion 122D has a second thickness T2 that is thinner than the first thickness T1. In one embodiment, the boundary between the first peripheral portion 121P and the first element portion 121D can be vertically aligned with the inner wall of the first keying sealing ring 125A, and the boundary between the second peripheral portion 122P and the second element portion 122D can be vertically aligned with the inner wall of the second keying sealing ring 125B.

In addition, the second device layer 120B has a recessed portion 124 facing the interconnect layer 132, and the protruding electrode 145 is located in the recessed portion 124. In one embodiment, the side wall of the recessed portion 124 can be vertically aligned with the inner side wall of the second keying seal ring 125B. In other embodiments, the side wall of the recessed portion 124 can also retreat inward toward the second cavity 112 and may not be vertically aligned with the inner side wall of the second keying seal ring 125B.

In other embodiments, the micro-electromechanical package 100 may further include other MEMS elements, and the vacuum degree required by the other MEMS elements may be different from the vacuum degree required by the first MEMS element 121 and the second MEMS element 122. For example, the micro-electromechanical package 100 may further include a third MEMS area (not shown), which includes a third MEMS element. The third MEMS area may be laterally separated from the first MEMS area 100A and the second MEMS area 100B by the scribe line SL, and a third element layer (not shown) including the third MEMS element is also packaged on the same wafer 130. The third MEMS element may have an element layer thickness different from the first thickness T1 and the second thickness T2. In addition, the third MEMS element may also have an electrode gap different from the first gap G1 and the second gap G2. In one embodiment, another protruding electrode (not shown) may be disposed on the interconnect layer 132, and the other protruding electrode may be located directly below the third MEMS element. In another embodiment, another portion of the top metal layer 133 may be exposed through the opening of the interconnect layer 132, and the other portion of the top metal layer 133 may be located directly below the third MEMS element. In addition, the MEMS structure of the third MEMS element may be different from the MEMS structure of the first MEMS element 121 and the second MEMS element 122. The disclosed microelectromechanical package may be applicable to 1-axis, 2-axis, 3-axis, and 6-axis inertial measurement units (IMUs), as well as various other MEMS elements that require different element layer thicknesses and different electrode gaps.

FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8 and FIG. 9 are cross-sectional schematic diagrams of some stages of a method for manufacturing a micro-electromechanical system package according to an embodiment of the present disclosure. Referring to FIG. 2, in step S101, a cap wafer 110, such as a silicon wafer, is first provided. Then, a first cavity 111 and a second cavity 112 are formed on the front surface of the cap wafer 110 through an etching process. In addition, alignment marks 118 may be formed on the back surface of the cap wafer 110. Next, a bonding layer 115 is sequentially formed on the front, sidewalls and backside of the cap wafer 110 and in the first cavity 111 and the second cavity 112 to wrap the cap wafer 110, and the bonding layer 115 is also formed on the sidewalls and bottom surface of the first cavity 111 and the second cavity 112. The bonding layer 115 is composed of silicon oxide, for example, and can be formed by a thermal oxidation process or a deposition process.

Next, still referring to FIG. 2, in step S103, a device wafer 120, such as a silicon wafer, is provided. The edge 128 of the device wafer 120 is trimmed first, and then the device wafer 120 is bonded to the cover wafer 110 via the bonding layer 115 and by melt bonding using an annealing process, so that the device wafer 120 covers the first cavity 111 and the second cavity 112. In step S103, the device wafer 120 has a thickness T3.

Then, referring to FIG. 3 , in step S105 , the thickness of the device wafer 120 is reduced from the thickness T3 of step S103 to the thickness T4 through a back grinding (BG) process and a chemical-mechanical planarization (CMP) process. Then, still referring to FIG. 3 , in step S107 , the device wafer 120 is etched to form stand-off bumps, a first bonding seal ring 125A, and a second bonding seal ring 125B. After step S107 , the device wafer 120 has a first thickness T1 thinner than the thickness T4 of step S105 .

Thereafter, referring to FIG. 4 , in step S109 , the device wafer 120 is etched and thinned to form a recessed portion 124 corresponding to the second cavity 112. In one embodiment, as shown in FIG. 4 , the sidewall of the recessed portion 124 may be vertically aligned with the inner sidewall of the second keying seal ring 125B. In other embodiments, the sidewall of the recessed portion 124 may also be retreated inward toward the second cavity 112, and the sidewall of the recessed portion 124 may not be vertically aligned with the inner sidewall of the second keying seal ring 125B. After etching the device wafer 120 to form the recessed portion 124, a portion of the device wafer 120 directly below the recessed portion 124 has a second thickness T2 thinner than the first thickness T1, and the other portions of the device wafer 120 have the first thickness T1. The second thickness T2 of the device wafer 120 is adjustable and can be controlled by the etching process for forming the recessed portion 124 in step S109.

Next, still referring to FIG. 4 , in step S111, first, a bonding material 127, such as germanium (Ge), is formed on the first bonding sealing ring 125A and the second bonding sealing ring 125B through a deposition and patterning process. Then, a patterned mask layer 160 is formed longitudinally on the device wafer 120 and in the recessed portion 124 through a spray coating and patterning process. In one embodiment, the patterned mask layer 160 can be a photoresist layer patterned through a photolithography process, and the patterned mask layer 160 has a plurality of openings and/or slits 161, 162, and 163. 1 and 4, the opening and/or slit 161 is located in the first MEMS region 100A for forming the first MEMS element 121, the opening and/or slit 162 is located in the second MEMS region 100B for forming the second MEMS element 122, and the slit 163 is located in the dicing line SL for forming a pre-dicing line.

Then, referring to FIG. 5 , in step S113A, the device wafer 120 is patterned through the openings and/or slits 161, 162, and 163 of the patterned mask layer 160 through an etching process to simultaneously form a first MEMS element 121, a second MEMS element 122, and a pre-cut line 129. The first MEMS element 121 has a first thickness T1 and corresponds to the first cavity 111. The second MEMS element 122 has a second thickness T2 that is thinner than the first thickness T1 and corresponds to the second cavity 112. The pre-cut line 129 is located at the scribe line SL, and the device wafer 120 is divided into a first device layer 120A and a second device layer 120B by the pre-cut line 129. The first element layer 120A includes a first element portion 121D and a first peripheral portion 121P, both of which have a first thickness T1. The second element layer 120B includes a second element portion 122D having a second thickness T2 and a second peripheral portion 122P having a first thickness T1, and the second element portion 122D is located between the recessed portion 124 and the second cavity 112. Afterwards, the first element portion 121D having the first thickness T1 is patterned to form the first MEMS element 121, and the second element portion 122D having the second thickness T2 is patterned to form the second MEMS element 122. In addition, the first keying seal ring 125A is connected to the first peripheral portion 121P of the first element layer 120A and forms an integrally formed structure, and the second keying seal ring 125B is connected to the second peripheral portion 122P of the second element layer 120B and forms an integrally formed structure.

Still referring to FIG. 5 , in step S115 , a wafer 130 is first provided, on which an interconnection layer 132 is formed. The wafer 130 may be a silicon wafer including a plurality of CMOS transistors or other elements formed therein, and may be referred to as a CMOS wafer. The interconnection layer 132 includes a plurality of metal layers, a plurality of inter-metal dielectric (IMD) layers, and a plurality of vias in the IMD layer for connecting two metal layers, wherein the metal layer includes a top metal layer 133, and the IMD layer includes a top dielectric layer 136 formed on the top metal layer 133. In addition, the interconnection layer 132 further includes a passivation layer 138 deposited on the top dielectric layer 136. In one embodiment, the metal layer is composed of aluminum (Al), the IMD layer is composed of silicon oxide, and the protective layer 138 is composed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Then, a dielectric material layer 140, such as a silicon oxide layer, is deposited on the protective layer 138. The thickness d1 of the dielectric material layer 140 is adjusted according to the difference between the first thickness T1 and the second thickness T2, and the thickness d1 of the dielectric material layer 140 can be less than the difference between the first thickness T1 and the second thickness T2.

Next, referring to FIG. 6 , in step S117, a patterned mask is used to form an opening 142 in the dielectric material layer 140, the protective layer 138, and the top dielectric layer 136 through an etching process, so that a portion of the top metal layer 133 is exposed through the opening 142. Then, still referring to FIG. 6 , in step S119, the opening 142 is filled with a conductive material to form a via 143. Thereafter, a conductive material layer, such as an aluminum (Al) layer, is deposited on the dielectric material layer 140, and the conductive material layer directly contacts the dielectric material layer 140 and the via 143. Then, the conductive material layer is patterned through photolithography and etching processes to form a protruding electrode 145, which is directly in contact with the via 143 and is located above the interconnect layer 132.

Thereafter, referring to FIG. 7 , in step S121, the dielectric material layer 140 is etched using the protruding electrode 145 as a mask to form a dielectric layer 141 between the protruding electrode 145 and the interconnect layer 132. In the top view, the dielectric layer 141 may have the same pattern as the protruding electrode 145. In addition, the via 143 passes through the dielectric layer 141 and electrically connects the protruding electrode 145 to the top metal layer 133 of the interconnect layer 132.

Next, still referring to FIG. 7 , in step S123 , a plurality of openings 134 , 135A, 135B and 137 are formed in the protective layer 138 and the top dielectric layer 136 through photolithography and etching processes. Among them, the opening 134 exposes a portion 133P of the top metal layer 133 located in the first MEMS area 100A, and this portion 133P can be used as an electrode of the first MEMS element 121. The opening 135A exposes a first bond ring area of the top metal layer 133 located in the first MEMS area 100A. The opening 135B exposes a second bond ring area of the top metal layer 133 located in the second MEMS area 100B. The opening 137 exposes a bond pad area of the top metal layer 133 located in the cutting line SL.

Afterwards, referring to FIG. 8, in step S125, the structure including the device wafer 120 and the cover wafer 110 bonded together formed in step S113A of FIG. 5 is turned upside down and bonded to the wafer 130 formed in step S123 of FIG. 7. The device wafer 120 is bonded to the interconnect layer 132 on the wafer 130 under a first pressure, so that the first cavity 111 and the second cavity 112 both have the first pressure. The first bonding sealing ring 125A and the second bonding sealing ring 125B of the device wafer 120 are bonded to the top metal layer 133 of the interconnect layer 132 through the bonding material 127 by eutectic bonding. After the device wafer 120 and the wafer 130 are bonded, the protruding electrode 145 is located directly below the second MEMS device 122 and corresponds to the second MEMS device 122. In one embodiment, the protruding electrode 145 may be located directly below the mass block of the second MEMS device 122. In some embodiments, a plurality of protruding electrodes 145 are formed on the interconnect layer 132, and the protruding electrodes 145 may correspond to the mass block and other components of the second MEMS device 122, respectively.

In step S125, the cap wafer 110 has a thickness T5, and the wafer 130 has a thickness T7. Then, referring to FIG. 9, in step S127, the cap wafer 110 is thinned by back grinding or dry etching process, so that the cap wafer 110 has a thickness T6 thinner than the thickness T5 of step S125 of FIG. 8, and the bonding layer 115 on the back side of the cap wafer 110 is also removed. In addition, the wafer 130 is also thinned by back grinding or dry etching process, so that the wafer 130 has a thickness T8 thinner than the thickness T7 of step S125 of FIG. 8.

Next, still referring to FIG. 9, in step S129, in one embodiment, a metal layer, such as an aluminum layer, is deposited on the back side of the thinned cap wafer 110 to form a conductive layer 117, wherein the formation of the conductive layer 117 may not require patterning. In another embodiment, the metal layer may be patterned by photolithography and etching processes to form a patterned conductive layer 117. The conductive layer 117 may be used to ground the cap wafer 110, so the conductive layer 117 may be formed without a pattern, or the conductive layer 117 may be patterned.

Afterwards, a portion of the cover wafer 110 and a portion 120P of the element wafer 120 located on the scribe line SL and between the pre-slice lines 129 are removed through a cutting process to complete the MEMS package 100 of FIG. 1. In the MEMS package 100, the bonding pads on the interconnection layer 132 located on the scribe line SL are exposed. In some embodiments, the bonding pads of the first MEMS element 121 and the bonding pads of the second MEMS element 122 are both disposed on one side of the interconnection layer 132 and are located on the same scribe line SL. Therefore, the bonding pads of both the first MEMS element 121 and the second MEMS element 122 can be exposed through one scribe line SL. In addition, the aforementioned cutting process forms a first cover plate 110A having a first cavity 111 and a second cover plate 110B having a second cavity 112, and the first cover plate 110A and the second cover plate 110B are laterally spaced apart from each other. At the same time, a first element layer 120A having a first MEMS element 121 and a second element layer 120B having a second MEMS element 122 are also formed, and the first element layer 120A and the second element layer 120B are laterally spaced apart from each other. In addition, the pressure in the first cavity 111 is maintained at the first pressure. In some embodiments, the pressure in the second cavity 112 can be reduced by vacuuming or other means. For example, the pressure in the second cavity 112 can be reduced from the first pressure to the second pressure through the vent hole in the second cover plate 110B, so that the first cavity 111 has the first pressure and the second cavity 112 has the second pressure lower than the first pressure.

In some embodiments, the first MEMS element 121 having the first thickness T1 is, for example, an accelerometer, and the second MEMS element 122 having the second thickness T2 thinner than the first thickness T1 is, for example, a gyroscope, but is not limited thereto. In addition, the electrode gap of the second MEMS element 122 is smaller than the electrode gap of the first MEMS element 121, wherein the electrode gap of the second MEMS element 122 is the second gap G2 between the protruding electrode 145 and the bottom surface of the second MEMS element 122, and the electrode gap of the first MEMS element 121 is the first gap G1 between a portion 133P of the top metal layer 133 and the bottom surface of the first MEMS element 121. According to the embodiment of the present disclosure, the first MEMS element 121 and the second MEMS element 122 can be manufactured simultaneously using the same element wafer 120, and can be packaged on the same wafer 130 at the same time to complete the micro-electromechanical package 100.

FIG. 10 is a cross-sectional schematic diagram of some stages of a manufacturing method of a MEMS package 100 according to another embodiment of the present disclosure. Referring to FIG. 2 and FIG. 10, in one embodiment, a first cavity 111, a second cavity 112 and a stopper 113 can be simultaneously formed by etching a cap wafer 110, wherein the stopper 113 is formed in the second cavity 112 and connected to the bottom surface of the second cavity 112. In this embodiment, a bonding layer 115 is also deposited on the stopper 113 in a longitudinal direction. Next, after executing the aforementioned steps S103, S105, S107, S109 and S111 on the device wafer 120, please refer to FIG. 10, in step S113B, the device wafer 120 is patterned by an etching process to simultaneously form the first MEMS element 121, the second MEMS element 122 and the pre-cut line 129. Among them, the blocking member 113 is bonded to the second device layer 120B via the bonding layer 115, and during the patterning of the device wafer 120, the blocking member 113 can support the second device portion 122D of the second device layer 120B. In one embodiment, the blocking member 113 may be located at the anchor end of the second MEMS element 122, thereby attaching the second MEMS element 122 to the second cover plate 110B. In another embodiment, after forming the second MEMS element 122, the bonding layer 115 between the blocking member 113 and the second element layer 120B may be removed, thereby releasing the blocking member 113 from the second MEMS element 122 as needed. In addition, the details of other components in step S113B of FIG. 10 may refer to the relevant description of step S113A of FIG. 5 above, and will not be repeated here.

After executing the aforementioned steps S115, S117, S119, S121, S123, S125, S127 and S129, please refer to FIG. 10. In step S131, a portion of the cover wafer 110 and a portion 120P of the device wafer 120 located between the scribe lines SL and the pre-cut lines 129 are removed by a dicing process to complete the MEMS package 100 of FIG. 10. In one embodiment, as shown in FIG. 10, the blocking member 113 is bonded to the second device portion 122D of the second device layer 120B and corresponds to the fixed end of the second MEMS device 122. In another embodiment, the blocking member 113 can be released from the second MEMS device 122. In addition, the details of other components of the MEMS package 100 of FIG. 10 can refer to the relevant description of the MEMS package 100 of FIG. 1, which will not be repeated here. In addition, the manufacturing method of the MEMS package 100 described in the steps of FIG. 2 to FIG. 10 can also be used to manufacture other MEMS packages, which can include more other MEMS elements different from the first MEMS element 121 and the second MEMS element 122.

According to some embodiments of the present disclosure, a MEMS package includes different MEMS components with different component layer thicknesses and different electrode gaps to meet the sensitivity and performance requirements of various MEMS components. These MEMS components can be manufactured simultaneously using the same component wafer and can be packaged simultaneously on the same wafer on which the interconnect layer and protruding electrodes are formed, thereby simplifying the entire manufacturing process of the MEMS package and reducing the cost of the MEMS package.

In addition, in the disclosed MEMS package, the protruding electrode is disposed on the interconnect layer and corresponds to a MEMS element with a thinner element layer thickness, thereby reducing the electrode gap of the MEMS element and improving the sensitivity of the MEMS element. In addition, by disposing a dielectric layer between the protruding electrode and the interconnect layer, the electrode gap between the protruding electrode and the bottom surface of the MEMS element is variable, and the electrode gap of the MEMS element can be controlled by the thickness of the dielectric layer to ensure the sensitivity of the MEMS element. In addition, the manufacturing of the protruding electrode can be compatible with the manufacturing process of the CMOS wafer.

In addition, according to some embodiments of the present disclosure, by thinning and etching the same component wafer, the component layer thickness of different MEMS components can be accurately controlled without using additional component wafers, which can meet the sensitivity and performance requirements of different MEMS components and reduce the cost and time of manufacturing micro-electromechanical packages. In addition, the micro-electromechanical package disclosed in the present disclosure does not require individual wire bonding, thereby reducing parasitic effects. In addition, the micro-electromechanical package disclosed in the present disclosure can be applied to 1-axis, 2-axis, 3-axis and 6-axis inertial measurement units (IMUs), as well as other MEMS components that require different component layer thicknesses and different electrode gaps. The above is only a preferred embodiment of the present invention, and all equal changes and modifications made according to the scope of the patent application of the present invention should be covered by the present invention.

100: MEMS package 100A: first MEMS area 100B: second MEMS area SL: cutting line 110: cover wafer 110A: first cover plate 110B: second cover plate 111: first cavity 112: second cavity 113: barrier 115: bonding layer 117: conductive layer 118: alignment mark 120: device wafer 120A: first device layer 120B: second device layer 120P: part 121: first MEMS device 121D: first device part 121P: first peripheral part 122: second MEMS device 122D: second device part 122P: second peripheral part 124: recessed portion 125A: first bonding seal ring 125B: second bonding seal ring 127: bonding material 128: edge 129: pre-cut line 130: wafer 132: interconnect layer 133: top metal layer 133P: a portion 136: top dielectric layer 138: protective layer 140: dielectric material layer 141: dielectric layer 134, 135A, 135B, 137, 142: opening 143: via hole 145: protruding electrode 160: patterned mask layer 161, 162, 163: slit G1: First gap G2: Second gap T1: First thickness T2: Second thickness d1, T3, T4, T5, T6, T7, T8: Thickness S101, S103, S105, S107, S109, S111, S113A, S113B, S115, S117, S119, S121, S123, S125, S127, S129, S131: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading this disclosure. Through the specific embodiments in this article and referring to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the working principle of the specific embodiments of the present disclosure is explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. Figure 1 is a cross-sectional schematic diagram of a micro-electromechanical system (MEMS) package drawn according to an embodiment of the present disclosure. Figures 2, 3, 4, 5, 6, 7, 8 and 9 are cross-sectional schematic diagrams of some stages of the manufacturing method of the micro-electromechanical system package drawn according to an embodiment of the present disclosure. FIG. 10 is a cross-sectional schematic diagram of some stages of a method for manufacturing a micro-electromechanical system package according to another embodiment of the present disclosure.

100:Micro-electromechanical packaging

100A: First MEMS area

100B: Second MEMS area

SL: Cutting Road

110A: First cover plate

110B: Second cover plate

111: First cavity

112: Second cavity

115: Bonding layer

117: Conductive layer

120A: First component layer

120B: Second component layer

121: First MEMS element

121D: First component part

121P: First outer part

122: Second MEMS element

122D: Second component part

122P: Second outer part

124: Depressed part

125A: First key sealing ring

125B: Second key sealing ring

127: Bonding materials

130: Wafer

132: Interconnection layer

133: Top metal layer

133P:Part

136: Top dielectric layer

138: Protective layer

141: Dielectric layer

143: Conductive hole

145: Protruding electrode

G1: First gap

G2: Second gap

T1: First thickness

T2: Second thickness

Claims (20)

A micro-electromechanical package, comprising: a wafer having an interconnection layer; a first component layer, comprising a first micro-electromechanical component having a first thickness, the first component layer being disposed on the wafer and bonded to the interconnection layer; a second component layer, comprising a second micro-electromechanical component having a second thickness, the second thickness being thinner than the first thickness, the second component layer being disposed on the wafer and bonded to the interconnection layer, the second component layer being laterally spaced from the first component layer; a protruding electrode, disposed above the interconnection layer and directly below the second micro-electromechanical component; a first cover plate, having a first cavity and bonded to the first component layer, wherein the first micro-electromechanical component corresponds to the first cavity; and A second cover plate has a second cavity and is bonded to the second component layer, wherein the second micro-electromechanical component corresponds to the second cavity, and the second cover plate is laterally separated from the first cover plate. The microelectromechanical package as described in claim 1 further includes: a dielectric layer disposed between the electrode of the protrusion and the interconnection layer; and a via penetrating the dielectric layer to electrically connect the electrode of the protrusion to the interconnection layer. A microelectromechanical system package as described in claim 2, wherein the difference between the first thickness and the second thickness is greater than the thickness of the dielectric layer. A micro-electromechanical system package as described in claim 2, wherein the protruding electrode and the dielectric layer have the same pattern in a top view. A micro-electromechanical system package as described in claim 2, wherein the electrode of the protrusion is located directly below a mass block of the second micro-electromechanical system component. A microelectromechanical package as described in claim 1, wherein the interconnect layer includes a top metal layer, a portion of which is exposed through an opening, and the portion of the top metal layer is located directly below the first microelectromechanical component, a first gap is located between the portion of the top metal layer and the first microelectromechanical component, a second gap is located between the protruding electrode and the second microelectromechanical component, and the second gap is smaller than the first gap. A microelectromechanical package as described in claim 1, wherein the first microelectromechanical component includes an accelerometer, the second microelectromechanical component includes a gyroscope, the first cavity has a first pressure, and the second cavity has a second pressure lower than the first pressure. A micro-electromechanical system package as described in claim 1, wherein the second component layer includes a recessed portion facing the interconnection layer, and the electrode of the protrusion is located in the recessed portion. The micro-electromechanical package as described in claim 8 further comprises: a first bonding sealing ring disposed between the first component layer and the wafer and bonded to the interconnection layer; and a second bonding sealing ring disposed between the second component layer and the wafer and bonded to the interconnection layer, wherein a side wall of the recessed portion is vertically aligned with an inner side wall of the second bonding sealing ring. A microelectromechanical package as described in claim 1, wherein the first component layer includes a first component part and a first peripheral part adjacent to the first component part, the second component layer includes a second component part and a second peripheral part adjacent to the second component part, the first component part, the first peripheral part and the second peripheral part all have the first thickness, and the second component part has the second thickness. A method for manufacturing a micro-electromechanical package, comprising: providing a cover wafer; forming a first cavity and a second cavity in the cover wafer; providing a component wafer; bonding the component wafer to the cover wafer, wherein the component wafer covers the first cavity and the second cavity; thinning the component wafer; after the component wafer is bonded to the cover wafer and thinned, etching the component wafer to form a recessed portion corresponding to the second cavity; patterning the component wafer to form a first micro-electromechanical component and a second micro-electromechanical component, wherein the first micro-electromechanical component has a first thickness corresponding to the first cavity, and the second micro-electromechanical component has a second thickness corresponding to the second cavity, and the second thickness is thinner than the first thickness; providing a wafer having an interconnect layer formed thereon; Forming a protruding electrode above the interconnect layer; Bonding the device wafer to the interconnect layer on the wafer, wherein the protruding electrode corresponds to the second micro-electromechanical device; and Removing a portion of the cover wafer and a portion of the device wafer located at a dicing line to form a first cover plate having the first cavity, a second cover plate having the second cavity, a first device layer having the first micro-electromechanical device, and a second device layer having the second micro-electromechanical device. The method for manufacturing a microelectromechanical package as described in claim 11 further includes: forming a dielectric layer between the protruding electrode and the interconnection layer; and forming a via through the dielectric layer, the via electrically connecting the protruding electrode to the interconnection layer. The manufacturing method of the micro-electromechanical package as described in claim 12, wherein forming the protruding electrode, forming the dielectric layer and forming the via comprises: Depositing a dielectric material layer on the interconnect layer; Etching the dielectric material layer and a portion of the interconnect layer to form an opening; Filling the opening to form the via; Depositing a conductive material layer on the dielectric material layer, and the conductive material layer directly contacts the via; Patterning the conductive material layer to form the protruding electrode; and Etching the dielectric material layer using the protruding electrode as a mask to form the dielectric layer. A method for manufacturing a microelectromechanical system package as described in claim 12 or 13, wherein the thickness of the dielectric layer is adjusted according to the difference between the first thickness and the second thickness, and the thickness of the dielectric layer is less than the difference between the first thickness and the second thickness. The manufacturing method of the micro-electromechanical system package as described in claim 11 further includes etching the device wafer to form a first bonding sealing ring and a second bonding sealing ring after thinning the device wafer and before etching the device wafer to form the recessed portion. A method for manufacturing a micro-electromechanical system package as described in claim 15, wherein a side wall of the recessed portion is vertically aligned with an inner side wall of the second keyed sealing ring. The manufacturing method of the micro-electromechanical package as described in claim 11, wherein patterning the device wafer comprises: Forming a patterned mask layer longitudinally on the device wafer and in the recessed portion through a spray coating process; and Etching the device wafer through a plurality of openings of the patterned mask layer to simultaneously form the first micro-electromechanical device and the second micro-electromechanical device. A method for manufacturing a microelectromechanical package as described in claim 11, wherein a first component portion of the component wafer has the first thickness, the first component portion is patterned to form the first microelectromechanical component, and a second component portion of the component wafer has the second thickness, the second component portion is located between the recessed portion and the second cavity, and the second component portion is patterned to form the second microelectromechanical component. A method for manufacturing a micro-electromechanical package as described in claim 18, wherein forming the second cavity in the cover wafer also includes simultaneously forming a barrier member in the second cavity, the barrier member being connected to the bottom surface of the second cavity and bonded to the second component portion of the component wafer. A method for manufacturing a microelectromechanical package as described in claim 11, wherein the first microelectromechanical component includes an accelerometer, the second microelectromechanical component includes a gyroscope, the first cavity has a first pressure, and the second cavity has a second pressure lower than the first pressure.

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