TWI875435B - Circuit substrate - Google Patents

Abstract

A circuit substrate includes a core layer, metal pillars, a first build-up structure and a second build-up structure. The core layer has a thickness of 30 to 150 μm. The core basal layer has a plurality of through holes, the aperture of the through holes on the surface is greater than the hole-width in the core layer, and the ratio of the minimum width of the hole to the aperture is 1/2 to 1. The metal pillars are in the through holes. The first build-up structure and the second build-up structure are respectively on the surfaces of the core base layer, and have a protective layer and electrical connection pillars, respectively. The protective layer includes openings corresponding to the through holes, and the electrical connection pillars are in the openings and connected to the metal pillars. The total thickness of the circuit substrate is greater than 200μm.

Description

Circuit board

The present invention relates to the field of electronics, and in particular to a circuit carrier board.

The biggest challenge for advanced packaging is the flatness and stability of the material base, which is especially challenging during the welding process with large temperature changes. Currently, the core substrate is mainly made of glass fiber. When the thickness is low, it is easy to warp during welding or other processes, which affects the coplanarity and stability of the package surface.

At present, the common method is to slightly increase the thickness of the core board. Generally speaking, when the thickness exceeds 200μm, the warping phenomenon caused by thermal effects will be significantly reduced. However, other problems will also arise at the same time.

As the line width of current chips is reduced, circuit boards may carry more chips, so perforation will be used for three-dimensional packaging. However, as the size is reduced, laser drilling is currently used, which will absorb energy and reduce the diameter of the middle hole. During electroplating, if the air in the hole cannot be discharged smoothly, or there is a local high current density around the hole, making the metal deposition speed faster than the middle hole, the via will be closed by copper metal prematurely, and the existence of internal holes is usually called hole packing phenomenon, which is easy to find electrical defects.

In order to solve the problems faced by the prior art, the inventors sorted out the experimental data and found that the hole-forming problem of general electroplating mainly occurs at a thickness of more than 200 μm. For the traditional 30 to 150 μm, no hole-forming phenomenon is found. Therefore, a circuit carrier is provided. The circuit carrier includes a core base layer, a plurality of metal pillars, at least one first build-up layer structure and at least one second build-up layer structure.

The core substrate layer includes a first surface and a second surface, and the thickness between the first surface and the second surface is 30 to 150 μm. The core substrate layer has a plurality of through holes, each of which penetrates from the first surface to the second surface. The aperture size of the through hole located on the first surface and the second surface is larger than the aperture width located between the first surface and the second surface, wherein the aperture size is 30 to 100 μm, and the ratio of the minimum width in the hole to the aperture size is 1/2 to 1. The metal column is located in the through hole. The first build-up layer structure is located on the first surface of the core substrate layer, and each first build-up layer structure includes a first protective layer and a plurality of first electrical connection columns. The first protective layer includes a plurality of first openings, each first opening corresponds to each through hole, and the first electrical connection column is located in the first opening and connected to the metal column.

The second build-up structure is located on the second surface of the core substrate layer. Each second build-up structure includes a second protective layer and a plurality of second electrical connection pillars. The second protective layer includes a plurality of second openings, the second openings correspond to the through holes, and the second electrical connection pillars are located in the second openings and connected to the metal pillars. The total thickness of the circuit carrier is greater than 200 μm.

In some embodiments, the circuit carrier further includes a plurality of connection pads, which are respectively connected to the metal pillars and are located between the first surface of the core substrate layer and the first protective layer, or between the second surface of the core substrate layer and the second protective layer.

In some embodiments, each first build-up layer structure further includes a first build-up layer connection pad, which is connected to the first electrical connection column and is located on the surface of the first protective layer.

In some embodiments, each second build-up layer structure further includes a second build-up layer connection pad, which is connected to the second electrical connection column and is located on the surface of the second protective layer.

In some embodiments, the thickness between the first surface and the second surface is 80 to 130 μm.

In some embodiments, the pore size is 45 to 80 μm.

In some embodiments, the ratio of the minimum width in the hole to the hole diameter is 3/4 to 1.

In some embodiments, the outermost one of the at least one first build-up layer structure further includes a first circuit pattern layer, and the first circuit pattern layer is connected to the first electrical connection column.

In some embodiments, the outermost one of the at least two first build-up layer structures further includes a second circuit pattern layer, and the second circuit pattern layer is connected to the second electrical connection column.

In some embodiments, the minimum width of each hole is at least greater than 12 μm.

As shown in the aforementioned embodiments, by reducing the thickness of the core substrate layer and using it as a circuit carrier in combination with a build-up layer structure, a sufficient thickness can be achieved to overcome the warping phenomenon caused by thermal stress and, at the same time, avoid the occurrence of hole packing.

It should be understood that when an element is referred to as being "disposed" or "connected" to another element, it may mean that the element is directly located on the other element, or there may be an intermediate element through which the element and the other element are connected. Conversely, when an element is referred to as being "directly disposed/connected to another element" or "directly disposed/connected to another element", it should be understood that it is clearly defined that there are no intermediate elements.

In addition, the terms "first", "second", and "third" are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part, rather than to indicate a necessary order of precedence. In addition, relative terms such as "lower" and "upper" may be used herein to describe the relationship between one element and another element, and it should be understood that the relative terms are intended to include different orientations of the device in addition to the orientation shown in the figure. For example, if a device in an accompanying figure is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. This only indicates a relative orientation relationship, not an absolute orientation relationship.

FIG1 is a partial cross-sectional schematic diagram of a circuit carrier. FIG2 is a partial cross-sectional enlarged diagram of a first embodiment of the circuit carrier. The circuit carrier 1 includes a core substrate layer 10, a plurality of metal pillars 20, at least one first build-up structure 30, and at least one second build-up structure 40. In the first embodiment, for the sake of illustration, the first embodiment is first described with a single layer of the first build-up structure 30 and the second build-up structure 40, but is not limited thereto.

The core substrate layer 10 includes a first surface 11 and a second surface 13. The thickness T between the first surface 11 and the second surface 13, that is, the thickness of the core substrate layer 10, is 30 to 150 μm. Preferably, the thickness is 80 to 130 μm.

The core substrate layer 10 has a plurality of through holes 15, each through hole 15 penetrates from the first surface 11 to the second surface 13. In current applications, the through holes 15 are drilled by laser, and the characteristic of laser drilling is that the aperture R of the through hole 15 is relatively small. The aperture R of the through hole 15 on the first surface 11 and the second surface 13 is 30 to 100 μm, preferably, the aperture R is 45 to 80 μm, for example, 75 μm. In addition, since the energy of the laser will be absorbed, the aperture R of the common laser through hole 15 located on the first surface 11 and the second surface 13 is larger than the width between the first surface 11 and the second surface 13. Usually, the ratio of the minimum width W in the hole to the aperture R is 1/2 to 1, preferably 3/4 to 1. In some embodiments, the minimum width W in the hole is at least greater than 12 μm.

The metal pillar 20 is located in the through-hole 15. It is directly formed by electroplating. According to the experimental records of the inventors, in the thickness range of less than 150 μm, no hole filling phenomenon is found in the through-hole 15 during the subsequent electroplating.

The first build-up structures 30 are located on the first surface 11 of the core substrate layer 10. Each first build-up structure 30 includes a first protection layer 31 and a plurality of first electrical connection pillars 33. The first protection layer 31 includes a plurality of first openings 35 corresponding to the through holes 15. The first electrical connection pillars 33 are located in the first openings 35 and connected to the metal pillars 20.

The second build-up structure 40 is located on the second surface 13 of the core substrate layer 10. Each second build-up structure 40 includes a second protective layer 41 and a plurality of second electrical connection pillars 43. The second protective layer 41 includes a plurality of second openings 45, the second openings 45 correspond to the through-holes 15, and the second electrical connection pillars 43 are located in the second openings 45 and connected to the metal pillars 20. Overall, the total thickness of the circuit carrier 1 is greater than 200 μm, which can reduce the warping phenomenon caused by thermal stress.

FIG3 is a partial cross-sectional enlarged view of the second embodiment of the circuit carrier. As shown in FIG3, with reference to FIG2, the second embodiment is different from the first embodiment in that the circuit carrier 1 further includes a plurality of connection pads 25. The connection pads 25 are respectively connected to the metal pillars 20, and are located between the first surface 11 of the core substrate layer 10 and the first protective layer 31, or between the second surface 13 of the core substrate layer 10 and the second protective layer 41. Here, the connection pads 25 can be manufactured together with the metal pillars 20 by electroplating, which can provide a precision tolerance for manufacturing the first electrical connection pillars 33 or the second electrical connection pillars 43, ensuring electrical connection.

In addition, referring to FIG. 2 , each first layer-added structure 30 may further include a first layer-added connection pad 37, which is connected to the first electrical connection column 33 and is located on the surface of the first protective layer 31. In this way, when adding layers, a precision tolerance can also be provided to ensure electrical connection. Similarly, the second layer-added structure 40 further includes a second layer-added connection pad 47, which is connected to the second electrical connection column 43 and is located on the surface of the second protective layer 41.

FIG4 is a partial cross-sectional enlarged view of the third embodiment of the circuit carrier. As shown in FIG4, a multi-layer build-up structure is used as an example. Here, the outermost one of these first build-up structures 30 further includes a first circuit pattern layer 39, and the first circuit pattern layer 39 is connected to the first electrical connection column 33. Here, the first build-up connection pad 37 can be a part of the first circuit pattern layer 39. Similarly, the outermost one of these second build-up structures 40 further includes a second circuit pattern layer 49, and the second circuit pattern layer 49 is connected to the second electrical connection column 43. In other words, the circuit carrier 1 can make the via filling and the circuit separately. The second build-up connection pad 47 can also be a part of the second circuit pattern layer 49.

In summary, the circuit carrier 1 can be made by filling holes and circuits separately. By increasing the layers, sufficient thickness is ensured to reduce the influence of thermal stress and avoid warping. At the same time, the phenomenon of hole packing is avoided.

Although the technical content of the present invention has been disclosed as above with the preferred embodiments, it is not intended to limit the present invention. Any slight changes and modifications made by anyone skilled in the art without departing from the spirit of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

1: Circuit board 10: Core substrate layer 11: First surface 13: Second surface 15: Perforation 20: Metal pillar 25: Connection pad 30: First build-up structure 31: First protective layer 33: First electrical connection pillar 35: First opening 37: First build-up connection pad 39: First circuit pattern layer 40: Second build-up structure 41: Second protective layer 43: Second electrical connection pillar 45: Second opening 47: Second build-up connection pad 49: Second circuit pattern layer T: Thickness R: Aperture W: Minimum width of the hole

FIG1 is a schematic diagram of a partial cross-section of a circuit carrier. FIG2 is an enlarged partial cross-section of a first embodiment of the circuit carrier. FIG3 is an enlarged partial cross-section of a second embodiment of the circuit carrier. FIG4 is an enlarged partial cross-section of a third embodiment of the circuit carrier.

10: Core base layer

11: First surface

13: Second surface

15:Piercing

20:Metal column

31: First protective layer

33: First electrical connection column

35: First opening

37: First layer connection pad

41: Second protective layer

43: Second electrical connection post

45: Second opening

47: Second layer connection pad

T:Thickness

R: aperture

W: minimum width of the hole

Claims (8)

A circuit carrier, comprising: A core substrate layer, comprising a first surface and a second surface, the thickness between the first surface and the second surface is 30 to 150 μm, the core substrate layer has a plurality of through holes, wherein each of the through holes penetrates from the first surface to the second surface, and each of the through holes has a hole diameter size greater than a hole diameter width between the first surface and the second surface, wherein the hole diameter size is 30 to 100 μm, and the ratio of the minimum width in a hole to the hole diameter size is 1/2 to 1; A plurality of metal pillars, located in the through holes; At least one first build-up layer structure is located on the first surface of the core substrate layer, wherein each of the first build-up layer structures comprises a first protective layer and a plurality of first electrical connection posts, the first protective layer comprises a plurality of first openings, each of the first openings corresponds to each of the through holes, the first electrical connection posts are located in the first openings and connected to the metal posts, wherein each of the first build-up layer structures further comprises a first build-up layer connection pad, the first build-up layer connection pad is connected to the first electrical connection post, and is located on the surface of the first protective layer; and At least one second build-up layer structure is located on the second surface of the core substrate layer, wherein each second build-up layer structure comprises a second protective layer and a plurality of second electrical connection posts, the second protective layer comprises a plurality of second openings, each second opening corresponds to each through hole, the second electrical connection posts are located in the second openings and connected to the metal posts, wherein each second build-up layer structure further comprises a second build-up layer connection pad, the second build-up layer connection pad is connected to the second electrical connection post and is located on the surface of the second protective layer; wherein the total thickness of the circuit carrier is greater than 200μm. A circuit carrier as described in claim 1, wherein the circuit carrier further comprises a plurality of connection pads, which are respectively connected to the metal pillars and are located between the first surface of the core base layer and the first protective layer, or between the second surface of the core base layer and the second protective layer. A circuit carrier as described in claim 1, wherein the thickness between the first surface and the second surface is 80 to 130 μm. A circuit carrier as described in claim 1, wherein the aperture size is 45 to 80 μm. A circuit carrier as described in claim 1, wherein the ratio of the minimum width of the hole to the hole diameter is 3/4 to 1. The circuit carrier as described in claim 1, wherein the outermost one of the at least one first build-up layer structure further includes a first circuit pattern layer, and the first circuit pattern layer is connected to the first electrical connection column. The circuit carrier as described in claim 6, wherein the outermost one of the at least two first build-up layer structures further includes a second circuit pattern layer, and the second circuit pattern layer is connected to the second electrical connection column. A circuit carrier as described in claim 1, wherein the minimum width of each hole is at least greater than 12μm.

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