TWI875215B - Calibration apparatus of memory device and calibration method thereof - Google Patents

Abstract

A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device may be a 3D NAND flash with high capacity and high performance. The calibration apparatus includes a reference impedance, a strong-arm comparator, a logic circuit and a calibration controller. The reference impedance is used to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares the reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal based on the latch signal and the inverted latch signal. The calibration controller performs an impedance calibration in the memory device according to the comparison result signal.

Description

Calibration apparatus and method for memory device

The present invention relates to an impedance calibration technology for a memory device, and in particular to a calibration device for a memory device and a calibration method thereof.

High-capacity and high-performance integrated circuit memory, including 3D NAND flash, is continuing to develop, hoping to use three-dimensional stacking technology and multi-level cells (MLC) to reduce the size of memory cells and increase data storage density, and improve data access and transmission speed.

On the other hand, as the operating speed of electronic devices increases, the swing width of the signal transmitted between memory devices in the electronic device will be correspondingly reduced, thereby reducing the delay time spent on signal transmission. However, as the swing width of the signal is reduced, the transmission of the signal will be greatly affected by external noise, and the signal reflection at the data transmission end will increase due to the impedance mismatch between the transmission paths, making it difficult to transmit data at high speed, reducing signal integrity and affecting the signal transmission quality. Impedance mismatch can be caused by changes in semiconductor manufacturing processes, supply voltage, and operating temperature (PVT). Therefore, calibrating the impedance in the data transmission path (e.g., ZQ calibration) is used to solve the problem of reduced signal integrity due to impedance mismatch during high-speed data transmission.

The present invention provides an impedance calibration technology for a memory device, which can reduce the error rate of impedance calibration and improve the signal integrity in the memory device.

The calibration equipment of the memory device described in the embodiment of the present invention includes an impedance, a strong-arm comparator, a logic circuit and a calibration controller. The impedance is used to generate a comparison voltage. The strong-arm comparator includes a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal receives a reference voltage. The inverting input terminal receives the comparison voltage. The strong-arm comparator compares the reference voltage with the comparison voltage to generate a comparison result, and latches the comparison result and correspondingly generates a latch signal and an inverted latch signal. The logic circuit is coupled to the strong-arm comparator. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. And the calibration controller implements impedance calibration in the memory device according to the comparison result signal.

Based on the above, the calibration device and calibration method of the memory device described in the embodiment of the present invention utilizes the change of circuit structure (for example, replacing the original comparison circuit with a strong arm comparator, adjusting the structure of the logic circuit) to reduce the delay time in comparing the comparison signal with the reference signal, so that the subsequent impedance calibration circuit (such as the controller implementing ZQ calibration) has sufficient timing budget and calculation margin, reducing the error rate of impedance calibration and improving the signal integrity in the memory device.

150: memory block

152: Page

154: Memory cell string

156. SSL: Serial Selection Line

157: Memory cells

158. GSL: Ground selection line

159. CSL: Common Source Line

BLn, BLn+1: bit line

WL0~WL95: character line

200, 400, 700: Calibration equipment

210, 410: Impedance

220: Comparator

231: Delay element

234, 434: Data Flip-Flop (DFF)

240, 440: Calibration controller

250, 450: Adjust the drive

310, 320, 610: arrows

420: Strong Arm Comparator

430:Logical Circuit

432: Anti-gate

510: Differential input pair

520: latch

530-1, 530-2: Reset circuit

660: Preamplifier

S910~S950: Steps of the memory device calibration method

VREF: reference voltage

Vdr: comparison voltage

Vin+: non-inverting input terminal

Vin-: inverting input terminal

OSC: clock signal

OSCB: Inverted clock signal

Cout: comparator output terminal

OSCBD: delayed clock signal

LAT_OUT1: Comparison results

LAT_OUT: latch signal

LAT_OUTB: Inverted latch signal

Result, Sres: comparison result signal

ZQS[n：0]: calibration signal

D: Data input port

CK: Clock receiving end

Q: Data output port

code1~code3: encoding

CDT1~CDT2: comparison delay

CADT1~CADT2: Calculate delay

VRT1~VRT2: reference voltage adjustment time

O1, O2, O3, R1, R2, R3: Data

OUT1: The first output terminal of the strong-arm comparator

OUT2: The second output terminal of the strong arm comparator

PO1: The first output terminal of the differential input pair

PO2: The second output terminal of the differential input pair

DFF_CK: Flip-flop clock signal

M1~M10, MCL: transistor

VDD: system voltage terminal

INV1, INV2: Inverter

Figure 1 is a schematic diagram of the structure of a memory block in a 3D memory chip according to an embodiment of the present invention.

FIG2 is a circuit block diagram of a calibration device for a memory device according to the first embodiment of the present invention.

Figure 3 is a timing diagram of the signals of the calibration equipment in Figure 2.

FIG4 is a circuit block diagram of a calibration device for a memory device according to the second embodiment of the present invention.

Figure 5 is a detailed circuit diagram of the strong arm comparator in Figure 4.

Figure 6 is a timing diagram of the signals of the calibration device in Figure 4.

FIG7 is a circuit block diagram of a calibration device for a memory device according to the third embodiment of the present invention.

Figures 8A and 8B respectively show schematic diagrams of the states corresponding to the calibration signals when the calibration controller uses linear search or binary search.

Figure 9 is a flow chart of a method for calibrating a memory device according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of the structure of a memory block 150 in a three-dimensional memory chip according to an embodiment of the present invention. The memory block 150 may be a part of a three-dimensional NAND flash memory with high capacity and high performance. The plurality of memory cells in the memory block 150 are arranged in three dimensions, for example, an XYZ coordinate system. Taking the memory cell 157 as an example, the memory cell 157 is coupled to the corresponding word line WL0 and the bit line BL. The word lines (e.g., word lines WL0~WL95) formed by the conductive layer or the word line layer and the plurality of memory cells coupled thereto form a plurality of pages 152. In other words, the memory cells in the memory block 150 are divided into a plurality of pages 152. Each page 152 can be, for example, a layer of memory cells in the XY plane, and the memory cells on the same layer (same page) are coupled to the same word line (e.g., word line WL0 or WL95) and obtain the corresponding word line voltage. Memory cells on different layers (different pages) are coupled to different word lines. Each page can be connected to a corresponding contact in the drive circuit, such as an X decoder (or scan driver). Each line has a corresponding voltage driver, and these voltage drivers can be controlled by a memory controller (not shown) or corresponding hardware. Multiple memory cells in the memory cell string 154 belong to different pages.

The memory cell string 154 includes a plurality of memory cells connected in series vertically along the Z direction. The memory cell is configured as a string select transistor SST coupled to a string select line SSL 156, and the memory cell may also be configured as a ground select transistor GST coupled to a ground select line GSL 158. The memory cell string 154 is connected to one or more drivers, such as a data driver. The memory cell string 154 including the memory cell 157 is connected to a common source line CSL 159 via a ground select transistor GST. SSL 156 may be a conductive line or conductive layer formed on the top of each page 152 (or word line layer). The memory block 150 may include a plurality of SSLs 156 provided on the top of the page 152. GSL 158 may be a conductive line or conductive layer formed on the bottom of each page 152 (or word line layer). CSL 159 may be a conductive layer or multiple conductive lines formed on the substrate of the three-dimensional storage chip. Several virtual lines or corresponding layers (not shown) may also be provided between the serial selection line SSL 156 and the topmost page 152, or between the ground selection line GSL 158 and the bottommost page 152.

On the other hand, in order to improve signal integrity and enhance the strength of the output signal, whether it is the NAND flash memory device in Figure 1 or the double data rate synchronous dynamic random access memory (DDR SDRAM), the memory device can have a terminal resistor and a corresponding adjustment driver to calibrate the impedance on the data transmission path (such as ZQ calibration), thereby reducing the impedance mismatch caused by changes in semiconductor manufacturing process, supply voltage and operating temperature (PVT), thereby maintaining signal integrity.

FIG2 is a circuit block diagram of a calibration device 200 for a memory device according to the first embodiment of the present invention. The calibration device 200 in FIG2 includes an impedance 210, a comparator 220, a delay element 231, a data flip-flop (DFF) 234, a calibration controller 240, and an adjustment driver 250. Impedance 210 can be referred to as a reference impedance, which generates a comparison voltage Vdr by adjusting the current provided by the driver. The comparator 220 has a non-inverting input terminal Vin+, an inverting input terminal Vin-, and an output terminal Cout. The non-inverting input terminal Vin+ receives a reference voltage VREF, and the inverting input terminal Vin- receives a comparison voltage Vdr. The comparator 220 uses the inverted clock signal OSCB which is inverse to the clock signal OSC as its clock signal to make the comparator 220 perform its function. The comparator 220 is used to compare the reference voltage VREF with the comparison voltage Vdr to generate a comparison result LAT_OUT1 at its output terminal Cout. The calibration device 200 of FIG2 also includes a reference voltage generator, which is controlled by the calibration signal ZQS[n:0] to adjust the voltage value of the reference voltage VREF accordingly.

Since the comparator 220 needs a period of processing time to compare the reference voltage VREF with the comparison voltage Vdr, it cannot generate the comparison result LAT_OUT1 to the DFF 234 immediately. Therefore, the delay element 231 delays the inverted clock signal OSCB for a predetermined time to generate a delayed clock signal OSCBD. The DFF 234 uses the delayed clock signal OSCBD as the clock signal of the DFF 234 to enable the DFF 234 to perform its function.

The calibration controller 240 implements impedance calibration (e.g., ZQ calibration) in the memory device according to the comparison result signal Result generated by the DFF 234. In detail, the calibration controller 240 generates a calibration signal ZQS[n:0] according to the comparison result signal Result to implement impedance calibration. The calibration signal ZQS[n:0] can represent the strength of the ZQ calibration and can be used as a signal provided to the adjustment driver 250. The adjustment driver 250 coupled to the impedance 210 generates an adjusted current according to the calibration signal ZQS[n:0]. The impedance 210 generates a comparison voltage Vdr through the adjusted current generated by the adjustment driver 250. The comparator 220, delay element 231, DFF 234, calibration controller 240 and adjustment driver 250 in the calibration device 200 are arranged in the chip, and the impedance 210 is a resistor or impedance transistor arranged outside the chip and coupled to a specific pin (e.g., ZQ pin) of the chip. The aforementioned resistor can be a passive resistor.

The processing time (herein referred to as comparison delay) of the comparator 220 when comparing the reference voltage VREF with the comparison voltage Vdr will correspondingly squeeze the processing time of the calibration controller 240 when implementing impedance calibration. In other words, the calibration controller 240 will not have sufficient timing budget, thereby affecting the accuracy of impedance calibration.

FIG3 is a timing diagram of each signal of the calibration device 200 in FIG2. Each state 1 to state 3 represents a ZQ calibration. The label "Vdr/VREF" in FIG3 is used to represent the comparison voltage Vdr (the corresponding solid line waveform of "Vdr/VREF" in FIG3) and the reference voltage VREF (the corresponding dashed line of "Vdr/VREF" in FIG3). It can be seen from the arrow 310 in FIG3 that the time point from the rising edge of the clock signal (inverted clock signal OSCB) corresponding to the comparator 220 to the time point when the comparator 220 generates the first data O1 in the comparison result LAT_OUT1 is the aforementioned comparison delay CDT1. In order to make the operation timing of DFF 234 in FIG. 2 correct, as shown by arrow 320, the timer in delay element 231 delays the inverted clock signal OSCB for a predetermined time to generate a delayed clock signal OSCBD. This can prevent DFF 234 from latching an erroneous result due to the slow output of comparator 220. In this way, the calibration controller 240 in Figure 2 can only calculate the code code2 in the corresponding calibration signal ZQS[n:0] within the calculation delay CADT1 time period, and in the next state (for example, state 2), the calibration controller 240 provides the calibration signal ZQS[n:0] with code code2 to the adjustment driver 250, so that the calibration controller 240 adjusts the voltage value of the reference voltage VREF in the reference voltage adjustment time VRT1, and continues the next ZQ calibration in state 2. The data O1, O2, and O3 in the comparison result LAT_OUT1 correspond to the data calculated in different states. The data R1, R2, and R3 in the comparison result signal Result correspond to the data calculated in different states.

As can be seen from Figure 3, the time point at which the comparator 220 generates the first data O1 in the comparison result LAT_OUT1 is delayed due to the comparison delay CDT1, which causes the calculation delay CADT1 of the calibration controller 240 in performing ZQ calibration to be shortened, correspondingly shortening the update time of the calibration signal ZQS[n:0] and shortening the reference voltage adjustment time VRT1. If the calibration signal ZQS[n:0] is updated too late, it will affect the reference voltage VREF in the next state and affect the comparator in the next state.

The second embodiment of the present invention uses a strong arm comparator including a differential input pair and a latch to replace the comparator 220 in FIG. 2, and replaces the delay element 231 composed of multiple inverters with an anti-AND gate in the logic circuit, so that the calibration device can have more timing budget when establishing the reference voltage VREF in the next state, and extend the timing budget of the calibration controller 240 to perform and calculate the ZQ calibration.

FIG4 is a circuit block diagram of a calibration device 400 for a memory device according to the second embodiment of the present invention. The main difference between FIG2 and FIG4 is that the calibration device 400 replaces the comparator 220 of FIG2 with the strong arm comparator 420 of FIG4, and the calibration device 400 uses the negative AND gate 432 in the logic circuit 430 to replace the delay element composed of multiple inverters. In detail, the calibration device 400 is composed of an impedance 410, a strong arm comparator 420, a logic circuit 430, a calibration controller 440 and an adjustment driver 450. The functions of the impedance 410, the calibration controller 440 and the adjustment driver 450 are the same as those of the corresponding elements in FIG2.

The non-inverting input terminal Vin+ of the strong arm comparator 420 receives the reference voltage VREF, and the inverting input terminal Vin- of the strong arm comparator 420 receives the comparison voltage Vdr. The strong arm comparator 420 generates a latch signal LAT_OUT and an inverted latch signal LAT_OUTB at its first output terminal OUT1 and second output terminal OUT2 by comparing the reference voltage VREF with the comparison voltage Vdr. The detailed circuit structure of the strong arm comparator 420 is shown in FIG5 and the corresponding description.

The logic circuit 430 is coupled to the strong arm comparator 420. The logic circuit 430 generates a comparison result signal Sres according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. In detail, the logic circuit 430 mainly includes an NAND gate 432 and a DFF 434. The first input terminal of the NAND gate 432 receives the latch signal LAT_OUT, and the second input terminal of the NAND gate 432 receives the inverted latch signal LAT_OUTB. The output terminal of the NAND gate 432 generates a flip-flop clock signal DFF_CK. Therefore, when the polarity of the latch signal LAT_OUT or the inverted latch signal LAT_OUTB is reversed, the flip-flop clock signal DFF_CK will trigger DFF 434.

DFF 434 includes a data input terminal D, a clock receiving terminal CK, and a data output terminal Q. The data input terminal D receives the latch signal LAT_OUT, and the clock receiving terminal CK receives the flip-flop clock signal DFF_CK. DFF 434 generates a comparison result signal Sres at the data output terminal Q according to the latch signal LAT_OUT and the flip-flop clock signal DFF_CK. The calibration controller 440 generates a calibration signal ZQS[n:0] according to the comparison result signal Sres, and the calibration signal ZQS[n:0] is provided to the adjustment driver 450 and is used to set the reference voltage VREF through the reference voltage generator.

FIG5 is a detailed circuit diagram of the strong arm comparator 420 of FIG4. The strong arm comparator 420 of FIG5 mainly includes a differential input pair 510 and a latch 520. The differential input pair 510 includes a first input terminal and a second input terminal, the first input terminal is used as the non-inverting input terminal Vin+ of the strong arm comparator 420 to receive the reference voltage VREF, and the second input terminal is used as the inverting input terminal Vin- of the strong arm comparator 420 to receive the comparison voltage Vdr. The differential input pair 510 compares the reference voltage VREF with the comparison voltage Vdr to generate a comparison result.

In detail, the differential input pair 510 includes a first transistor M1 and a second transistor M2. The control end of the transistor M1 is coupled to the non-inverting input terminal Vin+ of the strong arm comparator 420, and the first end of the transistor M1 serves as the first output terminal PO1 of the differential input pair 510. The control end of the transistor M2 is coupled to the inverting input terminal Vin- of the strong arm comparator 420. The first end of the transistor M2 serves as the second output terminal PO2 of the differential input pair 510. The second end of the transistor M1 is coupled to the second end of the transistor M2. The differential input pair 510 further includes a control transistor MCL and a current source 540. The first end of the control transistor MCL is coupled to the second end of the transistor M1 and the second end of the transistor M2. The control end of the control transistor MCL receives the clock signal CKB. The current source 540 is coupled to the second end of the control transistor MCL. The transistors M1, M2 and MCL of this embodiment are all N-type transistors.

The latch 520 of FIG5 latches the comparison result provided by the first output terminal PO1 and the second output terminal PO2 of the differential input pair 510 and generates a latch signal LAT_OUT and an inverted latch signal LAT_OUTB at the first output terminal OUT1 and the second output terminal OUT2 thereof. In detail, the latch 520 of FIG5 includes a first inverter INV1 and a second inverter INV2. The input terminal of the inverter INV1 is coupled to the first output terminal OUT1 of the strong arm comparator 420. The output terminal of the inverter INV1 is coupled to the second output terminal OUT2 of the strong arm comparator 420. The ground terminal of the inverter INV1 is coupled to the second output terminal PO2 of the differential input pair 510. The first output terminal OUT1 and the second output terminal OUT2 are used to generate a latch signal LAT_OUT and an inverted latch signal LAT_OUTB respectively. The input terminal of the inverter INV2 is coupled to the second output terminal OUT2 of the strong arm comparator 420, the output terminal of the inverter INV2 is coupled to the first output terminal OUT1 of the strong arm comparator 420, and the ground terminal of the inverter INV2 is coupled to the first output terminal PO1 of the differential input pair 510.

The inverter INV1 includes transistors M3 and M4. The control end of the transistor M3 is coupled to the first output end OUT1 of the strong arm comparator 420. The first end of the transistor M3 is coupled to the second output end OUT2 of the strong arm comparator 420. The second end of the transistor M3 is coupled to the second output end PO2 of the differential input pair 510. The control end of the transistor M4 is coupled to the first output end OUT1 of the strong arm comparator 420. The first end of the transistor M4 is coupled to the system voltage end VDD. The second end of the transistor M4 is coupled to the second output end OUT2 of the strong arm comparator 420.

The inverter INV2 includes transistors M5 and M6. The control end of transistor M5 is coupled to the second output end OUT2 of the strong arm comparator 420. The first end of transistor M5 is coupled to the first output end OUT1 of the strong arm comparator 420. The second end of transistor M5 is coupled to the first output end PO1 of the differential input pair 510. The control end of transistor M6 is coupled to the second output end OUT2 of the strong arm comparator 420, the first end of transistor M6 is coupled to the system voltage end VDD, and the second end of transistor M6 is coupled to the first output end OUT1 of the strong arm comparator 420. Transistors M3 and M5 are both N-type transistors, and transistors M4 and M6 are both P-type transistors.

The strong arm controller 420 further includes reset circuits 530-1 and 530-2. The reset circuits 530-1 and 530-2 couple the differential input pair 510 and the latch 520. The reset circuits 530-1 and 530-2 reset the first output terminal PO1 and the second output terminal PO2 of the differential input pair 510 and reset the latch 520 according to the clock signal CKB (i.e., the inverted clock signal OSCB in FIG. 4).

In detail, the reset circuit 530-1 includes transistors M7 and M8. The control end of the transistor M7 receives the clock signal CKB, the first end of the transistor M7 is coupled to the system voltage terminal VDD, and the second end of the transistor M7 is coupled to the first output terminal OUT1 of the strong arm comparator 420. The control end of the transistor M8 receives the clock signal CKB, the first end of the transistor M8 is coupled to the system voltage terminal VDD, and the second end of the transistor M8 is coupled to the first output terminal PO1 of the differential input pair 510. The reset circuit 530-2 includes transistors M9 and M10. The control end of the transistor M9 receives the clock signal, the first end of the transistor M9 is coupled to the system voltage terminal, and the second end of the transistor M9 is coupled to the second output terminal OUT2 of the strong arm comparator 420. The control end of transistor M10 receives the clock signal CKB, the first end of transistor M10 is coupled to the system voltage end VDD, and the second end of transistor M10 is coupled to the second output end PO2 of the differential input pair 510. Transistors M7 to M10 are all P-type transistors.

When the clock signal CKB is enabled, both ends of transistors M7 to M10 in the reset circuits 530-1 and 530-2 in FIG5 are turned on, so that the potentials of the first output terminal OUT1, the second output terminal OUT2 of the strong arm comparator 420, the first output terminal PO1, and the second output terminal PO2 of the differential input pair 510 are all raised to the same potential as the system voltage terminal VDD, thereby achieving the reset of the differential input pair 510 and the latch 520.

FIG6 is a timing diagram of each signal of the calibration device 400 in FIG4. The label "Vdr/VREF" in FIG6 is used to represent the comparison voltage Vdr (the corresponding solid line waveform of "Vdr/VREF" in FIG6) and the reference voltage VREF (the corresponding dashed line of "Vdr/VREF" in FIG6). Each state 1 to state 3 represents a ZQ calibration. From the arrow 610 in FIG6, it can be seen that the time point from the rising edge of the clock signal (inverted clock signal OSCB) corresponding to the strong arm comparator 420 to the time point when the strong arm comparator 420 generates the data O1 in the comparison result LAT_OUT1 is the comparison delay CDT2.

On the other hand, when the polarities of the latch signal LAT_OUT and the inverted latch signal LAT_OUTB are different, the flip-flop clock signal DFF_CK will be switched from disable to enable due to the NAND gate 432 in FIG. 4 , and DFF 434 will provide the comparison result signal Sres to the calibration controller 440 in FIG. 4 , so that the calibration controller 440 in FIG. 4 can calculate the code code2 in the corresponding calibration signal ZQS[n:0] within the time period of calculating the delay CADT2, and in the next state (for example, state 2), the calibration controller 440 will provide the calibration signal ZQS[n:0] having the code code2 to the adjustment driver 450. The calibration controller 440 adjusts the voltage value of the reference voltage VREF during the reference voltage adjustment time VRT2, and continues the next ZQ calibration in state 2.

Comparing Figure 3 and Figure 6, the time length of the comparison delay CDT2 in Figure 6 is significantly shorter than the comparison delay CDT1 in Figure 3. In addition, the calculated delay CADT2 of the calibration controller 440 in Figure 6 during ZQ calibration is significantly longer than the calculated delay CADT1 in Figure 3, and the reference voltage adjustment time VRT2 in Figure 6 is significantly longer than the reference voltage adjustment time VRT1 in Figure 2. In this way, the calibration controller 440 in Figure 6 can have more time to calculate the ZQ calibration and adjust the reference voltage VREF, thereby avoiding calibration errors.

FIG7 is a circuit block diagram of a calibration device 700 for a memory device according to the third embodiment of the present invention. Compared with the second embodiment of FIG6 , the calibration device 700 of FIG7 further includes a preamplifier 660 when the circuit design conditions are met. The preamplifier 660 is coupled between the strong arm comparator 420 and the impedance 410. The non-inverting input terminal Vin+ of the strong arm comparator 420 receives the reference voltage VREF through the preamplifier 660. The inverting input terminal Vin- of the strong arm comparator 420 receives the comparison voltage Vdr through the preamplifier 660. Specifically, the two input terminals of the preamplifier 660 receive the reference voltage VREF and the comparison voltage Vdr respectively, and the two output terminals of the preamplifier 660 are respectively coupled to the non-inverting input terminal Vin+ and the inverting input terminal Vin- of the strong arm comparator 420 to amplify the difference between the reference voltage VREF and the comparison voltage Vdr.

The calibration controller 240 in Figures 2 and 4 can use multiple methods to implement ZQ calibration. Figures 8A and 8B respectively present schematic diagrams of the states corresponding to the calibration signal ZQS[n:0] when the calibration controller uses linear search or binary search, where n and M are positive integers, and M is less than or equal to n. Linear search (corresponding to Figure 8A) or binary search (corresponding to Figure 8B) is used as an example to illustrate that ZQ calibration can have multiple implementation modes.

FIG9 is a flow chart of a calibration method for a memory device according to an embodiment of the present invention. The calibration method described in FIG9 can be applied to the calibration device 400 in FIG4. Please refer to FIG4 and FIG9 at the same time. In step S910, a comparison voltage Vdr is generated according to the impedance 410. In detail, the adjustment driver 450 is used to generate an adjusted current according to the calibration signal ZQS[n:0] so that the impedance 410 generates a comparison voltage Vdr.

In step S920, the strong arm comparator 420 is used to compare the comparison voltage Vdr and the reference voltage VREF to generate a comparison result. In step S930, the strong arm comparator 420 is used to latch the aforementioned comparison result, and correspondingly generates a latch signal LAT_OUT and an inverted latch signal LAT_OUTB. Specifically, the strong arm comparator 420 generates a latch signal LAT_OUT at its first output terminal OUT1 and generates an inverted latch signal LAT_OUTB at its second output terminal OUT2.

In step S940, the logic circuit 430 is used to generate the comparison result signal Sres according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. Specifically, the NAND gate 432 is used to generate the flip-flop clock signal DFF_CK according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. Furthermore, the data flip-flop 434 is used to generate the comparison result signal Sres according to the latch signal LAT_OUT, the inverted latch signal LAT_OUTB and the flip-flop clock signal DFF_CK. When the polarity of the latch signal LAT_OUT or the inverted latch signal LAT_OUTB is reversed, the flip-flop clock signal DFF_CK will be enabled to trigger the data flip-flop 434.

In step S950, the calibration controller 440 generates a calibration signal ZQS[n:0] according to the comparison result signal Sres to implement impedance calibration in the memory device. As described in the above embodiment, the impedance calibration can be ZQ calibration, and the implementation of ZQ calibration uses linear search or binary search.

In other embodiments consistent with the present invention, the preamplifier 660 of FIG. 7 can also be used to expand the voltage difference between the reference voltage VREF and the comparison voltage Vdr, so that the strong arm comparator 420 is more sensitive to the comparison between the reference voltage VREF and the comparison voltage Vdr. The detailed process and circuit structure details of the aforementioned steps can refer to the aforementioned embodiments.

In summary, the calibration device and calibration method of the memory device described in the embodiment of the present invention utilizes the change of circuit structure (for example, replacing the original comparison circuit with a strong arm comparator, adjusting the structure of the logic circuit) to reduce the delay time in comparing the comparison signal with the reference signal, so that the subsequent impedance calibration circuit (such as the controller implementing ZQ calibration) has sufficient timing budget and calculation margin, reduces the error rate of impedance calibration and improves the signal integrity in the memory device.

400: Calibration equipment

410: Impedance

434: Data flip-flop

440: Calibration controller

450: Adjust the drive

420: Strong Arm Comparator

430:Logical Circuit

432: Anti-gate

VREF: reference voltage

Vdr: comparison voltage

Vin+: non-inverting input terminal

Vin-: inverting input terminal

OSCB: Inverted clock signal

LAT_OUT: latch signal

LAT_OUTB: Inverted latch signal

Sres: comparison result signal

ZQS[n：0]: calibration signal

D: Data input port

Q: Data output port

CK: Clock receiving end

OUT1: The first output terminal of the strong-arm comparator

OUT2: The second output terminal of the strong arm comparator

DFF_CK: Flip-flop clock signal

Claims (20)

A memory device calibration device includes: an impedance for generating a comparison voltage; a strong-arm comparator, the strong-arm comparator including: a non-inverting input terminal, the non-inverting input terminal receiving a reference voltage; an inverting input terminal, the inverting input terminal receiving the comparison voltage, the strong-arm comparator comparing the reference voltage with the comparison voltage to generate a comparison voltage. A comparison result is generated, and the comparison result is latched and a latch signal and an inverted latch signal are generated accordingly; a first output terminal outputs the latch signal; and a second output terminal outputs the inverted latch signal; a logic circuit is coupled to the strong arm comparator, and generates a comparison result signal according to the latch signal and the inverted latch signal; and a calibration controller is configured to generate a comparison result signal according to the comparison result. The result signal implements impedance calibration in the memory device, wherein the logic circuit includes: a logic subcircuit, a first input terminal of the logic subcircuit is coupled to the first output terminal of the strong arm comparator, a second input terminal of the logic subcircuit is coupled to the second output terminal of the strong arm comparator, and an output terminal of the logic subcircuit generates a clock signal; and a data positive and negative The device comprises a data input terminal, a clock receiving terminal and a data output terminal. The first output terminal of the strong arm comparator is coupled to the data input terminal, the output terminal of the logic circuit is coupled to the clock receiving terminal, and the data flip-flop generates the comparison result signal at the data output terminal according to the latch signal and the clock signal generated by the logic circuit. A calibration device as described in claim 1, wherein the logic subcircuit includes an NAND gate, a first input terminal of the NAND gate receives the latch signal, a second input terminal of the NAND gate receives the inverted latch signal, and an output terminal of the NAND gate is coupled to an output terminal of the logic subcircuit. A calibration device as described in claim 2, wherein when the polarity of the latch signal or the inverted latch signal is reversed, the clock signal will be enabled to trigger the data flip-flop. As described in claim 1, the strong-arm comparator comprises: a differential input pair, including a first input terminal and a second input terminal, the first input terminal serving as the non-inverting input terminal of the strong-arm comparator to receive the reference voltage, the second input terminal serving as the inverting input terminal of the strong-arm comparator to receive the comparison voltage, the differential input pair compares the reference voltage with the comparison voltage to generate the comparison result; and a latch, coupled to the differential input pair, latches the comparison result and correspondingly generates the latch signal and the inverted latch signal. As described in claim 4, the differential input pair includes: a first transistor, whose control end is coupled to the non-inverting input end of the strong arm comparator, and the first end of the first transistor serves as the first output end of the differential input pair; and a second transistor, whose control end is coupled to the inverting input end of the strong arm comparator, the first end of the second transistor serves as the second output end of the differential input pair, and the second end of the first transistor is coupled to the second end of the second transistor. The calibration device as described in claim 5, wherein the differential input pair further comprises: a control transistor, a first end of which is coupled to the second end of the first transistor and the second end of the second transistor, and the control end of the control transistor receives a clock signal; and a current source, coupled to the second end of the control transistor. The calibration device as described in claim 4, wherein the latch comprises: a first inverter, whose input end is coupled to the first output end of the strong arm comparator, whose output end is coupled to the second output end of the strong arm comparator, and whose ground end is coupled to the second output end of the differential input pair; and a second inverter, whose input end is coupled to the second output end of the strong arm comparator, whose output end is coupled to the first output end of the strong arm comparator, and whose ground end is coupled to the first output end of the differential input pair, wherein the first output end and the second output end of the strong arm comparator are used to generate the latch signal and the inverted latch signal respectively. The calibration device as described in claim 7, wherein the first inverter comprises: a third transistor, whose control terminal is coupled to the first output terminal of the strong-arm comparator, a first terminal of the third transistor is coupled to the second output terminal of the strong-arm comparator, and a second terminal of the third transistor is coupled to the second output terminal of the differential input pair; and a fourth transistor, whose control terminal is coupled to the first output terminal of the strong-arm comparator, a first terminal of the fourth transistor is coupled to the system voltage terminal, and a second terminal of the fourth transistor is coupled to the second output terminal of the strong-arm comparator. The calibration device as described in claim 7, wherein the second inverter comprises: a fifth transistor, whose control terminal is coupled to the second output terminal of the strong-arm comparator, a first terminal of the fifth transistor is coupled to the first output terminal of the strong-arm comparator, and a second terminal of the fifth transistor is coupled to the first output terminal of the differential input pair; and a sixth transistor, whose control terminal is coupled to the second output terminal of the strong-arm comparator, a first terminal of the sixth transistor is coupled to the system voltage terminal, and a second terminal of the sixth transistor is coupled to the first output terminal of the strong-arm comparator. As described in claim 4, the strong arm controller further includes: a reset circuit, coupling the differential input pair and the latch, resetting the first output terminal and the second output terminal of the differential input pair and resetting the latch according to the clock signal. A calibration device as described in claim 10, wherein the reset circuit includes: a seventh transistor, whose control end receives the clock signal, the first end of the seventh transistor is coupled to the system voltage end, and the second end of the seventh transistor is coupled to the first output end of the strong-arm comparator; an eighth transistor, whose control end receives the clock signal, the first end of the eighth transistor is coupled to the system voltage end, and the second end of the eighth transistor is coupled to the first output end of the differential input pair; a ninth transistor, whose control end receives the clock signal, the first end of the ninth transistor is coupled to the system voltage end, and the second end of the ninth transistor is coupled to the second output end of the strong-arm comparator; and a tenth transistor, whose control end receives the clock signal, the first end of the tenth transistor is coupled to the system voltage end, and the second end of the tenth transistor is coupled to the second output end of the differential input pair. The calibration device as described in claim 1 further includes: an adjustment driver coupled to the impedance, wherein the impedance generates the comparison voltage through the adjusted current generated by the adjustment driver. A calibration device as described in claim 12, wherein the calibration controller generates a calibration signal based on the comparison result signal to implement the impedance calibration, and the adjustment driver is controlled by the calibration signal to generate the adjusted current. The calibration device as described in claim 1 further comprises: a preamplifier coupled between the strong arm comparator and the impedance, wherein the non-inverting input of the strong arm comparator receives the reference voltage through the preamplifier, and the inverting input of the strong arm comparator receives the comparison voltage through the preamplifier, wherein the preamplifier is used to amplify the voltage difference between the reference voltage and the comparison voltage. A calibration device as described in claim 1, wherein the impedance calibration is a ZQ calibration, and the calibration controller uses a linear search or a binary search to implement the ZQ calibration. A method for calibrating a memory device includes: generating a comparison voltage according to impedance; comparing the comparison voltage with a reference voltage based on a strong arm comparator to generate a comparison result; latching the comparison result and correspondingly generating a latch signal and an inverted latch signal; generating a comparison result signal according to the latch signal and the inverted latch signal; and generating a calibration signal according to the comparison result signal to implement impedance calibration in the memory device, wherein the step of generating the comparison result signal according to the latch signal and the inverted latch signal includes: using a logic circuit to generate a comparison result signal according to the latch signal and the inverted latch signal. The latch signal and the inverted latch signal generate a clock signal, wherein the first input terminal of the logic circuit is coupled to the first output terminal of the strong arm comparator, the second input terminal of the logic circuit is coupled to the second output terminal of the strong arm comparator, and the output terminal of the logic circuit generates the clock signal; and a data flip-flop is used to generate the comparison result signal according to the latch signal, the inverted latch signal and the clock signal, wherein when the polarity of the latch signal or the inverted latch signal is reversed, the clock signal will be enabled to trigger the data flip-flop. A calibration method as described in claim 16, wherein the logic subcircuit includes an NAND gate, a first input terminal of the NAND gate receives the latch signal, a second input terminal of the NAND gate receives the inverted latch signal, and an output terminal of the NAND gate is coupled to the output terminal of the logic subcircuit. The calibration method as described in claim 16, wherein the step of generating the comparison voltage according to the impedance includes: using an adjustment driver to generate an adjusted current according to the calibration signal so that the impedance generates the comparison voltage. The calibration method as described in claim 16 further includes: using a preamplifier to amplify the voltage difference between the reference voltage and the comparison voltage. A calibration method as described in claim 16, wherein the impedance calibration is a ZQ calibration, and the ZQ calibration is implemented using a linear search or a binary search.

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