TWI874051B - Method and computer program product and apparatus for programming and recovering protected data - Google Patents

Abstract

The invention is related to a method, a computer program product and an apparatus for programming and recovering protected data. The method, performed by a processing unit, includes: receiving protected data instructed by a data write command in multiple batches from a host side; and after an intermediate calculation result is generated by using an encoding algorithm according to a first portion of the protected data and an authentication key, arranging multiple authentication calculation operations for the remaining portions of the protected data and multiple data programming operations for all portions of the protected data, thereby enabling the authentication calculation operations and the data programming operations to be performed in parallel partially. The authentication calculation operations calculate a message authentication code (MAC) by using the encoding algorithm according to the intermediate calculation result, the remaining portions of the protected data and the authentication key. Each data programming operation programs a corresponding portion of the protected data and its associated metadata into a current block in a flash module. The metadata includes information to be used in a determination whether the protected data has been authenticated in a sudden power off recovery (SPOR) procedure.

Description

Method for writing and restoring protected data, computer program product and device

The present invention relates to a storage device, and more particularly to a method, a computer program product and a device for writing and restoring protected data.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pins and obtain the data stored at the address from the data pins of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not randomly accessed, but sequentially accessed. NAND flash memory cannot access any random address like NOR flash memory. Instead, the host side needs to write the value of the sequence of bytes into the NAND flash memory to define the type of request command (such as read, write, discard, erase, etc.) and the address used in this command. An address can point to a page (the smallest block of data that can be written to flash memory) or a block (the smallest block of data that can be erased from flash memory).

Before writing protected data to the flash memory module, the flash memory controller needs to check the security of the protected data. If the protected data received from the host does not pass the authentication, the flash memory controller cannot write the protected data.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related areas is indeed a problem to be solved.

The present specification relates to a method for writing and recovering protected data, which is executed by a processing unit and includes: receiving protected data indicated by a data write command from a host in multiple batches; and after using a coding algorithm to generate an intermediate calculation result based on a first portion of the protected data and an identification key, arranging multiple identification calculation operations for the remaining portion of the protected data and multiple data write operations for all portions of the protected data, so that the multiple identification calculation operations and the multiple data write operations can be executed partially in parallel.

A plurality of authentication calculation operations are used to calculate a message authentication code using the encoding algorithm based on the intermediate calculation results, the remaining portion of the protected data and the authentication key. Each data writing operation is used to write the corresponding portion of the protected data and its associated metadata to the current block in the flash memory module. The metadata includes information used in the instantaneous power failure recovery process to determine whether the protected data has passed the authentication.

The present specification also relates to a computer program product, comprising a program code. When a processing unit executes the program code, the method of writing and restoring protected data as described above is implemented.

The present specification also relates to a device for writing and restoring protected data, comprising: a host interface coupled to a host end; a flash memory interface coupled to a flash memory module; and a processing unit coupled to the host interface and the flash memory interface. The processing unit is configured to drive the host interface to receive protected data indicated by a data write command from the host end in multiple batches; and after using a coding algorithm to generate an intermediate calculation result based on the first portion of the protected data and an identification key, arrange multiple identification calculation operations for the remaining portion of the protected data and multiple data write operations for all portions of the protected data, so that the multiple identification calculation operations and the multiple data write operations can be partially executed in parallel.

One of the advantages of the above embodiment is that by providing information in the metadata that can be used in the instantaneous power failure recovery process to determine whether the protected data has passed the identification, the instantaneous power failure recovery process can refer to the metadata to discard the protected data that has been written to the flash memory module but has not passed the identification.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following will be used in conjunction with the accompanying drawings to illustrate embodiments of the present invention. In these drawings, the same reference numerals represent the same or similar components, steps or operations.

Several aspects and embodiments of the present disclosure are provided below. Some embodiments can be implemented independently, while some embodiments can be implemented in combination with one of ordinary skill in the art as would be easily conceived. The following description is for illustrative purposes only, and the specific details are provided to enable the various aspects of the present invention to be fully understood. However, it is apparent that these embodiments do not necessarily require such detailed and complete implementation. The accompanying drawings and descriptions are not intended to be limitations of the present invention.

The following descriptions are merely examples of various aspects and are not intended to limit the scope, applicable fields, or settings of the present disclosure. Instead, the examples of various aspects will provide descriptions that can be implemented by a person of ordinary skill in the art. It should be understood that the functions and arrangements of the components therein may be changed without violating the scope and spirit of the claims.

Referring to FIG. 1 , the electronic device 10 includes a host side 110, a flash memory controller 130, and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 may be collectively referred to as a device side. The electronic device 10 may be implemented in electronic products such as an external storage device, a personal computer, a laptop PC, a tablet computer, a mobile phone, a digital camera, a digital video camera, a smart TV, a smart refrigerator, and an automotive electronics system. The host end 110 and the host interface 131 of the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash interface 139 of the flash controller 130 and the flash module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR Toggle), or other communication protocols. The flash controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (e.g., a microcontroller unit, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and provides the functions described below when executing software and/or firmware instructions. The processing unit 134 receives host commands, such as a write command, a read command, a discard command, an erase command, etc., through the host interface 131, and schedules and executes these commands. The flash memory controller 130 further includes a random access memory (RAM) 136, which can be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination of the two, and is used to configure space as a data buffer to store user data (also referred to as host data) read from the host end 110 and to be written to the flash memory module 150, as well as user data read from the flash memory module 150 and to be output to the host end 110. The random access memory 136 can also store data required during the execution process, such as variables, data tables, data structures, host-address to flash-address mapping/H2F table, flash-address to host-address mapping/F2H table, etc. The flash memory interface 139 includes a NAND flash controller (NFC), which provides functions required for accessing the flash memory module 150, such as a command sequencer, a low density parity check (LDPC), etc.

The flash memory controller 130 may be configured with a bus architecture 132 for coupling components to transmit data, addresses, control signals, etc. These components include but are not limited to the host interface 131, the processing unit 134, the RAM 136, the flash memory interface 139, etc. The direct memory access (DMA) circuit in the component may transfer data between components through the bus architecture 132 according to instructions or control signals. For example, the DMA circuit in the host interface 131 or the flash memory interface 139 may move data in the data buffer therein to a specific address in the RAM 136, or move data at a specific address in the RAM 136 to a specific data buffer therein.

The flash memory module 150 provides a large amount of storage space, usually hundreds of Gigabytes (GB) or even several Terabytes (TB), for storing a large amount of user data, such as high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array, and the memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and reads user data from a specified address (source address) in the flash memory module 150. The flash memory interface 139 uses several electronic signals to coordinate the data and command transmission between the flash memory controller 130 and the flash memory module 150, including a data line, a clock signal, and a control signal. The data line can be used to transmit commands, addresses, read and write data; the control signal line can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).

2, the interface 151 in the flash memory module 150 may include four I/O channels (hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory cells, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell may be packaged as an independent chip (die). The flash memory interface 139 can enable NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by sending one of the enable signals CE#0 to CE#3 through the interface 151, and then read user data from the enabled NAND flash memory cells or write user data to the enabled NAND flash memory cells in parallel.

Refer to FIG. 3 for a partial hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may include a memory block 300, and the memory block 300 includes a plurality of memory cells, such as a floating gate transistor 310 or other charge trap devices. The structure of the memory block 300 includes a plurality of bit lines and a plurality of word lines. For simplicity, FIG. 3 only indicates the bit lines BL1 to BL3, and the word lines WL0 to WL5. For example, the floating gate transistors on the word lines WL0 to WL2 and WL3 to WL5 form different pages, respectively, to store data of two pages.

The host 110 allocates a continuous logical block address (LBA) to the protected data, and issues a special write command carrying the LBA to the flash memory controller 130 to instruct the flash memory controller 130 to write the protected data of the specified LBA into the flash memory module 150. The flash memory controller 130 can store the protected data in the flash memory module 150, such as replay protected memory block (RPMB) data, advanced replay protected memory block (Advanced RPMB) data, etc. Since the protected data is usually confidential or sensitive data, such as system information, key values used by the operating system, etc., the protected data received from the host 110 must be authenticated before being written into the flash memory module 150, or the protected data read from the flash memory module 150 must be authenticated before being returned to the host 110. Once authenticated, the flash memory controller 130 can write the protected data into the flash memory module 150 or return the read protected data to the host 110.

Taking Advanced RPMB as an example, the host 110 initially writes an authentication key into a designated area of the device, such as a One Time Programmable (OTP) area, which is 32 bytes long, so that the device can use a designated encoding algorithm (e.g., SHA128, SHA256, SHA512, etc.) and authentication key to verify protected data transmitted from the host 110 in the future.

The host 110 can use an Authenticated Data Write Command to write 64K or 128K bytes of protected data. For details, refer to the sequence diagram of data writing of the Advanced RPMB shown in Figure 4. The host 110 can send a Command UFS Protocol Information Unit (UPIU) 430 to the device 400, which includes an operation code of the security protocol output "SECURITY PROTOCOL OUT" and an Extra Header Segment (EHS) field. The request type in the EHS field is an Authenticated Data Write Request "0003h". The EHS field contains the LBAs of the 64K bytes of protected data. The EHS field also contains a 32-byte message authentication code (MAC) for the device 400 to verify the 64K bytes of RPMB data to be transmitted next. The MAC is generated by the host 110 based on the 64K bytes of protected data using a specified encoding algorithm (e.g., SHA128, SHA256, SHA512, etc.) and an authentication key. This authentication key is the same as the authentication key initially written into the device 400. After receiving this COMMAND UPIU 340 through the host interface 131, the device 400 is ready to start receiving protected data.

Once ready, the host 110 and the device 400 will work together to repeatedly execute a loop 450 to allow the device 400 to receive 64K bytes of protected data. In each iteration, the host interface 131 may send a Ready To Transfer UFS Protocol Information Unit (RTT UPIU) 451 to the host 110. Each time the host 110 receives the RTT UPIU 451, it transmits a DATA Out UFS Protocol Information Unit (UPIU) 455 to the device 400, so that the host interface 131 can receive the 4K bytes of protected data carried in the DATA Out UPIU 455 and store the received protected data in the data buffer therein.

Regardless of whether the device 400 successfully writes the 64K bytes of protected data into the flash memory module 150, after the device 400 receives the 64K bytes of protected data corresponding to the COMMAND UPIU 430, the host interface 131 transmits a response UFS Protocol Information Unit (UPIU) 470 to the host 110, which includes the EHS field. The message type in the EHS field is Authenticated Data Write Response "0300h".

In order to ensure the security of the 64K-byte protected data, in some embodiments, the processing unit 134 can execute computer instructions to implement a specified encoding algorithm (e.g., SHA128, SHA256, SHA512, etc.) to generate a MAC based on the received protected data and the authentication key in the OTP area. Then, the processing unit 134 determines whether the MAC carried in the COMMAND UPIU 430 is the same as the MAC calculated by the specified encoding algorithm. If the same, the processing unit 134 determines that the 64K-byte protected data has not been omitted or tampered with during the transmission process, and the sender is a legitimate source, and drives the flash memory interface 139 to write the protected data into the flash memory module 150. If they are not the same, the processing unit 134 does not allow the 64K-byte protected data to be successfully written into the flash memory module 150 .

Each physical block in the flash memory module 150 can be divided into a current block or a data block according to its function. The processing unit 134 can select an empty physical block in each NAND flash memory unit as a current block for preparing to write the protected data received from the host end 110. In order to improve the efficiency of data writing, the protected data provided by the host end 110 can be written to specific pages in multiple current blocks in multiple NAND flash memory units in parallel. The processing unit 134 can maintain a flash-host comparison table (F2H Table) for each current block in the RAM 136, which includes multiple records, storing information about which logical address the protected data or normal user data (Normal User Data) of each page in the current block is associated with in the order of page numbers. The logical address can be represented by a logical block address (Logical Block Address, LBA) or other methods and is managed by the host end 110. After all pages in a current block are full of data, or after the remaining pages in a current block are filled with false values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 into the specified page of the current block (for example, the last page), or the empty page in other specified physical blocks. When the corresponding F2H table has been written into the flash memory module 150, the current block is changed into a data block. In other words, the user data stored therein will no longer change. It should be noted that the current block across different NAND flash memory units can be called a super current block, and the specific page across different NAND flash memory units can be called a super page. However, to simplify the explanation, the current block referred to in the following paragraphs may represent one or more current blocks in a super current block spanning different NAND flash memory cells, and the physical page may represent one or more physical pages in a super page spanning different NAND flash memory cells.

Refer to FIG. 5 for a schematic diagram of writing protected data of some embodiments. The processing unit 134 drives the host interface 131 to obtain the protected data from the host end 110 at a time interval 510, and stores the protected data at a specified address of the RAM 136. Thereafter, at a time interval 520, the processing unit 134 uses a specified encoding algorithm to generate a MAC based on the obtained protected data and the authentication key. Next, the processing unit 134 compares the MAC sent from the host end 110 with the MAC calculated by the device end 400 at a time interval t _CMP . Only when the two are the same, the processing unit 134 drives the flash memory interface 139 to write the protected data into the flash memory module 150.

Assume that the processing unit 134 writes protected data to the flash memory module 150 using two input/output channels CH#0 and CH#1: the processing unit 134 drives the flash memory interface 139 to transmit part of the protected data (for example, the first part received in the time interval 510) to the flash memory module 150 using the input/output channel CH#0 in the time interval 531. After the time period 531, the processing unit 134 drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation, and the actual write operation requires a time period 542; and drives the flash memory interface 139 to transmit part of the protected data (such as the second part received in the time period 510) to the flash memory module 150 through the input and output channel CH#1 in the time period 551. After the time period 551, the processing unit 134 drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation, and the actual write operation requires a time period 562. After the time period 542, the processing unit 134 drives the flash memory interface 139 to transmit part of the protected data (e.g., the third part received in the time period 510) to the flash memory module 150 via the input/output channel CH#0 during the time period 533. After the time period 533, the processing unit 134 drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation, which requires a time period 544; and drives the flash memory interface 139 to transmit part of the protected data (e.g., the fourth part received in the time period 510) to the flash memory module 150 via the input/output channel CH#1 during the time period 553. After the time period 553, the processing unit 134 drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual writing operation, and the actual writing operation requires a time period 564.

In order to shorten the writing time of the protected data as described above, the embodiment of the present invention proposes a data writing method for allowing the calculation of MAC and the actual writing of protected data to be performed in parallel. Refer to the schematic diagram of the parallel execution of MAC calculation and protected data writing shown in Figure 6. The processing unit 134 drives the host interface 131 to obtain part of the protected data from the host end 110 in four batches, and stores the protected data in the specified address of the RAM 136. For example, the processing unit 134 drives the host interface 131 to obtain part of the protected data from the host end 110 in each of the time periods 611, 613, 615 and 617. After time interval 611, processing unit 134 generates an intermediate calculation result based on the obtained protected data and the authentication key using the specified encoding algorithm in time interval 622. After time interval 613 or 615, processing unit 134 updates the intermediate calculation result based on the newly obtained protected data, the previously generated intermediate calculation result and the authentication key using the specified encoding algorithm in time interval 624 or 626. After time interval 617, processing unit 134 generates a MAC based on the newly obtained protected data, the previously generated intermediate calculation result and the authentication key using the specified encoding algorithm in time interval 628. Next, the processing unit 134 compares the MAC sent from the host 110 and the MAC calculated by the device 400 during the time interval t _CMP . When the two are identical, the processing unit 134 drives the flash memory interface 139 to write the protected data into the flash memory module 150. For example, the processing unit 134 obtains 16K bytes of protected data through the host interface 131 during any of the time intervals 611, 613, 615, and 617. Once the physical layer (not shown) of the host interface 131 collects the 16K bytes of protected data from the host 110 and stores them in the data cache (not shown) of the host interface 131, the DMA circuit (not shown) of the host interface 131 stores the 16K bytes of protected data in the data cache to the specified address in the RAM 136 through the bus structure 132. The 16K bytes of protected data can be completely written into one physical page in the current block of the flash memory module 150. The entire 64K bytes of protected data can be written into four physical pages in the specified current block of the flash memory module 150. In order to shorten the writing time of the protected data, the processing unit 134 immediately starts to drive the flash memory interface 139 to transmit 16K bytes of protected data (that is, received in the time period 611) to the flash memory module 150 via the input and output channel CH#0 after the period 622 ends, and the actual transmission operation requires a time period 631. After the time period 631, the processing unit 134 immediately drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation, and the actual write operation requires a time period 642; and immediately drives the flash memory interface 139 to transmit 16K bytes of protected data (such as received in the time period 613) to the flash memory module 150 through the input and output channel CH#1, and the actual transmission operation requires a time period 651. After the time period 651, the processing unit 134 immediately drives the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation, and the actual write operation requires a time period 662. The operations of time intervals 633, 653, 644 and 664 are similar to the technical details of time intervals 533, 553, 544 and 564, respectively, and will not be elaborated for the sake of brevity.

However, if the 64K bytes of protected data are identified as illegal, but a sudden power off (SPO) occurs after at least one 16K bytes of protected data has been written into the physical page of the flash memory module 150, an unexpected error will occur. Because the identification result in the RAM 136 disappears due to the power off, some of the protected data that have been written into the physical page are mistakenly retained in the subsequent sudden power off recovery (SPOR) process, which endangers security. Although some technical shortcomings are described in the specification, this is only to illustrate the original inspiration of the invention embodiment described below. People skilled in the art may apply these technical solutions to solve other technical problems or apply them to other technical environments, and the present invention should not be limited thereby.

In order to solve or alleviate the defects of the above-mentioned embodiments, the processing unit 134 receives the protected data indicated by the data write command from the host end 110 through the host interface 131 in multiple batches; and after using the coding algorithm to generate an intermediate calculation result based on the first part of the protected data and the authentication key, arranges multiple authentication calculation operations for the remaining protected data and multiple data write operations for all the protected data, so that the multiple authentication calculation operations and the multiple data write operations can be partially executed in parallel. The multiple authentication calculation operations are used to calculate MAC based on the intermediate calculation result, the remaining protected data and the same authentication key using the same coding algorithm. Each data write operation is used to write the corresponding portion of protected data and its associated metadata to a physical page of the current block in the flash memory module 150 through the flash memory interface 139. The metadata contains information about whether the protected data has passed the authentication for future use in the SPOR process.

The embodiment of the present invention proposes a method for writing protected data as shown in FIG7 , and a method for reconstructing the corresponding protected data implemented in a SPOR procedure as shown in FIG8 . In addition to storing protected data, each physical page also reserves some space (e.g., 96 bytes) for the processing unit 134 to store metadata, cyclic redundancy check code (CRC) and error check and correction code (ECC). The metadata is used to describe the protected data in this physical page. The metadata may include four LBAs of the protected data, each LBA indicating the logical address of the protected data of 4K bytes. In order to ensure the security of the protected data of a data write command (e.g., an authentication data write command), the processing unit 134 may store the total number of written pages and the page index in the metadata of each physical page. In addition, the authentication result of the entire protected data is stored in the metadata of the last physical page. The CRC is generated based on the protected data and metadata stored in this physical page, and is used to check whether the corresponding protected data and metadata contain error bits. The ECC is also generated based on the protected data and metadata stored in this physical page, and is used to correct a limited number of error bits in the corresponding protected data and metadata. ECC can be Low-Density Parity Check Code (LDPC), BCH code (Bose–Chaudhuri–Hocquenghem Code), etc.

Referring to the flowchart of the method for writing protected data shown in FIG. 7 , the method is implemented by the processing unit 134 when loading and executing the code of the Firmware Translation Layer (FTL), and the details are as follows:

Step S710: Use a specified encoding algorithm to generate an intermediate calculation result based on the protected data in the header and the identification key.

Step S720: Set the variable i to 0. The processing unit 134 may use the variable i to record the page index of the protected data corresponding to the data write command.

Step S730: Store the LBAs, page index idx=i and write page count MAXpg of the i+1th portion of protected data in the metadata area of the RAM 136. The write page count MAXpg is set to indicate the total number of physical pages required for a data write command of the protected data.

Step S740: Determine whether the variable i is equal to the total number of written pages MAXpg minus 1. If so, it means that the physical page to be written in this iteration is the last physical page of this data write command (it can also mean that the data to be written in this iteration is related to the last part of the protected data), and the process continues to process step S762; otherwise, the process continues to process step S752.

Step S752: Drive the flash memory interface 139 to transmit the i+1th part of protected data, metadata, CRC and ECC to the flash memory module 150 via the specific input and output channels. It should be noted that the metadata transmitted in this step does not include the identification result of the entire protected data. In addition, after driving the flash memory interface 139, the processing unit 134 can jump to perform other tasks (for example, execute a specified encoding algorithm) without waiting for the actual transmission operation to be completed before executing other tasks.

Step S754: Drive the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation. It should be noted that after driving the flash memory interface 139, the processing unit 134 can immediately jump to perform other tasks (for example, execute a specified encoding algorithm) without waiting for the actual write operation to be completed before performing other tasks. After the write operation is completed, the processing unit 139 updates the mapping table (Mapping Table) temporarily stored in the RAM 136, which can also be called the host-flash memory mapping table (H2F Table), to modify the physical address corresponding to the LBAs of the protected data of the i-th part. The mapping table contains multiple records, which store the physical address corresponding to each LBA number from small to large according to the LBA number.

Step S756: Detect that the flash memory interface 139 and the flash memory module 150 are in an available state.

Step S758: Increase the variable i by 1.

Step S762: Store the identification result of the entire protected data into the metadata area in RAM 136.

Step S764: Drive the flash memory interface 139 to transmit the last portion of protected data, metadata, CRC and ECC to the flash memory module 150 via the specific input and output channels. It should be noted that after driving the flash memory interface 139, the processing unit 134 can jump to perform other tasks (e.g., execute a specified encoding algorithm) without waiting for the actual transmission operation to be completed before executing other tasks.

Step S766: Drive the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation. It should be noted that after driving the flash memory interface 139, the processing unit 134 can immediately jump to perform other tasks (e.g., execute a specified encoding algorithm) without waiting for the actual write operation to be completed before performing other tasks. After the write operation is completed, the processing unit 134 updates the lookup table temporarily stored in the RAM 136 to modify the physical address corresponding to the LBAs of the last portion of the protected data. After the processing unit 134 has updated the lookup table in the RAM 136 for the last portion of protected data, it does not necessarily drive the flash memory interface 139 to write the lookup table in the RAM 136 to the designated physical address in the flash memory module 150. Under normal circumstances, the processing unit 134 will drive the flash memory interface 139 to write the lookup table in the RAM 136 to the designated physical address in the flash memory module 150 only after the current block is fully written. It should be noted that when the lookup table in the RAM 136 is written to the designated physical address in the flash memory module 150, the protected data can be considered to be securely stored in the flash memory module 150.

6 , assuming that an identification data write command can instruct the flash memory controller 130 to write 64K bytes of protected data, and a physical page of the flash memory module 150 can store 4 LBAs (i.e., 16K bytes) of protected data: when executing the identification data write command, the flash memory controller 130 writes 64K bytes of protected data to the four physical pages of the designated current block of the flash memory module 150. In step S730, the index of the first physical page is 0, the index of the second physical page is 1, and so on. The total number of written pages MAXpg is set to 4.

The processing unit 134 executes step S710 in time interval 622. Next, for the first portion of protected data, the processing unit 134 executes steps S720, S730, S740, and S752 in sequence in time interval 631, and executes step S754 in time interval 642. Next, for the second portion of protected data, the processing unit 134 executes steps S756, S758, S730, S740, and S752 in sequence in time interval 651, and executes step S754 in time interval 662. Next, for the third portion of protected data, the processing unit 134 sequentially executes steps S756, S758, S730, S740, and S752 in time interval 633, and executes step S754 in time interval 644. Next, for the last portion of protected data, the processing unit 134 sequentially executes steps S756, S758, S730, S740, S762, and S764 in time interval 653, and executes step S766 in time interval 664. If the MAC sent by the host 110 and the MAC calculated by the device 400 are found to be the same during the time interval t _CMP , the metadata corresponding to the last portion of the protected data includes information that the identification is successful. Otherwise, the metadata corresponding to the last portion of the protected data includes information that the identification fails. The metadata corresponding to the last portion of the protected data may include a one-bit identification flag to indicate information on whether the identification is successful or failed.

In conjunction with the protected data writing method of FIG. 7 , refer to the flowchart of the protected data reconstruction method implemented in the SPOR program shown in FIG. 8 . This method is implemented by the processing unit 134 when loading and executing the FTL program code, and is described in detail as follows:

Step S810: Drive the flash memory interface 139 to read the lookup table of the protected data from the flash memory module 150, and store the lookup table to the designated address of the RAM 136.

Step S820: Find the last successfully written page (Last Success-programmed Page Before SPO) from the current block for storing protected data in the flash memory module 150. The processing unit 134 may start scanning forward from the last physical page in the current block for storing protected data in the flash memory module 150 to repeatedly read the protected data, metadata, CRC and ECC in a physical page until the last successfully written page before the power failure is found. For each iterative reading, the processing unit 134 checks whether the original protected data and metadata can pass the preliminary test using CRC. If they can pass the preliminary test, this physical page is the last successfully written page before the power failure. If the initial detection fails, the ECC is used to correct the error bits in the protected data and metadata to generate corrected protected data and metadata. Then, the processing unit 134 checks whether the corrected protected data and metadata can pass the re-detection using CRC. If the re-detection passes, this physical page is the last successfully written page before the instantaneous power failure. If the re-detection fails, this physical page is marked as an Uncorrectable ECC (UECC) page.

Step S830: Obtain the page index idx and the total number of written pages MAXpg from the metadata of the last successfully written page before the instantaneous power failure.

Step S840: Determine whether the page index idx is equal to the total number of written pages MAXpg minus 1. If yes, it means that the last successfully written page before the instantaneous power failure is the last physical page of a data write command, and the process continues to step S850; otherwise, the process continues to step S870.

Step S850: Determine whether the metadata contains information of successful identification. If yes, proceed to step S860; otherwise, the process continues to step S870.

Step S860: Update the lookup table in RAM 136. The processing unit 134 drives the flash memory interface 139 to read other physical pages of the data write command from the flash memory module 150. The lookup table in RAM 136 is updated according to the physical addresses of the last successfully written page and other physical pages stored in the flash memory module 150 before the instantaneous power failure and the LBAs in the metadata of the last successfully written page and other physical pages before the instantaneous power failure. Then, the flash memory interface 139 is driven to store the updated lookup table in RAM 136 to the specified address in the flash memory module 150 to reflect the status of the entire protected data that has been identified and written into the flash memory module 150 before the instantaneous power failure. In other words, after the updated lookup table is stored in the flash memory module 150, the protected data before the instantaneous power failure can be successfully restored.

Step S870: The comparison table in RAM 136 is not updated, so that the entire protected data that has not passed the identification cannot be successfully written into the flash memory module 150.

In other embodiments, the present invention also proposes a protected data writing method as shown in FIG9 , and a corresponding protected data reconstruction method implemented in a SPOR program as shown in FIG11 . Similarly, each physical page also reserves some space for the processing unit 134 to store metadata, CRC, and ECC. In order to ensure the security of the protected data of a data write command (e.g., an identification data write command), the processing unit 134 may store the total number of written pages and the page index in the metadata of each physical page, but will not store the identification result of the entire protected data in the metadata of the last physical page.

Referring to the flowchart of the method for writing protected data shown in FIG9 , the method is implemented by the processing unit 134 when loading and executing the FTL code. The technical details of steps S710, S720, S730, S752, S754, S756, S758, S764 and S766 in FIG9 are basically the same as those in FIG7 , and will not be repeated for the sake of brevity. The method shown in FIG9 does not execute step S762 in FIG7 . The technical details included in FIG9 that are different from those in FIG7 are described in detail as follows:

Step S910: Determine whether the variable i is equal to the total number of written pages MAXpg minus 1. If yes, it means that the physical page to be written in this iteration is the last physical page of this data write command (it can also mean that the data to be written in this iteration is related to the last part of the protected data), and the process continues to process step S920; otherwise, the process continues to process step S752.

Step S920: Determine whether the entire protected data is successfully identified. If yes, the process continues to process step S764; otherwise, the process ends and the last portion of the protected data is not written into the flash memory module 150.

The actual execution of the protected data writing method shown in FIG. 9 can also refer to FIG. 6, and the assumptions can refer to the description in the above paragraph. The steps executed by the processing unit 134 in time intervals 631, 642, 651, 662, 633 and 644 can refer to the description in the above paragraph, and will not be repeated for the sake of brevity. If the entire protected data passes the identification and is the last part of the protected data, the processing unit 134 executes steps S756, S758, S730, S910, S920 and S764 in time interval 653 in sequence, and executes step S766 in time interval 664. It should be noted that, since FIG. 9 does not execute step S762 as shown in FIG. 7 , the metadata associated with the last portion of the protected data written in step S766 does not contain information on the identification result.

If the entire protected data fails to pass the identification, the writing of the protected data can refer to the schematic diagram shown in Figure 10. Compared with Figure 6, Figure 10 lacks time periods 653 and 664.

In conjunction with the protected data writing method of FIG9 , refer to the flowchart of the protected data reconstruction method implemented in the SPOR program shown in FIG11 . The technical details of steps S810, S820, S830, S860 and S870 in FIG11 are basically the same as those in FIG8 , and will not be repeated for the sake of brevity. Since the metadata in the last entity page does not include the identification result, the method shown in FIG11 does not execute step S850 in FIG8 . The technical details included in FIG11 that are different from those in FIG8 are described in detail as follows:

Step S1110: Determine whether the page index idx is equal to the total number of written pages MAXpg minus 1. If yes, it means that the last successfully written page before the instantaneous power failure is the last physical page of a data write command (it may also mean that the data written by the last successfully written page before the instantaneous power failure is related to the last part of the protected data), and continue to process step S860; otherwise, the process continues to process step S870.

In other embodiments, the present invention also proposes a method for writing protected data as shown in FIG12. Similarly, each physical page also reserves some space for the processing unit 134 to store metadata, CRC, and ECC. However, the processing unit 134 does not store any information in the metadata for the security of the protected data.

Referring to the flowchart of the method for writing protected data shown in FIG12, the method is implemented by the processing unit 134 when loading and executing the FTL code. The technical details of steps S710, S720, S752, S754, S756, S758, S764 and S766 in FIG12 are basically the same as those in FIG7, and will not be repeated for the sake of simplicity. The method shown in FIG12 does not execute steps S730 and S762 in FIG7. The technical details included in FIG12 that are different from those in FIG7 are described in detail as follows:

Step S1210: Determine whether the variable i is equal to the total number of written pages MAXpg minus 1. If yes, it means that the physical page to be written in this iteration is the last physical page of this data write command (it can also mean that the data to be written in this iteration is related to the last part of the protected data), and the process continues to process step S764; otherwise, the process continues to process step S752.

Step S1220: After driving the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation of the last part of the protected data, it is determined whether the identification of the entire protected data is successful. If so, the process continues to process step S1230; otherwise, the process ends and the updated comparison table in the RAM 136 is not written to the flash memory module 150. It should be noted that if the updated comparison table is not written to the flash memory module 150, the flash memory module 150 only retains the previous version of the comparison table, resulting in that the protected data of this data write command cannot be read out even if it is written to the flash memory module 150.

Step S1230: Detect that the flash memory interface 139 and the flash memory module 150 are in an available state.

Step S1240: Drive the flash memory interface 139 to transfer the updated lookup table in the RAM 136 to the flash memory module 150 via a specific input/output channel. It should be noted that after driving the flash memory interface 139, the processing unit 134 can jump to perform other tasks immediately without waiting for the actual transfer operation to be completed before executing other tasks.

Step S1250: Drive the flash memory interface 139 to issue a command to the flash memory module 150 to start the actual write operation. It should be noted that after driving the flash memory interface 139, the processing unit 134 can jump to execute other tasks immediately without waiting for the actual write operation to complete before executing other tasks.

Refer to the schematic diagram of protected data writing shown in Figure 13. Assume that an identification data write command can instruct the flash memory controller 130 to write 64K bytes of protected data, and a physical page of the flash memory module 150 can store 4 LBAs (i.e., 16K bytes) of protected data: when executing the identification data write command, the flash memory controller 130 writes 64K bytes of protected data to the four physical pages of the designated current block of the flash memory module 150.

The operations performed by the processing unit 134 in time intervals 611, 613, 615, 617, 622, 624, 626 and 628 can be referred to the description in the above paragraphs, and will not be repeated for the sake of brevity. The processing unit 134 performs step S710 in time interval 622. Then, for the first portion of protected data, the processing unit 134 sequentially performs steps S720, S1210 and S752 in time interval 1331, and performs step S754 in time interval 1342. Next, for the second portion of protected data, the processing unit 134 sequentially executes steps S756, S758, S1210, and S752 in time interval 1351, and executes step S754 in time interval 1362. Next, for the third portion of protected data, the processing unit 134 sequentially executes steps S756, S758, S1210, and S752 in time interval 1333, and executes step S754 in time interval 1344. Next, for the last portion of protected data, the processing unit 134 sequentially executes steps S756, S758, S1210, and S764 in time interval 1353, and executes step S766 in time interval 1364. If the processing unit 134 finds in step S1220 that the MAC sent by the host end 110 and the MAC calculated by the device end 400 are the same, the processing unit 134 sequentially executes steps S1230 and S1240 in time interval 1335, and executes step S1250 in time interval 1346.

In conjunction with the protected data writing method of FIG. 12 , the SPOR procedure does not additionally implement a protected data reconstruction method for the protected data, because all valid records contained in the protected data comparison table of the flash memory module 150 will not be associated with the protected data that has not passed the authentication.

Although the present invention is illustrated and described herein with reference to specific embodiments, the present invention is not intended to be limited to the details shown. On the contrary, various modifications may be made to the details within the scope and equivalents of the claims without departing from the present invention. It should be understood that the above description is illustrative of the present invention and should not be interpreted as limiting the present invention. Various modifications, applications and/or combinations of the embodiments may be conceived by a person of ordinary skill in the art without departing from the scope of the present invention as defined by the claims.

It will be readily understood by those skilled in the art that the present invention discussed above can be implemented using different configurations of hardware components than those disclosed. Therefore, although the present invention has been described based on these preferred embodiments, certain modifications, variations, and alternative configurations are obvious to those skilled in the art and are also within the scope of the present invention.

It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, operation processes, elements and/or components, but do not exclude the addition of more technical features, numerical values, method steps, operation processes, elements, components, or any combination of the above.

The terms "first", "second", "third", etc. used in the claims are used to modify the elements in the claims, and are not used to indicate a priority order, a preceding relationship, or that one element precedes another element, or a temporal sequence in performing method steps. They are only used to distinguish elements with the same name.

It should be understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, and there may be intervening elements. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements may also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

The word "device" or "module" is not limited to one or a specific number of physical objects (e.g., a smart phone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some of the functions of the present invention in this disclosure. Although the description and examples use the word "device" or "module" to describe various aspects of the present disclosure, the word "device" or "module" is not limited to a specific configuration, type, or number of entities. In addition, the word "system" or "module" is not limited to multiple components or a specific direction. For example, a system can be implemented on one or more printed circuit boards or other substrates and can have movable or static components. Although the description and examples use the word "system" to describe various aspects of the invention in this disclosure, the word "system" is not limited to a specific configuration, type, or number of entities.

Specific details are provided in the above description to assist in a thorough understanding of various aspects of the invention. However, it will be understood by those skilled in the art that these aspects can be implemented without these specific details. In order to be able to explain clearly, in some examples, the present technology can be presented as including separate functional blocks, which include steps or subroutines embodied in methods of devices, device components, software, or a combination of hardware and software. Other additional components different from those shown in the figures and/or described herein can also be used. For example, circuits, systems, networks, processing and other components can be displayed as components in the form of block diagrams to avoid unnecessary details blurring these aspects. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring these aspects.

Some aspects may be described herein as processes or methods, which may be shown as flowcharts, data flow diagrams, structure diagrams, or block diagrams. Although a flowchart may describe the operations as a sequential process, multiple operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. The process terminates when the operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

All or part of the steps in the method described in the present invention can be implemented by computer instructions, such as the firmware translation layer (FTL) in the storage device, the driver of the specific hardware, etc. In addition, it can also be implemented in other types of programs. A person with ordinary knowledge in the relevant technical field can write the method of the embodiment of the present invention into computer instructions, and for the sake of brevity, it will not be described again. The computer instructions implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable medium, and can also be placed in a network server that can be accessed through a network (for example, the Internet, or other appropriate carriers).

Computer-readable storage media include volatile and non-volatile, removable and non-removable media that use any method or technology to implement the storage of information, such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include but are not limited to RAM, ROM, EEPROM, flash or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage, magnetic cards, tapes, disks or other magnetic storage, or other carriers that can be used to store information required and accessed by the instruction execution system. It should be noted that the computer-readable storage medium can be paper or other suitable medium for printing out the program code so that the program code can be obtained electronically, such as by optically scanning the paper or other medium, and then, if necessary, compiled, interpreted or processed by other appropriate methods, and then stored in the memory of the electronic device.

The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processors may be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in alternative embodiments, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors with a DSP core, or any other similar configuration. Accordingly, the term "processor," as used herein, may represent any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counting described herein.

The various illustrative logic blocks, modules, engines, circuits, and algorithmic steps described in conjunction with the invention disclosed herein may be implemented as electronic hardware, computer software, firmware, or any combination thereof. In order to clearly indicate the interchangeability of hardware and software, various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above according to their functions. Whether these functions are to be implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the entire system. A person of ordinary skill in the art may implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be interpreted as departing from the scope of this application.

Although FIG. 1 to FIG. 3 include the elements described above, it is not excluded that more additional elements may be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of FIG. 7 to FIG. 9 and FIG. 11 to FIG. 12 are executed in a specified sequence, a person skilled in the art may modify the sequence of these steps without violating the spirit of the invention, so the present invention is not limited to the sequence described above. In addition, a person skilled in the art may also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereto.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the present invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10: Electronic device 110: Host side 130: Flash memory controller 131: Host interface 132: Bus 134: Processing unit 136: Random access memory 139: Flash memory interface 150: Flash memory module 151: Interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: Channel CE#0~CE#3: Enable signal 300: Memory block 310: Floating gate transistor BL1~BL3: Bit line WL0~WL5: Word line 400: Device side 430: Command universal flash memory storage protocol information unit 450: Loop 451: Transfer ready universal flash memory storage protocol information unit 455: Data output universal flash memory storage protocol information unit 470: Reply universal flash memory storage protocol information unit 510,520,531,533,542,544,551,553,562,564: Time interval 611,613,615,617,622,624,626,628,631,633,642,644,651,653,662,664: Time interval S710~S766: Method steps S810~S870: Method steps S910~S920: Method steps S1110: Method steps S1210~S1250: Method steps 1331,1333,1335,1342,1344,1346,1351,1353,1362,1364: Time interval

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

FIG3 is a schematic diagram of a partial hardware architecture of a NAND flash memory unit according to an embodiment of the present invention.

FIG. 4 is a sequence diagram of data writing into an advanced replay protection memory block according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating independently performing Message Authentication Code (MAC) calculation and protected data writing according to some implementations.

FIG. 6 is a schematic diagram of MAC calculation and protected data writing performed in parallel according to an embodiment of the present invention.

FIG. 7 is a flow chart of a method for writing protected data according to an embodiment of the present invention.

FIG. 8 is a flow chart of a method for restoring protected data in a sudden power off recovery (SPOR) procedure adapted to FIG. 7 according to an embodiment of the present invention.

FIG. 9 is a flow chart of a method for writing protected data according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of MAC calculation and protected data writing performed in parallel according to an embodiment of the present invention.

FIG. 11 is a flow chart of a protected data reconstruction method adapted to FIG. 9 and implemented in a SPOR procedure according to an embodiment of the present invention.

FIG. 12 is a flow chart of a method for writing protected data according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating MAC calculation, protected data writing, and host-flash lookup table writing performed in parallel according to an embodiment of the present invention.

S710~S766: Method steps

Claims (15)

A method for writing and restoring protected data, executed by a processing unit, comprising: Receiving protected data indicated by a data write command from a host in multiple batches; and After using the coding algorithm to generate an intermediate calculation result based on the first part of the protected data and the authentication key, multiple authentication calculation operations for the remaining part of the protected data and multiple data writing operations for all parts of the protected data are arranged to allow the multiple authentication calculation operations and the multiple data writing operations to be partially executed in parallel, wherein the multiple authentication calculation operations are used to use the coding algorithm to calculate the first message authentication code based on the intermediate calculation result, the remaining part of the protected data and the authentication key, and each of the data writing operations is used to write the corresponding part of the protected data and its associated metadata to the current block in the flash memory module, The metadata includes information used in the instantaneous power failure recovery process to determine whether the protected data has passed the identification. A method for writing and restoring protected data as described in claim 1, wherein the data write command is a command universal flash memory storage protocol information unit, the command universal flash memory storage protocol information unit includes an operation code output by the security protocol and an additional header segment field, and the request type in the additional header segment field is an identification data write request. A method for writing and restoring protected data as described in claim 2, wherein the length of each portion of the protected data is 16K bytes. The method for writing and restoring protected data as described in claim 1 comprises: In the first metadata associated with the protected data that is not the last part, recording information that this is not the last part of the protected data; Writing the protected data that is not the last part and the first metadata associated with it into the current block in the flash memory module; When the first message identification code is the same as the second message identification code carried by the data write command, recording information that this is the last part of the protected data and information that the protected data has been successfully verified in the second metadata associated with the last part of the protected data; When the first message identification code is different from the second message identification code carried by the data write command, record information that this is the last part of the protected data and information that the protected data verification fails in the second metadata associated with the last part of the protected data; and write the last part of the protected data and the second metadata associated with it into the current block in the flash memory module. The method for writing and restoring protected data as described in claim 4 comprises: In the instantaneous power failure recovery procedure, finding the last successfully written page before the instantaneous power failure from the flash memory module; When the third metadata of the last successfully written page before the instantaneous power failure indicates that this is not the last part of the protected data, or indicates that this is the last part of the protected data and the identification result is failure, the host-flash memory comparison table of the protected data is not updated; and When the third metadata of the last successfully written page before the instantaneous power failure indicates that this is the last part of the protected data and the identification result is successful, according to the physical addresses of all physical pages of the protected data associated with the data write command stored in the flash memory module and the logical addresses recorded in the metadata of all physical pages associated with the data write command, the host-flash memory comparison table of the protected data is updated and the updated host-flash memory comparison table is written into the flash memory module to reflect the status of the protected data being written into the flash memory module before the instantaneous power failure. The method for writing and restoring protected data as described in claim 1 comprises: recording information that the protected data that is not the last part in the first metadata associated with the protected data that is not the last part; writing the protected data that is not the last part and the first metadata associated with it into the current block in the flash memory module; when the first message identification code is the same as the second message identification code carried by the data write command, writing the protected data of the last part and the second metadata associated with it into the current block in the flash memory module, wherein the second metadata includes information that this is the last part of the protected data; and When the first message identification code is different from the second message identification code carried by the data write command, the last portion of the protected data and the second metadata associated therewith are not written into the current block in the flash memory module. The method for writing and restoring protected data as described in claim 6 comprises: In the instantaneous power failure recovery procedure, finding the last successfully written page before the instantaneous power failure from the flash memory module; When the third metadata of the last successfully written page before the instantaneous power failure indicates that this is not the last part of the protected data, not updating the host-flash memory comparison table of the protected data; and When the third metadata of the last successfully written page before the instantaneous power failure indicates that this is the last part of the protected data, according to the physical addresses of all physical pages of the protected data associated with the data write command stored in the flash memory module and the logical addresses recorded in the metadata of all physical pages associated with the data write command, the host-flash memory comparison table of the protected data is updated and the updated host-flash memory comparison table is written into the flash memory module to reflect the status of the protected data being written into the flash memory module before the instantaneous power failure. A computer program product comprising program code, wherein when a processing unit executes the program code, a method of writing and restoring protected data as described in any one of claims 1 to 7 is implemented. A device for writing and restoring protected data, comprising: a host interface, coupled to a host end; a flash memory interface, coupled to a flash memory module; and a processing unit, coupled to the host interface and the flash memory interface, configured to drive the host interface to receive protected data indicated by a data write command from the host end in multiple batches; and after using a coding algorithm to generate an intermediate calculation result based on the protected data of the first part and an identification key, arranging multiple identification calculation operations for the remaining part of the protected data and multiple data write operations for all parts of the protected data, so as to allow The multiple authentication calculation operations and the multiple data writing operations can be partially executed in parallel, wherein the multiple authentication calculation operations are used to use the coding algorithm to calculate the first message authentication code according to the intermediate calculation result, the remaining part of the protected data and the authentication key, and each of the data writing operations is used to write the corresponding part of the protected data and its associated metadata to the current block in the flash memory module through the flash memory interface, wherein the metadata includes information used in the instantaneous power failure recovery procedure to determine whether the protected data has passed the authentication. A device for writing and restoring protected data as described in claim 9, wherein the data write command is a command universal flash memory storage protocol information unit, the command universal flash memory storage protocol information unit includes an operation code output by the security protocol and an additional header segment field, and the request type in the additional header segment field is an identification data write request. A device for writing and restoring protected data as described in claim 10, wherein the length of each portion of the protected data is 16K bytes. The apparatus for writing and restoring protected data as described in claim 9, wherein the processing unit is configured to record information that the protected data is not the last part in the first metadata associated with the protected data; drive the flash memory module to write the protected data that is not the last part and the first metadata associated with it into the current block in the flash memory module; when the first information When the identification code is the same as the second message identification code carried by the data write command, the information that this is the last part of the protected data and the information that the protected data has been successfully verified are recorded in the second metadata associated with the last part of the protected data; and the flash memory interface is driven to write the last part of the protected data and the second metadata associated with it into the current block in the flash memory module. The apparatus for writing and restoring protected data as described in claim 12, wherein the processing unit is configured to drive the flash memory interface to find the last successfully written page before the momentary power failure from the flash memory module in the momentary power failure recovery procedure; when the third metadata of the last successfully written page before the momentary power failure indicates that this is not the last part of the protected data, or indicates that this is the last part of the protected data and the identification result is failure, the host-flash memory comparison table of the protected data is not updated; and when the last successfully written page before the momentary power failure is When the third metadata of the page indicates that this is the last part of the protected data and the identification result is successful, the host-flash memory comparison table of the protected data is updated according to the physical addresses of all physical pages of the protected data associated with the data write command stored in the flash memory module and the logical addresses recorded in the metadata of all physical pages associated with the data write command, and the flash memory interface is driven to write the updated host-flash memory comparison table into the flash memory module to reflect the status of the protected data being written into the flash memory module before the instantaneous power failure. The apparatus for writing and restoring protected data as described in claim 9, wherein the processing unit is configured to record information that the protected data is not the last part in the first metadata associated with the protected data that is not the last part; drive the flash memory interface to write the protected data that is not the last part and the first metadata associated with it into the current block in the flash memory module; when the first message identification code is the same as the second message carried by the data write command When the first message identification code is different from the second message identification code carried by the data write command, the last part of the protected data and the second metadata associated therewith are not written into the current block in the flash memory module. The apparatus for writing and restoring protected data as described in claim 14, wherein the processing unit is configured to drive the flash memory interface to find the last successfully written page before the instantaneous power failure from the flash memory module during the instantaneous power failure recovery procedure; when the third metadata of the last successfully written page before the instantaneous power failure indicates that this is not the last part of the protected data, the host-flash memory comparison table of the protected data is not updated; and when the third metadata of the last successfully written page before the instantaneous power failure indicates that When this is the last part of the protected data, based on the physical addresses of all physical pages of the protected data associated with the data write command stored in the flash memory module and the logical addresses recorded in the metadata of all physical pages associated with the data write command, the host-flash memory comparison table of the protected data is updated and the flash memory interface is driven to write the updated host-flash memory comparison table into the flash memory module to reflect the status of the protected data being written into the flash memory module before the instantaneous power failure.

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