TWI873918B - 6t-sram device - Google Patents

Abstract

A six-transistor static random access memory （6T-SRAM） device includes a 6T-SRAM, a first chip and a second chip. The 6T-SRAM consists of the first group of transistors and the second group of transistors. The first group of transistors in the 6T-SRAM is disposed on a surface of the first chip, and the second group of transistors in the 6T-SRAM is disposed on a surface of the second chip. The second chip is face-to-face bonded to the first chip by hybrid bonding.

Description

Six-transistor SSRAM device

The present invention relates to a static random access memory (SRAM), and more particularly to a six-transistor static random access memory (6T-SRAM) device.

Static random access memory (SRAM) is a volatile memory cell. When the power supplied to the SRAM disappears, the stored data will be erased at the same time.

SRAM stores data by utilizing the conduction state of transistors in memory cells. The design of SRAM is based on cross-coupled transistors, which does not have the problem of capacitor discharge and does not require constant charging to keep data from being lost. In addition, the channel gate speed of SRAM is quite fast, so it can be used as cache memory in computer systems.

However, because SRAM basically uses six transistors and is also called six-transistor static random access memory (6T-SRAM), it requires a larger area compared to other types of memory.

The present invention provides a six-transistor static random access memory (6T-SRAM) device, which can significantly reduce the device area and prevent the latch-up effect from occurring.

The present invention also provides an integrated circuit stack structure, which has the above-mentioned 6T-SRAM device installed therein.

The six-transistor static random access memory device of the present invention includes a 6T-SRAM, a first chip and a second chip. The 6T-SRAM is composed of a first group of transistors and a second group of transistors. The second chip is face-to-face bonded to the first chip through heterojunction. The first group of transistors in the 6T-SRAM is arranged on the surface of the first chip, and the second group of transistors in the 6T-SRAM is arranged on the surface of the second chip.

In an embodiment of the present invention, the first group of transistors includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, and the second group of transistors includes a first channel gate transistor and a second channel gate transistor.

In one embodiment of the present invention, the first group of transistors share an active region of a rectangular frame.

In an embodiment of the present invention, the first group of transistors is a first pull-up transistor and a second pull-up transistor, and the second group of transistors is a first pull-down transistor, a second pull-down transistor, a first channel gate transistor, and a second channel gate transistor.

In one embodiment of the present invention, the first group of transistors are P-type metal oxide semiconductor (PMOS) transistors, and the second group of transistors are N-type metal oxide semiconductor (NMOS) transistors.

In one embodiment of the present invention, the above-mentioned 6T-SRAM device may further include at least one top metal layer disposed on the surface of the first chip or the surface of the second chip, and the top metal layer electrically connects a transistor in the first group of transistors and a transistor in the second group of transistors.

In one embodiment of the present invention, the 6T-SRAM device may further include at least one first top metal layer and at least one second top metal layer. The first top metal layer is disposed on the surface of the first chip and is electrically connected to a transistor in the first group of transistors. The second top metal layer is disposed on the surface of the second chip and is electrically connected to a transistor in the second group of transistors, and the first top metal layer and the second top metal layer are bonded together.

In an embodiment of the present invention, the first chip is a wafer or a die.

In one embodiment of the present invention, the second chip is a wafer or a die.

The integrated circuit stack structure of the present invention is composed of a plurality of stacked chips, wherein the 6T-SRAM device is disposed in the plurality of chips.

Based on the above, the present invention sets the six transistors in the 6T-SRAM in different chips and joins the two chips together by heterojunction, so that the cell size can be reduced to four transistors. When the six transistors in the 6T-SRAM are set in different chips according to NMOS and PMOS, since there will not be both N-type well and P-type well in the same chip, the latching effect can be prevented, and since there is no need to consider the latching effect, there is no need to increase the distance between the regions in the active area of the device, so that the cell size can be further reduced.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of an integrated circuit stacking structure according to a first embodiment of the present invention.

Referring to FIG. 1 , the integrated circuit stack structure 10 of the first embodiment is composed of a plurality of stacked chips C1, C2, C3, and C4, wherein a six-transistor static random access memory (6T-SRAM) device 100 is disposed in the chips C1 and C2. In other words, the 6T-SRAM device 100 of the present invention can be disposed in the existing integrated circuit stack structure 10, and only requires an area of four transistors (4T). The bonding between the chips C1 and C2 can be hybrid bonding, and the integrated circuit stack structure 10 can be manufactured using semiconductor chip packaging technologies such as die to die, die to wafer, or wafer to wafer. Various implementations of the 6T-SRAM device 100 will be described in detail below.

FIG. 2 is a schematic plan view of a six-transistor static random access memory (6T-SRAM) device according to a second embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , the 6T-SRAM device 100 basically includes a 6T-SRAM, a first chip C1, and a second chip C2, wherein the 6T-SRAM is composed of a first group of transistors T1 and a second group of transistors T2. The first chip C1 may be a wafer or a die, and the second chip C2 may also be a wafer or a die. The second chip C2 is face-to-face bonded to the first chip C1 by heterojunction, as shown in the cross-sectional view of FIG. 1 . FIG. 2 shows in a layout manner the first group of transistors T1 disposed on the surface 200a of the first chip C1 and the second group of transistors T2 disposed on the surface 200b of the second chip C2.

In the second embodiment, the first group of transistors T1 includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2, wherein the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 form a latch circuit so that data can be latched in the storage nodes SNL and SNR. The second group of transistors T2 includes a first pass gate transistor PG1 and a second pass gate transistor PG2. The first pass gate transistor PG1 and the second pass gate transistor PG2 serve as active loads.

Please continue to refer to Figure 2. The first pull-up transistor PU1 and the second pull-up transistor PU2 are P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are N-type metal oxide semiconductor (NMOS) transistors, so the first chip C1 has an N-type well area NW and a P-type well area PW1. The first group of transistors T1 share a rectangular active area 202, which spans the N-type well area NW and the P-type well area PW1. The source region of the first pull-up transistor PU1 and the source region of the second pull-up transistor PU2 may be electrically connected to a voltage source Vdd via a contact window 204, and the source region of the first pull-down transistor PD1 and the source region of the second pull-down transistor PD2 may be connected to a ground voltage source GND via another contact window 206. The first pull-up transistor PU1 and the first pull-down transistor PD1 may share a gate 208, and the second pull-up transistor PU2 and the second pull-down transistor PD2 may share a gate 210, but the present invention is not limited thereto; in another embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 may each have a gate and be electrically connected using an additional line; and so on.

In order to be able to mirror-dock with the first group of transistors T1 in the first chip C1, the layout of the second group of transistors T2 in the second chip C2 can be appropriately adjusted. For example, the first channel gate transistor PG1 is set at the upper left and the second channel gate transistor PG2 is set at the lower right. The first channel gate transistor PG1 and the second channel gate transistor PG2 are NMOS transistors, so the second chip C2 has a P-type well region PW2. The first channel gate transistor PG1 includes an active region 212 and a gate 214 spanning the active region 212, and the second channel gate transistor PG2 includes an active region 216 and a gate 218 spanning the active region 216, wherein the gate 214 and the gate 218 are electrically connected to the word line (WL). The gates 208, 210, 214, 218 can be polysilicon layers or other conductive material layers. The source region of the first pass gate transistor PG1 is electrically connected to the bit line BL, and the source region of the second pass gate transistor PG2 is electrically connected to another bit line BL'.

FIG3 shows a circuit diagram of a 6T-SRAM. Therefore, the drain region of the first pull-up transistor PU1 and the gate 210 of the second pull-up transistor PU2 in the first chip C1 can be electrically connected via a first connection structure 220, wherein the first connection structure 220 can include components such as contact windows and wires, and the shape and distribution of components can be adjusted as required, and are not limited to those shown in the figure. Similarly, the gate 208 of the first pull-up transistor PU1 and the drain region of the second pull-up transistor PU2 in the first chip C1 can be electrically connected via a second connection structure 222, wherein the second connection structure 222 can include components such as contact windows and wires, and the shape and distribution of components can be adjusted as required, and are not limited to those shown in the figure. The drain region of the first channel gate transistor PG1 in the second chip C2 can be electrically connected to the gate 210 of the second pull-up transistor PU2 and the drain region of the first pull-up transistor PU1 through the via VA1, the via VA4 on the first connection structure 220, and other electrical connection components (not shown). The drain region of the second channel gate transistor PG2 in the second chip C2 can be electrically connected to the drain region of the second pull-up transistor PU2 and the gate 208 of the first pull-up transistor PU1 through the via VA3, the via VA2 on the second connection structure 222, and other electrical connection components (not shown).

FIG. 4 is a schematic plan view of another example of the 6T-SRAM device of FIG. 3 , wherein a feasible bonding structure between the first chip C1 and the second chip C2 is further described.

4 , the 6T-SRAM device 100 may further include first top metal layers 400a and 400b and second top metal layers 402a and 402b. The first top metal layers 400a and 400b are disposed on the surface 200a of the first chip C1, and the second top metal layers 402a and 402b are disposed on the surface 200b of the second chip C2. The first top metal layer 400a contacts the via VA2, the first top metal layer 400b contacts the via VA4, and the first top metal layer 400a and the first top metal layer 400b are electrically insulated. The second top metal layer 402a contacts the via VA1, the second top metal layer 402b contacts the via VA3, and the second top metal layer 402a is electrically insulated from the second top metal layer 402b. The second chip C2 is face-to-face bonded to the first chip C1 by heterogeneous bonding, so that the first top metal layer 400a is bonded to the second top metal layer 402b, and the first top metal layer 400b is bonded to the second top metal layer 402a.

In FIG4 , the first top metal layer 400a can be electrically connected to the gate of the first pull-up transistor PU1 in the first group of transistors T1 through the via VA2. The first top metal layer 400b can be electrically connected to the gate of the second pull-up transistor PU2 in the first group of transistors T1 through the via VA4. The second top metal layer 402a can be electrically connected to the drain region of at least one transistor in the second group of transistors T2 (such as the drain region of the first pass gate transistor PG1) through the via VA1. The second top metal layer 402b may be electrically connected to the drain region of at least one transistor in the second group of transistors T2 (eg, the drain region of the second pass gate transistor PG2) through the via VA3.

In addition to the above-mentioned embodiments, the second top metal layer 402a and the second top metal layer 402b may be omitted, so that the first top metal layer 400a is directly bonded to the via window VA3, and the first top metal layer 400b is directly bonded to the via window VA1. In another embodiment, the first top metal layer 400a and the first top metal layer 400b may be omitted, and the second top metal layer 402a is directly bonded to the via window VA4, and the second top metal layer 402b is directly bonded to the via window VA2. That is, by disposing a top metal layer on the surface 200a of the first chip C1 or on the surface 200b of the second chip C2, one transistor in the first group of transistors T1 and one transistor in the second group of transistors T2 can be electrically connected.

FIG5 is a schematic plan view of a 6T-SRAM device according to the third embodiment of the present invention, wherein the same element symbols as those in the second embodiment are used to represent the same or similar parts and components, and the relevant contents of the same or similar parts and components can also refer to the contents of the second embodiment and will not be repeated here.

5 , the 6T-SRAM device 500 is the same as the second embodiment, and has a 6T-SRAM, a first chip C1, and a second chip C2, wherein the 6T-SRAM is composed of a first group of transistors T1 and a second group of transistors T2. However, the first group of transistors T1 of the 6T-SRAM device 500 is a first pull-up transistor PU1 and a second pull-up transistor PU2, and the second group of transistors T2 is a first pull-down transistor PD1, a second pull-down transistor PD2, a first channel gate transistor PG1, and a second channel gate transistor PG2. In this embodiment, the first group of transistors T1 is a PMOS transistor, and the second group of transistors T2 is an NMOS transistor, so the first chip C1 has an N-type well region NW, and the second chip C2 has a P-type well region PW. Since the same chip does not have both an N-type well region and a P-type well region, the structure of this embodiment can prevent the latching effect, and since there is no need to consider the latching effect, the device can be made more compact.

In the first chip C1 of FIG. 5 , the first pull-up transistor PU1 has an active region 502, and the second pull-up transistor PU2 has an active region 504, and the active region 502 and the active region 504 have different shapes and are separated from each other. The source region of the first pull-up transistor PU1 and the source region of the second pull-up transistor PU2 can be electrically connected to the voltage source Vdd via the contact window 506 and the contact window 508. The gate 510 of the first pull-up transistor PU1 and the drain region of the second pull-up transistor PU2 can be electrically connected via the third connection structure 512, wherein the third connection structure 512 can include components such as contact windows and wires, and its shape and distribution of components can be adjusted according to needs, and are not limited to those shown in the figure. Furthermore, in order to be able to mirror-connect with the second group of transistors T2 in the second chip C2, the connection point CP1 can be set to connect to the drain region of the first pull-up transistor PU1, the connection point CP2 can be set to connect to the gate 510 of the first pull-up transistor PU1, the connection point CP3 can be set to connect to the gate 514 of the second pull-up transistor PU2, and the connection point CP4 can be set to connect to the drain region of the second pull-up transistor PU2, wherein the connection points CP1-CP4 are, for example, metal pads. A connection component such as a contact window or a conductive layer can also be set between the connection points CP1-CP4 and the structure below them, and can be adjusted according to needs, not limited to what is shown in FIG. 5.

In the second chip C2 of FIG. 5 , the second channel gate transistor PG2 and the first pull-down transistor PD1 may share an active region 516, and the first channel gate transistor PG1 and the second pull-down transistor PD2 may share an active region 518, wherein the active region 516 is separated from the active region 518. The source region of the first pull-down transistor PD1 and the source region of the second pull-down transistor PD2 may be connected to the ground voltage source GND via the contact window 520 and the contact window 522. The first channel gate transistor PG1 includes a gate 524 across the active region 516, and the second channel gate transistor PG2 includes a gate 526 across the active region 518, wherein the gate 524 and the gate 526 are electrically connected to the word line (WL). The source region of the first channel gate transistor PG1 is electrically connected to the bit line BL, and the source region of the second channel gate transistor PG2 is electrically connected to another bit line BL'. The gate 528 of the second pull-down transistor PD2 and the drain region of the second pass gate transistor PG2 can be electrically connected via a fourth connection structure 530, wherein the fourth connection structure 530 can include components such as contact windows and wires, and its shape and distribution of components can be adjusted as required and are not limited to those shown in the figure.

Furthermore, in order to be able to be mirror-connected with the first group of transistors T1 in the first chip C1, a connection point CP5 may be set on the surface 200b of the second chip C2 to connect to the source region of the first pull-down transistor PD1, a connection point CP6 may be set to connect to the gate 532 of the first pull-down transistor PD1, a connection point CP7 may be set to connect to the gate 528 of the second pull-down transistor PD2, and a connection point CP8 may be set to connect to the drain region of the second pull-down transistor PD2, wherein the connection points CP5-CP8 are, for example, metal pads. A contact window or a conductive layer or other components may also be set between the connection points CP5-CP8 and the structure below them, and may be adjusted according to needs, and is not limited to that shown in FIG. 5 .

After the first chip C1 and the second chip C2 of FIG. 5 are mirror-joined, the connection point CP1 is joined to the connection point CP5, the connection point CP2 is joined to the connection point CP6, the connection point CP3 is joined to the connection point CP7, and the connection point CP4 is joined to the connection point CP8. Moreover, the joined 6T-SRAM device 500 can also be set in the integrated circuit stack structure 10 of FIG. 1, replacing the 6T-SRAM device 100 therein.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10: Integrated circuit stacking structure 100, 500: 6T-SRAM device 200a, 200b: Surface 202, 212, 216, 502, 504, 516, 518: Active area 204, 206, 506, 508, 520, 522: Contact window 208, 210, 214, 218, 510, 514, 524, 526, 528, 532: Gate 220: First connection structure 222: Second connection structure 400a, 400b: First top metal layer 402a, 402b: Second top metal layer 512: Third connection structure 530: Fourth connection structure 6T-SRAM: Six-transistor static random access memory BL, BL’: Bit lines C1: First chip C2: Second chip C3, C4: Chips CP1, CP2, CP3, CP4, CP5, CP6, CP7, CP8: Connection points GND: Ground voltage source NW: N-type well area PD1: First pull-down transistor PD2: Second pull-down transistor PG1: First channel gate transistor PG2: Second channel gate transistor PU1: First pull-up transistor PU2: Second pull-up transistor PW, PW1, PW2: P-type well area SNL, SNR: Storage nodes T1: First group of transistors T2: Second group of transistors VA1, VA2, VA3, VA4: interlayer window Vdd: voltage source

FIG. 1 is a cross-sectional schematic diagram of an integrated circuit stack structure according to the first embodiment of the present invention. FIG. 2 is a plan schematic diagram of a six-transistor static random access memory (6T-SRAM) device according to the second embodiment of the present invention. FIG. 3 is a circuit diagram of a 6T-SRAM. FIG. 4 is a plan schematic diagram of another example of the 6T-SRAM device of FIG. 3. FIG. 5 is a plan schematic diagram of a 6T-SRAM device according to the third embodiment of the present invention.

100:6T-SRAM device

200a, 200b: surface

202, 212, 216: Active zone

204, 206: Contact window

208, 210, 214, 218: Gate

220: First connection structure

222: Second connection structure

6T-SRAM: Six-transistor static random access memory

BL, BL’: bit line

C1: First chip

C2: Second chip

GND: Ground voltage source

NW: N-type well area

PD1: First pull-down transistor

PD2: Second pull-down transistor

PG1: First channel gate transistor

PG2: Second channel gate transistor

PU1: First pull-up transistor

PU2: Second pull-up transistor

PW1, PW2: P-type well area

SNL, SNR: storage nodes

T1: The first set of transistors

T2: The second set of transistors

VA1, VA2, VA3, VA4: interlayer window

Vdd: voltage source

Claims (6)

A six-transistor static random access memory (6T-SRAM) device includes: a 6T-SRAM, which is composed of a first group of transistors and a second group of transistors; a first chip; and a second chip, which is face-to-face bonded to the first chip through heterojunction, wherein the first group of transistors in the 6T-SRAM is arranged on the surface of the first chip, and the second group of transistors in the 6T-SRAM is arranged on the surface of the second chip, wherein the first group of transistors is a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor, and the second group of transistors is a first channel gate transistor and a second channel gate transistor. A six-transistor static random access memory device as described in claim 1, wherein the first group of transistors share an active area of a rectangular frame. The six-transistor static random access memory device as described in claim 1 further includes at least one top metal layer disposed on the surface of the first chip or the surface of the second chip, and the at least one top metal layer electrically connects at least one transistor in the first group of transistors and at least one transistor in the second group of transistors. The six-transistor static random access memory device as described in claim 1 further includes: at least one first top metal layer, disposed on the surface of the first chip, and electrically connected to at least one transistor in the first group of transistors; and at least one second top metal layer, disposed on the surface of the second chip, and electrically connected to at least one transistor in the second group of transistors, and the first top metal layer and the second top metal layer are bonded together. A six-transistor static random access memory device as described in claim 1, wherein the first chip is a wafer or a die, and the second chip is a wafer or a die. An integrated circuit stack structure is composed of a plurality of stacked chips, wherein a six-transistor static random access memory device as described in any one of claims 1 to 5 is provided in the plurality of chips.

Images