TWI870124B - Memory device and reading method thereof - Google Patents

Abstract

A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; when applying the pass voltage to the first word line, applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line, when the second read voltage is applied to the first word line.

Description

Memory device and reading method thereof

The present disclosure relates to an electronic component and an operating method thereof, and more particularly to a memory device and a reading method thereof.

With the development of memory, various memory types are constantly being introduced. Memory can be used to store various digital data and has been widely used in various electronic devices. However, due to its physical characteristics, some memories will have a critical voltage shift after long-term storage, which will cause data reading errors. Therefore, various technologies are needed to reduce the data reading error rate.

In order to reduce the data read error rate, an error correction technology (Error-correcting codes) has been developed. However, error correction technology requires additional error correction operation circuits to check and correct data. Error correction operation circuits will occupy a considerable area, seriously affecting the goal of miniaturization of electronic components. In addition, error correction operations will also increase the memory read delay time, seriously affecting the memory read speed. Furthermore, too many error correction operations will also reduce the life of the memory. Therefore, researchers are working hard to develop innovative technologies to reduce data read error rates.

At least one embodiment of the present disclosure is related to a memory device and a reading method thereof. After a control circuit reads a memory cell of the memory device, if a read error occurs in a memory cell on a selected word line, the control circuit identifies the voltage level of the read voltage and determines whether the read error occurs in a high level state group or a low level group. After determining whether the read error occurs in a high level state group or a low level group, the critical voltage distribution curve of the memory cell of a specific critical group can be evaluated as shifting toward a higher critical voltage or shifting toward a lower critical voltage. Afterwards, the control circuit identifies the neighboring data patterns (i.e., high neighboring critical voltage group or low neighboring critical voltage group) of the memory cells of the selected (or failed) word line. Then, the control circuit performs a re-reading process on some memory cells of the selected word line to improve the reading efficiency and enhance the reading accuracy.

According to an embodiment of the present disclosure, a method for reading a memory device is provided. The memory device includes at least a first word line, a second word line, and a third word line. The second word line and the third word line are adjacent to the first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. In response to a read error occurring in at least one of these memory cells, an identification procedure is executed. A reread procedure is executed on the memory cells. The reading procedure includes: applying a first read voltage to the first word line; and applying a first conduction voltage to the second word line and the third word line when the first read voltage is applied to the first word line. The identification process includes: applying a first conduction voltage to the first word line; when the first conduction voltage is applied to the first word line, applying an identification voltage to at least one of the second word line and the third word line. The rereading process includes: applying a second read voltage to the first word line; when the second read voltage is applied to the first word line, applying a second conduction voltage to the second word line and a third conduction voltage to the third word line.

According to another embodiment of the present disclosure, a memory device is provided. The memory device includes at least a first word line, a second word line, a third word line and a control circuit. The second word line and the third word line are adjacent to the first word line. The control circuit is used to execute a read procedure to read a plurality of memory cells of the first word line. The control circuit also executes an identification procedure in response to a read error in at least one of the memory cells. The control circuit also executes a reread procedure on the memory cells. In a read process, the control circuit is used to apply a first read voltage to the first word line; when the first read voltage is applied to the first word line, the control circuit is used to apply a first conduction voltage to the second word line and the third word line. In an identification process, the control circuit is used to apply a first conduction voltage to the first word line; when the first conduction voltage is applied to the first word line, the control circuit is used to apply an identification voltage to at least one of the second word line and the third word line. In a reread process, the control circuit is used to apply a second read voltage to the first word line; when the second read voltage is applied to the first word line, the control circuit is used to apply a second conduction voltage to the second word line and a third conduction voltage to the third word line.

In order to better understand the above and other aspects of the present disclosure, the following is a detailed description of the embodiments with accompanying drawings as follows:

Please refer to FIG. 1, which shows a schematic diagram of a memory device 100 according to an embodiment. The memory device 100 is, for example, a NAND flash memory. The memory device 100 includes a plurality of bit lines BLi, a plurality of word lines WLi, a row decoding circuit 110, a column decoding circuit 120, and a control circuit 130. The word lines WLi include a first word line WL1, a second word line WL2, and a third word line WL3 that are adjacent to each other. The second word line WL2 and the third word line WL3 are adjacent to the first word line WL1 and are located on both sides of the first word line WL1.

The row decoding circuit 110 is connected to the bit line BLi. The column decoding circuit 120 is connected to the word line WLi. The control circuit 130 is connected to the row decoding circuit 110 and the column decoding circuit 120. The control circuit 130 is used to control the voltage input to the bit line BLi and the word line WLi to execute an erase procedure, a programming procedure, or a read procedure. In at least one example, the memory device 100 includes a plurality of memory strings, each memory string including a plurality of memory cells connected in series. The plurality of memory cells in the same memory string are respectively connected to different word lines (for example, a first word line WL1, a second word line WL2, and a third word line WL3). In the same row, memory cells of different memory strings are connected to the same word line (eg, the first word line WL1 in FIG. 1 ).

Please refer to FIG. 2, which shows the critical voltage distribution curve of the memory cell of the selected word line (such as the first word line WL1 in FIG. 1) according to an embodiment. Taking a triple level cell (TLC) storing 3 bits of data as an example, the memory cell has 8 states, namely, an erase state E, a first programming state P1, a second programming state P2, a third programming state P3, a fourth programming state P4, a fifth programming state P5, a sixth programming state P6 and a seventh programming state P7. The critical voltages of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6 and the seventh programming state P7 increase in sequence. In one embodiment, the erase state E and the first programming state P1 can be classified into a low-level state group G_L. The second programming state P2, the third programming state P3, the fourth programming state P4 and the fifth programming state P5 can be classified into a middle-level state group G_M. The sixth programming state P6 and the seventh programming state P7 can be classified into a high-level state group G_H.

In another embodiment, the erase state E, the first programming state P1 and the second programming state P2 can be classified into a low-level state group G_L. The third programming state P3 and the fourth programming state P4 can be classified into a middle-level state group G_M. The fifth programming state P5, the sixth programming state P6 and the seventh programming state P7 can be classified into a high-level state group G_H.

In another embodiment, multi-level memory cells (MLCs) can be used to store 2-bit data and have four states: an erase state, a first programming state, a second programming state, and a third programming state. The critical voltages of the erase state, the first programming state, the second programming state, and the third programming state increase in sequence. The erase state can be summarized as a low-level state group G_L. The first programming state and the second programming state can be summarized as a middle-level state group G_M. The third programming state can be summarized as a high-level state group G_H.

In another embodiment, a quad-level cell (QLC) can be used to store 4-bit data and has 16 states, including an erase state, a first programming state, a second programming state, a third programming state, a fourth programming state, a fifth programming state, a sixth programming state, a seventh programming state, an eighth programming state, a ninth programming state, a tenth programming state, an eleventh programming state, a twelfth programming state, a thirteenth programming state, a fourteenth programming state, and a fifteenth programming state. The critical voltages of the erase state, the first programming state, the second programming state to the fifteenth programming state increase in sequence. The erase state, the first programming state to the fourth programming state can be summarized as a low-level state group G_L. The fifth programming state to the tenth programming state can be summarized as a medium-level state group G_M. The eleventh programming state to the fifteenth programming state can be summarized as a high-level state group G_H.

The number of bits in a memory cell is not a limitation of the present technology. In another embodiment, a memory cell may have various numbers of erase/program states.

As shown in FIG. 2, when the memory cell on the selected word line (such as the first word line WL1 shown in FIG. 1) has just been programmed, the critical voltage distribution curves of the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6 and the seventh programming state P7 are respectively located in the eight intervals divided by the read voltages Vread01, Vread12, Vread23, Vread34, Vread45, Vread56 and Vread67. Therefore, in the read process, the correct data can be read using the read voltages Vread01, Vread12, Vread23, Vread34, Vread45, Vread56 and Vread67. The erase state E, or the first programming state P1 to the seventh programming state P7 are memory states (level states).

However, after long-term use, after a period of retention, or after being affected by neighboring memory cells, the memory cell will experience a critical voltage shift. The critical voltage shift includes a low critical voltage shift of the high-level state group G_H and a high critical voltage shift of the low-level state group G_L.

Figure 3 illustrates the critical voltage distribution curve of the high-level state group G_H (such as the sixth programming state P6 and the seventh programming state P7). Just after programming, the critical voltage distribution curve is shown as the solid line C0. The memory cells in the sixth programming state P6 and the seventh programming state P7 can be distinguished by applying the read voltage Vread67. After being maintained for a period of time after programming, the critical voltage distribution curve (as shown by the dotted line C1) will become wider and shift toward a lower critical voltage. The memory cells in the sixth programming state P6 and the seventh programming state P7 can no longer be distinguished by applying the read voltage Vread67. Since the sixth programming state P6 and the seventh programming state P7 partially overlap, a read error may occur. Some memory cells of the seventh programming state P7 of the dotted line C1 may be identified as an error state (sixth programming state P6). Some memory cells of the sixth programming state P6 of the dotted line C1 may be identified as an error state (seventh programming state P7).

Figure 4 illustrates the critical voltage distribution curve of the low-level state group G_L (such as the erase state E and the first programming state P1). Just after programming, the critical voltage distribution curve is shown as the solid line C0'. The memory cells in the erase state E and the first programming state P1 can be distinguished by applying the read voltage Vread01. After programming and maintaining it for a period of time, the critical voltage distribution curve (as shown by the dotted line C1') will become wider and shift toward a higher critical voltage. The memory cells in the erase state E and the first programming state P1 can no longer be distinguished well by applying the read voltage Vread01. Since the erase state E and the first programming state P1 partially overlap, a read error may occur. Some memory cells in the erase state E of the dashed line C1' may be identified as an error state (first programming state P1). Some memory cells in the first programming state P1 of the dashed line C1 may be identified as an error state (erased state E).

In one embodiment, the control circuit 130 reads the memory cells of the selected word line (such as the first word line WL1) of the memory device 100. If a read error occurs, the control circuit 130 can identify that the read error occurs in the high-level state group G_H or the low-level state group G_L. The critical voltage deviation direction of the critical voltage distribution curve of the memory cells of the selected word line (such as the first word line WL1) can be determined. Then, the control circuit 130 executes a recognition procedure of the adjacent data state of the selected word line (such as the first word line WL1). Then, the control circuit 130 executes a reread process on the memory cells of the selected word line (such as the first word line WL1) to reduce the reading error range and increase the reading accuracy.

Please refer to FIG. 5 , which shows a flow chart of a method for reading a memory device 100 according to an embodiment. The method for reading a memory device 100 according to this embodiment includes a reading procedure PD11 , a recognition procedure PD12 , and a re-reading procedure PD13 .

The read program PD11 is used to read the memory cells of the first word line WL1 (i.e., the selected word line). The memory cells connected to the first word line WL1 may have read errors. The read error or failure represents that the number of error bits of the memory cell exceeds a predetermined value of a specific programming state. The read error can be identified as occurring in the high-level state group G_H or the low-level state group G_L. The critical voltage deviation direction of the critical voltage distribution curve of the memory cell of the selected first word line WL1 can be determined. When identifying the level state group, the read voltage can be used to identify the high level state group G_H or the low level state group G_L. For example, if the read voltage Vread67 is applied to read the memory cells of the sixth programming state P6 and the seventh programming state P7, a read error occurs. The read voltage Vread67 can be used to identify that the read error occurs in the high level state group G_H. After programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1 in Figure 3) will become wider and shift toward a lower critical voltage. The identification process PD12 is used to identify the neighboring data patterns of the selected first word line WL1. The rereading process PD13 is used to reread some memory cells (ie, error memory cells) of the first word line WL1.

The read procedure PD11 includes steps S110 to S120. Please refer to FIG. 6, which illustrates an example of the read procedure PD11. Here, the first word line WL1, the second word line WL2, and the third word line WL3 of the word line WLi in FIG. 1 are used as an example for explanation. In step S110 of the read procedure PD11, the control circuit 130 applies a first read voltage Vread1 to the first word line WL1. The first read voltage Vread1 is, for example, the read voltages Vread01, Vread12, Vread23, Vread34, Vread45, Vread56, and Vread67 used in the aforementioned different memory cell states.

Next, in step S120 of the read procedure PD11, the control circuit 130 applies a first conduction voltage Vpass1 to the second word line WL2 and the third word line WL3. Steps S110 and S120 of the read procedure PD11 are executed simultaneously. In the read procedure PD11, the second word line WL2 and the third word line WL3 are applied with the same first conduction voltage Vpass1 to conduct the memory cells connected to the second word line WL2 and the third word line WL3.

In the reading process PD11, as long as the memory cell does not have a critical voltage offset phenomenon, the correct data content can be read out. However, after a long period of use, a memory cell is retained for a period of time, or is affected by adjacent memory cells, a critical voltage offset phenomenon may occur.

As shown in FIG. 1 mentioned above, the memory device 100 includes several memory strings, each of which includes several memory cells connected in series. Several memory cells in the same memory string are respectively connected to different word lines (for example, the first word line WL1, the second word line WL2, and the third word line WL3). In the same row, memory cells in different memory strings are connected to the same word line (for example, the first word line WL1 in FIG. 1). To simplify the following description, FIGS. 6, 7, 8, 10, 11, 14, 16, 18, 20, 23, and 24 only illustrate three memory cells connected in series. These three memory cells are respectively connected to the second word line WL2, the first word line WL1, and the third word line WL3.

As described in the previous paragraph, after programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1 in FIG. 3) of the selected word line (such as the first word line WL1) will become wider and the distribution curves (as shown by the dotted lines in FIG. 3) of the adjacent programming states (such as the sixth programming state P6 and the seventh programming state P7 in FIG. 3) will partially overlap. As shown in FIG. 6, researchers have found that in an embodiment of the sixth programming state P6 and the seventh programming state P7, the critical voltage distribution curve (dotted line C1) will be formed by the adjacent low voltage group curve Cnlg in FIG. 6 and the adjacent high voltage group curve Cnhg in FIG. 7. In FIG. 6, a memory string includes three serially connected memory cells. These memory cells are respectively connected to the second word line WL2, the first word line WL1 and the third word line WL3. The neighboring low voltage group curve Cnlg corresponds to the memory cells of the selected word line (the first word line WL1) having neighboring data patterns such as "LXL", "LXM" or "MXL". The above "L" represents the low-level state group G_L, the above "M" represents the middle-level state group G_M, the above "H" represents the high-level state group G_H, and the above "X" represents any-level state group. "LXL" means that the memory cells of the second word line WL2, the first word line WL1, and the third word line WL3 are respectively located in the "low-level state group G_L, any-level state group, low-level state group G_L". "LXM", "MXL" and so on. The identification of neighbor data patterns will be introduced in the identification procedure PD12 later.

Please refer to FIG. 7, which illustrates another example of the read program PD11. Similarly, in an embodiment of the sixth programming state P6 and the seventh programming state P7, the neighboring high voltage group curve Cnhg is shown in FIG. 7. In FIG. 7, a memory string includes three memory cells connected in series. These memory cells are respectively connected to the second word line WL2, the first word line WL1, and the third word line WL3. The neighboring high voltage group curve Cnhg corresponds to the memory cell of the selected word line (the first word line WL1) having neighboring data patterns such as "HXH", "LXH", "HXL", "HXM", or "MXH". The critical voltage distribution curve (dashed line C1), the neighboring low voltage group curve Cnlg and the neighboring high voltage group curve Cnhg shown in FIGS. 6 and 7 can be applied to select any two adjacent programming states of the word line, and the present disclosure is not limited to the sixth programming state P6 and the seventh programming state P7.

In step S130, the control circuit 130 determines whether a read error occurs. A read error or failure represents that the number of error bits of the memory cell of the selected word line (such as the first word line WL1) exceeds a predetermined value of a specific programming state. The control circuit 130 can know whether a read error occurs, for example, through an error check operation. The control circuit 130 can identify whether the read error occurs in the high-level state group G_H or the low-level state group G_L. The critical voltage offset direction of the critical voltage distribution curve of the memory cell of the selected first word line WL1 can be determined. If a read error occurs, the identification process PD12 is entered.

The identification process PD12 includes step S140 and step S150. Please refer to FIG. 8, which illustrates an example of the identification process PD12 according to an embodiment. In step S140 of the identification process PD12, the control circuit 130 applies a first pass voltage Vpass1 to the first word line WL1 to turn on the memory cell connected to the first word line WL1.

In step S150 of the identification procedure PD12, the control circuit 130 applies an identification voltage Vrg23 to the second word line WL2 and the third word line WL3 to simultaneously read the memory cells connected to the second word line WL2 and the third word line WL3. As shown in FIG. 8, the memory cells of the second word line WL2 and the memory cells of the third word line WL3 are adjacent to the memory cells of the first word line WL1 and are located in the same memory cell series. The selected neighboring data of the first word line WL1 (the data stored in the memory cells of the second word line WL2 and the third word line WL3, respectively) can be a low-level state group G_L (represented by L) or a high-level state group G_H (represented by H). The neighboring data pattern of the selected first word line WL1 can be identified by the identification process PD12. The selected first word line WL1 includes a low neighboring critical voltage group NL1 and a high neighboring critical voltage group NH1. The low neighboring critical voltage group NL1 and the high neighboring critical voltage group NH1 of FIG. 8 will be described as follows.

Please refer to FIG. 9, which illustrates the identification voltage Vrg23 of FIG. 8 according to an embodiment. In one embodiment, the identification voltage Vrg23 is, for example, a voltage value at the middle point of all level states (or memory states) (for example, between the third programming state P3 and the fourth programming state P4 of the memory cell of the second word line WL2 and the third word line WL3). In another embodiment, the identification voltage Vrg23 is, for example, between the fifth programming state P5 and the sixth programming state P6 of the memory cell of the second word line WL2 and the third word line WL3. The setting value of the identification voltage Vrg23 is not intended to limit the present invention. As shown in FIG. 8, the low neighbor critical voltage group NL1 and the high neighbor critical voltage group NH1 can be distinguished by identifying the voltage Vrg23. In at least one embodiment of FIG. 9, the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3 of the memory cells of the second word line WL2 and the third word line WL3 are in the low level state group G_L (indicated by L), which can be classified into the low neighbor critical voltage group NL1. The fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7 of the memory cells of the second word line WL2 and the third word line WL3 are located in the high level state group G_H (indicated by H), which can be classified as the high neighbor critical voltage group NH1.

Returning to FIG. 8, in the low neighbor critical voltage group NL1, the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 are located in "LXL", "LXM", and "MXL". In the case of "LXL", "LXM", and "MXL", among the memory cells connected to the second word line WL2 and/or the third word line WL3, no memory cell is located in the high level state group G_H, and the low neighbor critical voltage group NL1 is formed. The high neighbor critical voltage group NH1 includes the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 in the cases of "HXH", "LXH", "HXL", "HXM", and "MXH". In the cases of "HXH", "LXH", "HXL", "HXM", and "MXH", at least one memory cell connected to the second word line WL2 and/or the third word line WL3 is in the high level state group G_H, forming the high neighbor critical voltage group NH1.

By applying the identification voltage Vrg23 to the second word line WL2 and the third word line WL3, the neighboring data pattern (ie, the high neighboring critical voltage group NH1 and/or the low neighboring critical voltage group NL1) can be identified.

After the critical voltage deviation is identified through the identification process PD12, the re-reading process PD13 is entered. The re-reading process PD13 includes steps S160-S170.

FIG. 10 illustrates an example of a rereading procedure PD13 according to an embodiment. As described above, the first read voltage Vread1 (such as the read voltage Vread67 in FIG. 2) can be used to identify that the read error occurs in the high-level state group G_H (such as the sixth programming state P6 and the seventh programming state P7). After programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1) will become wider and shift toward a lower critical voltage (as shown in FIG. 3). In step S160 of the rereading procedure PD13, the control circuit 130 applies a second read voltage Vread2 to the first word line WL1. The second read voltage Vread2 is lower than the first read voltage Vread1 (such as the read voltage Vread67). The second read voltage Vread2 is only used to read the memory cells with neighboring data patterns such as "LXL", "LXM", or "MXL" in the neighboring low voltage group curve Cnlg of the selected word line (such as the first word line WL1). The second read voltage Vread2 is not used to read all memory cells (located on the dotted line C1) of the selected word line (such as the first word line WL1). For example, the second read voltage Vread2 is equal to the first read voltage Vread1 minus an adjustment voltage △V10. Adjust the voltage △V10 to be greater than 0.

Next, in step S170 of the rereading procedure PD13, the control circuit 130 applies the first conduction voltage Vpass1 to the second word line WL2 and the third word line WL3. Steps S160 and S170 of the rereading procedure PD13 are executed simultaneously. In the rereading procedure PD13, the second word line WL2 and the third word line WL3 are applied with the same first conduction voltage Vpass1 to conduct the memory cells connected to the second word line WL2 and the third word line WL3.

As shown in Figure 10, the memory cells near the low voltage group curve Cnlg are less than the memory cells on the dotted line C1. The rereading procedure PD13 can effectively improve the reading efficiency and enhance the reading accuracy.

FIG. 11 illustrates a rereading procedure PD13 according to another embodiment. In the embodiment of FIG. 11, in step S160 of the rereading procedure PD13, the control circuit 130 applies a second read voltage Vread2' to the first word line WL1. The second read voltage Vread2' is higher than the first read voltage Vread1. For example, the second read voltage Vread2' is equal to the first read voltage Vread1 plus an adjustment voltage △V11. The adjustment voltage △V11 is greater than 0.

Next, in step S170 of the rereading procedure PD13, the control circuit 130 applies the first conduction voltage Vpass1 to the second word line WL2 and the third word line WL3. Steps S160 and S170 of the rereading procedure PD13 are executed simultaneously. In the rereading procedure PD13, the second word line WL2 and the third word line WL3 are applied with the same first conduction voltage Vpass1 to conduct the memory cells connected to the second word line WL2 and the third word line WL3.

As shown in FIG. 11, in this embodiment, the first read voltage Vread1 (such as the read voltage Vread01 in FIG. 2) can be used to identify that the read error occurs in the low-level state group G_L (such as the erase state E and the first programming state P1). After programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1') will become wider and shift toward a higher critical voltage (as shown in FIG. 4). The second read voltage Vread2 is only used to read the memory cells with neighboring data patterns such as "LXH", "HXL", "MXH", "HXM" or "HXH" in the neighboring high voltage group curve Cnhg' of the selected word line (such as the first word line WL1). The second read voltage Vread2 is not used to read all the memory cells (located on the dotted line C1') of the selected word line (such as the first word line WL1). As shown in Figure 11, the memory cells near the high voltage group curve Cnhg' are less than the memory cells on the dotted line C1'. The rereading procedure PD13 can effectively improve the reading efficiency and enhance the reading accuracy.

Through the above-mentioned embodiment, after the control circuit 130 reads the memory cell of the memory device 100, if a read error occurs in the memory cell of the selected word line (e.g., the first word line WL1), the control circuit 130 can identify the read error in the high level state group G_H or the low level state group G_L through the read voltage. After determining that the read error occurs in the high level state group G_H or the low level state group G_L, the critical voltage deviation direction of the critical voltage distribution curve of the memory cell of the selected word line (e.g., the first word line WL1) can be determined. Then, the control circuit 130 can identify the neighboring data patterns (i.e., the high neighboring critical voltage group NH1 or the low neighboring critical voltage group NL1) of the memory cells of the selected/error word line (e.g., the first word line WL1). Then, the control circuit 130 performs a rereading process on some memory cells of the selected word line (e.g., the first word line WL1) according to the critical voltage offset to improve the read efficiency and increase the read accuracy.

The identification procedure PD12 for identifying neighboring data states and critical voltage offset conditions can be executed in different implementations. Please refer to FIG. 12, which shows a flow chart of a reading method of a memory device 100 according to another embodiment. The identification procedure PD22 includes steps S240 and S250. Please refer to FIG. 13, which illustrates an example of the identification procedure PD22 according to another embodiment. In step S240 of the identification procedure PD22, the control circuit 130 applies a first conduction voltage Vpass1 to the first word line WL1 and the third word line WL3 to conduct the memory cells connected to the first word line WL1 and the third word line WL3.

In step S250 of the identification procedure PD22, the control circuit 130 applies an identification voltage Vrg2' to the second word line WL2 to read the memory cell connected to the second word line WL2. As shown in FIG. 13, the memory cell of the second word line WL2 and the memory cell of the third word line WL3 are adjacent to the memory cell of the first word line WL1 and are located in the same memory cell series. The selected neighboring data of the first word line WL1 (the data stored in the memory cells of the second word line WL2 and the third word line WL3, respectively) can be a low-level state group G_L (represented by L) or a high-level state group G_H (represented by H). The neighboring data pattern of the selected first word line WL1 can be identified by the identification process PD22. The selected first word line WL1 includes a low neighboring critical voltage group NL2 and a high neighboring critical voltage group NH2. The low neighboring critical voltage group NL2 and the high neighboring critical voltage group NH2 will be explained in the following content.

Please refer to FIG. 14, which shows the identification voltage Vrg2 of FIG. 13 according to another embodiment. In this embodiment, the identification voltage Vrg2 is, for example, located between the fifth programming state P5 and the sixth programming state P6 of the memory cell of the second word line WL2. The setting value of the identification voltage Vrg2 is not intended to limit the present invention. As shown in FIG. 13, the low neighbor critical voltage group NL2 and the high neighbor critical voltage group NH2 can be distinguished by the identification voltage Vrg2. In at least one embodiment of FIG. 14, the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, and the fifth programming state P5 of the memory cells of the second word line WL2 and the third word line WL3 are located in the low level state group G_L (represented by L) or the middle level state group G_M (represented by M), which can be classified as the low neighbor critical voltage group NL2. The sixth programming state P6 and the seventh programming state P7 of the memory cells of the second word line WL2 and the third word line WL3 are located in the high level state group G_H (represented by H), which can be classified as the high neighbor critical voltage group NH2.

Returning to FIG. 13 , the low neighbor critical voltage group NL2 includes the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 in the cases of “LXL”, “LXM”, “LXH”, “MXL”, “MXM”, and “MXH”. In the cases of “LXL”, “LXM”, “LXH”, “MXL”, “MXM”, and “MXH”, the memory cells connected to the second word line WL2 are in the low level state group G_L or the middle level state group G_M, forming the low neighbor critical voltage group NL2. The high neighbor critical voltage group NH2 includes the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 in the cases of "HXL", "HXM", and "HXH". In the cases of "HXL", "HXM", and "HXH", the memory cells connected to the second word line WL2 are in the high level state group G_H, forming the high neighbor critical voltage group NH2.

By applying the identification voltage Vrg2 to the second word line WL2, the neighboring data pattern (i.e., the high neighboring critical voltage group NH2 and/or the low neighboring critical voltage group NL2) can be identified. After the identification process PD22, the rereading process PD13 is entered.

Please refer to FIG. 15 again, which illustrates an example of the identification process PD22 according to another embodiment. In step S240 of the identification process PD22, the control circuit 130 applies the first pass voltage Vpass1 to the first word line WL1 and the third word line WL3 to turn on the memory cells connected to the first word line WL1 and the third word line WL3.

In step ' of the identification procedure PD22, the control circuit 130 applies an identification voltage Vrg2 to the second word line WL2 to read the memory cell connected to the second word line WL2. As shown in FIG. 15, the memory cell of the second word line WL2 and the memory cell of the third word line WL3 are adjacent to the memory cell of the first word line WL1 and are located in the same memory cell series. The selected neighboring data of the first word line WL1 (the data stored in the memory cells of the second word line WL2 and the third word line WL3, respectively) can be a low-level state group G_L (represented by L) or a high-level state group G_H (represented by H). The neighboring data pattern of the selected first word line WL1 can be identified by the identification process PD22. The selected first word line WL1 includes a low neighbor critical voltage group NL2' and a high neighbor critical voltage group NH2'. The low neighbor critical voltage group NL2' and the high neighbor critical voltage group NH2' of FIG. 15 will be explained in the following content.

Please refer to FIG. 16, which shows the identification voltage Vrg2' of FIG. 15 according to another embodiment. In this embodiment, the identification voltage Vrg2' is, for example, located between the first programming state P1 and the second programming state P2 of the memory cell of the second word line WL2. The setting value of the identification voltage Vrg2' is not intended to limit the present invention. As shown in FIG. 15, the low neighbor critical voltage group NL2' and the high neighbor critical voltage group NH2' can be distinguished by the identification voltage Vrg2'. In at least one embodiment of FIG. 16, the erase state E and the first programming state P1 of the memory cells of the second word line WL2 and the third word line WL3 are located in the low level state group G_L (represented by L), which can be classified as the low neighbor critical voltage group NL2'. The second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7 of the memory cells of the second word line WL2 and the third word line WL3 are located in the high level state group G_H (represented by H) or the middle level state group G_M (represented by M), which can be classified as the high neighbor critical voltage group NH2'.

Returning to FIG. 15, the low neighbor critical voltage group NL2' includes the cases where the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 are located at "LXL", "LXM", and "LXH". In the cases of "LXL", "LXM", and "LXH", the memory cells connected to the second word line WL2 are located in the low level state group G_L, forming the low neighbor critical voltage group NL2'. The high neighbor critical voltage group NH2' includes the cases where the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 are located at "MXL", "MXM", "MXH", "HXL", "HXM", and "HXH". In the cases of “MXL”, “MXM”, “MXH”, “HXL”, “HXM”, and “HXH”, the memory cells connected to the second word line WL2 are in the high level state group G_H or the middle level state group G_M, forming a high neighbor critical voltage group NH2’.

By applying the identification voltage Vrg2' to the second word line WL2, the neighboring data pattern (i.e., the high neighboring critical voltage group NH2' and/or the low neighboring critical voltage group NL2') can be identified. After the identification process PD22, the rereading process PD13 is entered.

The identification procedures PD12 and P22 for identifying neighboring data states and critical voltage offset conditions can be executed in another implementation manner. Please refer to FIG. 17, which shows a flow chart of a reading method of a memory device 100 according to another embodiment. The identification procedure PD32 includes steps S340 and S350. Please refer to FIG. 18, which illustrates an example of the identification procedure PD32 according to another embodiment. In step S340 of the identification procedure PD32, the control circuit 130 applies a first conduction voltage Vpass1 to the first word line WL1 and the second word line WL2 to conduct the memory cells connected to the first word line WL1 and the second word line WL2.

In step S350 of the identification procedure PD32, the control circuit 130 applies an identification voltage Vrg3' to the third word line WL3 to read the memory cell connected to the third word line WL3. As shown in FIG. 18, the memory cell of the second word line WL2 and the memory cell of the third word line WL3 are adjacent to the memory cell of the first word line WL1 and are located in the same memory cell series. The selected neighboring data of the first word line WL1 (the data stored in the memory cells of the second word line WL2 and the third word line WL3, respectively) can be a low-level state group G_L (represented by L) or a high-level state group G_H (represented by H). The neighboring data pattern of the selected first word line WL1 can be identified by the identification process PD32. The selected first word line WL1 includes a low neighboring critical voltage group NL3 and a high neighboring critical voltage group NH3. The low neighboring critical voltage group NL3 and the high neighboring critical voltage group NH3 of FIG. 18 will be explained in the following content.

Please refer to FIG. 19, which shows the identification voltage Vrg3 of FIG. 18 according to another embodiment. In this embodiment, the identification voltage Vrg3 is, for example, located between the fifth programming state P5 and the sixth programming state P6 of the memory cell of the third word line WL3. The setting value of the identification voltage Vrg3 is not intended to limit the present invention. As shown in FIG. 18, the low neighbor critical voltage group NL3 and the high neighbor critical voltage group NH3 can be distinguished by the identification voltage Vrg3. In at least one embodiment of FIG. 19, the erase state E, the first programming state P1, the second programming state P2, the third programming state P3, the fourth programming state P4, and the fifth programming state P5 of the memory cells of the second word line WL2 and the third word line WL3 are located in the low level state group G_L (represented by L) or the middle level state group G_M (represented by M), which can be classified as the low neighbor critical voltage group NL3. The sixth programming state P6 and the seventh programming state P7 of the memory cells of the second word line WL2 and the third word line WL3 are located in the high level state group G_H (represented by H), which can be classified as the high neighbor critical voltage group NH3.

Returning to FIG. 18, the low neighbor critical voltage group NL3 includes the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3, and are located in the cases of "LXL", "MXL", "HXL", "LXM", "MXM", and "HXM". In the cases of "LXL", "MXL", "HXL", "LXM", "MXM", and "HXM", the memory cells connected to the third word line WL3 are located in the low level state group G_L or the middle level state group G_M, and form the low neighbor critical voltage group NL3. The high neighbor critical voltage group NH3 includes the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 in the cases of "LXH", "MXH", and "HXH". In the cases of "LXH", "MXH", and "HXH", the memory cells connected to the third word line WL3 are in the high level state group G_H, forming the high neighbor critical voltage group NH3.

By applying the identification voltage Vrg3 to the third word line WL3, the neighboring data pattern (i.e., the high neighboring critical voltage group NH3 and/or the low neighboring critical voltage group NL3) can be identified. After the identification process PD32, the rereading process PD13 is entered.

Please refer to FIG. 20 again, which illustrates an example of the identification process PD32 according to another embodiment. In step S340 of the identification process PD32, the control circuit 130 applies a first pass voltage Vpass1 to the first word line WL1 and the second word line WL2 to turn on the memory cells connected to the first word line WL1 and the second word line WL2.

In step S350 of the identification procedure PD32, the control circuit 130 applies an identification voltage Vrg3 to the third word line WL3 to read the memory cell connected to the third word line WL3. As shown in FIG. 20, the memory cell of the second word line WL2 and the memory cell of the third word line WL3 are adjacent to the memory cell of the first word line WL1 and are located in the same memory cell series. The selected neighboring data of the first word line WL1 (the data stored in the memory cells of the second word line WL2 and the third word line WL3, respectively) can be a low level state group G_L (represented by L) or a high level state group G_H (represented by H). The neighboring data pattern of the selected first word line WL1 can be identified by the identification process PD32. The selected first word line WL1 includes a low neighbor critical voltage group NL3' and a high neighbor critical voltage group NH3'. The low neighbor critical voltage group NL3' and the high neighbor critical voltage group NH3' of FIG. 20 will be explained in the following content.

Please refer to FIG. 21, which shows the identification voltage Vrg3' of FIG. 20 according to another embodiment. In this embodiment, the identification voltage Vrg3' is, for example, between the first programming state P1 and the second programming state P2 of the memory cell of the third word line WL3. The setting value of the identification voltage Vrg3' is not intended to limit the present invention. As shown in FIG. 20, the low neighbor critical voltage group NL3' and the high neighbor critical voltage group NH3' can be distinguished by the identification voltage Vrg3'. In at least one embodiment of FIG. 21, the erase state E and the first programming state P1 of the memory cells of the second word line WL2 and the third word line WL3 are located in the low level state group G_L (represented by L), which can be classified into the low neighbor critical voltage group NL3. The second programming state P2, the third programming state P3, the fourth programming state P4, the fifth programming state P5, the sixth programming state P6, and the seventh programming state P7 of the memory cells of the second word line WL2 and the third word line WL3 are located in the high level state group G_H (represented by H) or the middle level state group G_M (represented by M), which can be classified into the high neighbor critical voltage group NH3.

Returning to FIG. 20, the low neighbor critical voltage group NL3' includes the cases where the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 are located at "LXL", "MXL", and "HXL". In the cases of "LXL", "MXL", and "HXL", the memory cells connected to the third word line WL3 are located in the low level state group G_L, forming the low neighbor critical voltage group NL3'. The high neighbor critical voltage group NH3' includes the cases where the memory cells connected to the second word line WL2, the first word line WL1, and the third word line WL3 are located at "LXM", "MXM", "HXM", "LXH", "MXH", and "HXH". In the cases of “LXM”, “MXM”, “HXM”, “LXH”, “MXH”, and “HXH”, the memory cells connected to the third word line WL3 are in the high level state group G_H or the middle level state group G_M, forming a high neighbor critical voltage group NH3’.

By applying the identification voltage Vrg3' to the third word line WL3, the neighboring data pattern (i.e., the high neighboring critical voltage group NH3' and/or the low neighboring critical voltage group NL3') can be identified. After the identification process PD32, the rereading process PD13 is entered.

The above-mentioned rereading program PD13 for rereading the memory cell can be executed in another implementation method. Please refer to Figure 22, which shows a flow chart of the reading method of the memory device 100 according to another embodiment. In the embodiment of Figure 22, the identification program PD32 is used to identify the neighboring data status and the critical voltage offset. In another embodiment, the identification program PD32 can be replaced by the identification program PD12 of Figure 5 or the identification program PD22 of Figure 12. In Figure 22, the rereading program PD23 includes steps S260~S280.

Please refer to FIG. 23, which illustrates an example of a rereading procedure PD23 according to another embodiment. As described above, the first read voltage Vread1 (such as the read voltage Vread67 in FIG. 2) can be used to identify that the read error occurs in the high-level state group G_H (such as the sixth programming state P6 and the seventh programming state P7). After programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1) will become wider and shift toward a lower critical voltage (as shown in FIG. 3). In step S260 of the rereading procedure PD23, the control circuit 130 applies the first read voltage Vread1 (such as the read voltage Vread67) to the first word line WL1. The re-reading procedure PD23 uses the same first read voltage Vread1 (such as read voltage Vread67) as the read procedure PD11. The first read voltage Vread1 (such as read voltage Vread67) is only used to read the memory cells with neighboring data patterns such as "LXL", "LXM", or "MXL" in the neighboring low voltage group curve Cnlg of the selected word line (such as the first word line WL1). The first read voltage Vread1 (such as read voltage Vread67) is not used to read all memory cells (located on the dotted line C1) of the selected word line (such as the first word line WL1).

Next, in step S270 of the rereading process PD23, the control circuit 130 applies a second conduction voltage Vpass2 to the second word line WL2. The second conduction voltage Vpass2 is lower than the first conduction voltage Vpass1. For example, the second conduction voltage Vpass2 is equal to the first conduction voltage Vpass1 minus an adjustment voltage ΔV23. The adjustment voltage ΔV23 is greater than 0.

Then, in step S280 of the rereading procedure PD23, the control circuit 130 applies a third conduction voltage Vpass3 to the third word line WL3. The third conduction voltage Vpass3 is lower than the first conduction voltage Vpass1. For example, the third conduction voltage Vpass3 is equal to the first conduction voltage Vpass1 minus an adjustment voltage △V23'. The adjustment voltage △V23' is greater than 0. The adjustment voltage △V23' can be the same as the adjustment voltage △V23, or different from the adjustment voltage △V23. By adjusting the second conduction voltage Vpass2 and the third conduction voltage Vpass3, the critical voltage distribution curve (as shown by the dotted line C2) can be moved back and narrowed, thereby reducing the overlap between the sixth programming state P6 and the seventh programming state P7 and reducing the reading error. Therefore, the rereading procedure PD23 can effectively improve the reading efficiency and enhance the reading accuracy.

Please refer to FIG. 24, which illustrates an example of a rereading procedure PD23 according to another embodiment. As described above, the first read voltage Vread1 (such as the read voltage Vread01 in FIG. 2) can be used to identify that the read error occurs in the low-level state group G_L (such as the erase state E and the first programming state P1). After programming and maintaining for a period of time, the critical voltage distribution curve (as shown by the dotted line C1') will become wider and shift toward a higher critical voltage (as shown in FIG. 4). In the embodiment of FIG. 24, in step S260 of the rereading procedure PD23, the control circuit 130 applies the first read voltage Vread1 (such as the read voltage Vread01) to the first word line WL1. The rereading procedure PD23 uses the same first read voltage Vread1 (such as read voltage Vread01) as the read procedure PD11. The first read voltage Vread1 (such as read voltage Vread01) is only used to read the memory cells having neighboring data patterns such as "LXH", "HXL", "MXH", "HXM", "HXH" in the neighboring high voltage group curve Cnhg' of the selected word line (such as the first word line WL1). The first read voltage Vread1 (such as read voltage Vread01) is not used to read all memory cells (located at the dotted line C1') of the selected word line (such as the first word line WL1).

Next, in step S270 of the rereading process PD23, the control circuit 130 applies a second conduction voltage Vpass2' to the second word line WL2. The second conduction voltage Vpass2' is higher than the first conduction voltage Vpass1. For example, the second conduction voltage Vpass2' is equal to the first conduction voltage Vpass1 plus an adjustment voltage ΔV24. The adjustment voltage ΔV24 is greater than 0.

Then, in step S280 of the rereading procedure PD23, the control circuit 130 applies a third conduction voltage Vpass3' to the third word line WL3. The third conduction voltage Vpass3' is higher than the first conduction voltage Vpass1. For example, the third conduction voltage Vpass3' is equal to the first conduction voltage Vpass1 plus an adjustment voltage △V24'. The adjustment voltage △V24' is greater than 0. The adjustment voltage △V24' can be the same as the adjustment voltage △V24, or different from the adjustment voltage △V24. By adjusting the second conduction voltage Vpass2' and the third conduction voltage Vpass3', the critical voltage distribution curve (as shown by the dotted line C2') can be moved back and narrowed, thereby reducing the overlap between the sixth programming state P6 and the seventh programming state P7 and reducing the reading error. Therefore, the rereading program PD23 can effectively improve the reading efficiency and enhance the reading accuracy.

The reading procedure PD11, identification procedures PD12, PD22, PD32, and re-reading procedures PD13, PD23 disclosed in the above-mentioned embodiments can be implemented in an interactive manner and are not limited to the contents disclosed in the diagrams.

Through the above-mentioned embodiment, after the control circuit 130 reads the memory cells of the memory device 100, if a read error occurs in the memory cells on the selected word line (such as the first word line WL1), the control circuit 130 identifies the voltage level of the read voltage and determines whether the read error occurs in the high level state group G_H or the low level state group G_L. After determining whether the read error occurs in the high level state group G_H or the low level state group G_L, the critical voltage distribution curve of the memory cells of the specific reference group can be evaluated as shifting toward a higher critical voltage or shifting toward a lower critical voltage. Afterwards, the control circuit 130 identifies the neighboring data pattern (i.e., the high neighboring critical voltage group NH1 or the low neighboring critical voltage group NL1). Then, the control circuit 130 performs a reread process on some memory cells of the selected word line (such as the first word line WL1) to improve the read efficiency and enhance the read accuracy.

Through the above embodiment, after the control circuit 130 reads the memory cell, if a read error occurs, the control circuit 130 can identify the adjacent data pattern and the critical voltage offset of the memory cell. Then, the control circuit 130 performs a re-reading process on the memory cell according to the critical voltage offset to reduce the read error range and increase the read accuracy.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100: memory device 110: row decoding circuit 120: column decoding circuit 130: control circuit BLi: bit line C0, C0’: solid line C1, C1’, C2, C2’: dashed line Cnlg: neighbor low voltage group curve Cnhg, Cnhg’: neighbor high voltage group curve E: erase state G_L: low level state group G_M: middle level state group G_H: high level state group NH1, NH2, NH2’, NH3, NH3’: high neighbor critical voltage group NL1, NL2, NL2’, NL3, NL3’: low neighbor critical voltage group P1: first programming state P2: second programming state P3: third programming state P4: fourth programming state P5: fifth programming state P6: sixth programming state P7: seventh programming state PD11: read program PD12, PD22, PD32: identify program PD13, PD23: reread program S110, S120, S130, S140, S150, S160, S170, S240, S250, S260, S270, S280, S340, S350: steps Vpass1: first conduction voltage Vpass2: second conduction voltage Vpass3: third conduction voltage Vread01, Vread12, Vread23, Vread34, Vread45, Vread56, Vread67: read voltage Vread1: first read voltage Vread2, Vread2’: second read voltage Vrg2, Vrg2’, Vrg3, Vrg3’, Vrg23: identification voltage WL1: first word line WL2: second word line WL3: third word line WLi: word line △V10, △V11, △V23, △V23’, △V24, △V24’: adjustment voltage

FIG. 1 shows a schematic diagram of a memory device according to an embodiment. FIG. 2 shows a critical voltage distribution curve of a memory cell of a selected word line according to an embodiment. FIG. 3 shows an example of a critical voltage distribution curve of a high-level state group. FIG. 4 shows an example of a critical voltage distribution curve of a low-level state group. FIG. 5 shows a flow chart of a read method of a memory device according to an embodiment. FIG. 6 shows an example of a read procedure. FIG. 7 shows another example of a read procedure. FIG. 8 shows an example of an identification procedure according to an embodiment. FIG. 9 shows an identification voltage of FIG. 8 according to an embodiment. FIG. 10 shows an example of a reread procedure according to an embodiment. FIG. 11 illustrates a rereading procedure according to another embodiment. FIG. 12 shows a flow chart of a reading method of a memory device according to another embodiment. FIG. 13 illustrates an identification procedure according to another embodiment. FIG. 14 shows an identification voltage according to FIG. 13 of another embodiment. FIG. 15 illustrates an identification procedure according to yet another embodiment. FIG. 16 shows an identification voltage according to FIG. 15 of another embodiment. FIG. 17 shows a flow chart of a reading method of a memory device according to another embodiment. FIG. 18 illustrates an identification procedure according to another embodiment. FIG. 19 shows an identification voltage according to FIG. 18 of another embodiment. FIG. 20 illustrates an identification procedure according to another embodiment. FIG. 21 illustrates an identification voltage according to FIG. 20 according to another embodiment. FIG. 22 illustrates a flow chart of a reading method of a memory device according to another embodiment. FIG. 23 illustrates a rereading procedure according to another embodiment. FIG. 24 illustrates a rereading procedure according to another embodiment.

NH1: High neighbor critical voltage group

NL1: Low adjacent critical voltage group

PD12: Identification procedure

Vpass1: first conduction voltage

Vrg23: Identification voltage

WL1: First word line

WL2: Second word line

WL3: third word line

Claims (10)

A method for reading a memory device, the memory device at least comprising a first word line, a second word line and a third word line, the second word line and the third word line being adjacent to the first word line, the method comprising: Executing a reading procedure to read a plurality of memory cells of the first word line, wherein the reading procedure comprises: Applying a first reading voltage to the first word line; and When applying the first reading voltage to the first word line, applying a first conduction voltage to the second word line and the third word line; and In response to a reading error occurring in at least one of the memory cells, executing an identification procedure, wherein the identification procedure comprises: Applying the first conduction voltage to the first word line; and When applying the first conduction voltage to the first word line, applying an identification voltage to at least one of the second word line and the third word line to identify the adjacent data pattern; and Performing a rereading procedure on the at least one memory cell, the rereading procedure comprising: Applying a second read voltage to the first word line; and When the second read voltage is applied to the first word line, applying a second conduction voltage to the second word line and a third conduction voltage to the third word line. A reading method for a memory device as described in claim 1, wherein in the rereading process, the second reading voltage is different from the first reading voltage. A method for reading a memory device as described in claim 1, wherein in the identification process, the first conduction voltage is applied to the first word line, and the identification voltage is applied to the second word line and the third word line. A method for reading a memory device as described in claim 1, wherein in the identification process, the first conduction voltage is applied to the first word line and the third word line, and the identification voltage is applied to the second word line. A method for reading a memory device as described in claim 1, wherein the first read voltage is used to identify a high level state group or a low level state group. A memory device comprises at least: a first word line; a second word line; a third word line, the second word line and the third word line are adjacent to the first word line; and a control circuit, the control circuit is used to execute a read procedure to read a plurality of memory cells of the first word line; the control circuit executes an identification procedure in response to a read error in at least one of the memory cells; the control circuit executes a reread procedure for the at least one memory cell, wherein in the read procedure, the control circuit is used to apply a first read voltage to the first word line; When the first read voltage is applied to the first word line, the control circuit is used to apply a first conduction voltage to the second word line and the third word line; In the identification process, The control circuit is used to apply the first conduction voltage to the first word line; and When the first conduction voltage is applied to the first word line, the control circuit is used to apply an identification voltage to at least one of the second word line and the third word line to identify the adjacent data pattern; In the reread process, The control circuit is used to apply a second read voltage to the first word line; and When the second read voltage is applied to the first word line, the control circuit is used to apply a second conduction voltage to the second word line and a third conduction voltage to the third word line. A memory device as described in claim 6, wherein in the reread process, the second read voltage is different from the first read voltage. A memory device as described in claim 6, wherein in the identification process, the first conduction voltage is applied to the first word line, and the identification voltage is applied to the second word line and the third word line. A memory device as described in claim 6, wherein in the identification process, the first conduction voltage is applied to the first word line and the third word line, and the identification voltage is applied to the second word line. A memory device as described in claim 6, wherein the first read voltage is used to identify belonging to a high level state group or a low level state group.

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