TWI869311B - Matrix-vector multiplication circuit and circuit configuring method of the same - Google Patents

Abstract

A matrix-vector multiplication circuit configured to represent a plurality of weight values is provided in the present disclosure. The matrix-vector multiplication circuit comprises a plurality of resistor strings, and each of the plurality of resistor strings comprises a plurality of weight units. The plurality of resistor strings are coupled between two reference voltages in parallel. For each of the plurality of resistor strings, the plurality of weight units are coupled between the two reference voltages in series. The plurality of weight units form a plurality of combinations corresponding to the plurality of weight values. For each of the plurality of combinations, the plurality of weight units have the same order in the plurality of resistor strings respectively. Each of the plurality of weight units has a status value, and the status values of the plurality of weight units in the plurality of combinations form a plurality of sequences respectively corresponding to the plurality of weight values. The plurality of weight units corresponding to a plurality of most significant bits of the plurality of sequences are located in at least two of the plurality of resistor strings.

Description

Matrix vector operation circuit and circuit configuration method thereof

The present disclosure relates to a resistor configuration technique in a matrix vector operation circuit, and more particularly to a matrix vector operation circuit and a circuit configuration method thereof that can improve output linearity.

As the amount of computation in today's semiconductor devices increases, how to configure array circuits in memory devices has become one of the key points in designing memory devices. Among the many array circuit configurations, the mixing-mode matrix-vector multiplication (MVM) circuit structure is widely used because it can handle large amounts of input data and weight value operations.

In order to ensure that the calculation results are correct, the memory device needs to be able to accurately calculate the equivalent resistance value of the array circuit to produce accurate output. However, in the current configuration of mixed-mode MVM circuits, the weights inside the circuit are unevenly distributed. In other words, in the current configuration, the linearity of the output of the mixed-mode MVM circuit is insufficient, which leads to a deviation between the estimated resistance value and the actual resistance value, and may produce inaccurate output. Therefore, how to improve the linearity of the output of the mixed-mode MVM circuit by adjusting the configuration of the circuit is one of the topics in this field.

The present disclosure document provides a matrix vector operation circuit for presenting multiple weight values. The matrix vector operation circuit includes multiple resistor strings, each of which includes multiple weight units. The multiple resistor strings are coupled in parallel between two reference voltages, and the multiple weight units of each resistor string are coupled in series between the two reference voltages. The multiple weight units form multiple combinations, the multiple combinations correspond to multiple weight values, and the multiple weight units in each combination have the same order in the multiple resistor strings. Each weight unit has a state value, and the multiple state values of the multiple weight units of the multiple combinations form multiple sequences, and the multiple sequences correspond to the multiple weight values. The multiple weight units corresponding to the multiple most significant bits of the multiple sequences are located in at least two of the multiple resistor strings.

In some embodiments of the matrix vector operation circuit, the weight units corresponding to the most significant bits of the odd sequences in the plurality of sequences are located in one of the plurality of resistor strings, and the weight units corresponding to the most significant bits of the even sequences in the plurality of sequences are located in another one of the plurality of resistor strings. The odd sequences are different from the even sequences.

In some embodiments of the matrix-vector operation circuit, the weight units corresponding to the most significant bits of the odd-numbered sequences and the weight units corresponding to the least significant bits of the even-numbered sequences are located in the same one of the resistor strings. The weight units corresponding to the most significant bits of the even-numbered sequences and the weight units corresponding to the least significant bits of the odd-numbered sequences are located in another same one of the resistor strings.

In some embodiments of the matrix vector operation circuit, a plurality of weight units corresponding to a plurality of odd number sequences and a plurality of weight units corresponding to a plurality of even number sequences are alternately arranged in a plurality of resistor strings.

In some embodiments of the matrix vector operation circuit, multiple state values of multiple weight units each belong to bit 0 or bit 1, and the multiple weight values respectively correspond to the number of weight units having state values belonging to bit 1 in multiple combinations.

In some embodiments of the matrix-vector operation circuit, the plurality of sequences belong to a unary code array, and each weight value corresponds to the number of consecutive bits 1 starting from the most significant bit in a corresponding one of the plurality of sequences.

In some embodiments of the matrix-vector operation circuit, the weight unit corresponding to the least significant bit of one of the multiple sequences and the weight unit corresponding to the most significant bit of an adjacent one of the multiple sequences are located in the same one of the multiple resistor strings.

In some embodiments of the matrix vector operation circuit, the matrix vector operation circuit further includes a control circuit for generating a plurality of input signals to a plurality of weight units respectively. The plurality of weight units each have a resistance value, and the resistance value is related to the state value and to the plurality of input signals.

In some embodiments of the matrix vector operation circuit, each of the plurality of resistor strings further comprises an additional resistor. The additional resistor is coupled in series to the plurality of weight units to prevent the plurality of resistor strings from undergoing a fast charging behavior.

In some embodiments of the matrix vector operation circuit, each of the plurality of weight units and the additional resistor has a resistance value, and the resistance value of the additional resistor is close to or greater than the resistance value of each weight unit.

The present disclosure document provides a circuit configuration method for configuring a matrix vector operation circuit. The matrix vector operation circuit includes a control circuit and a plurality of resistor strings coupled in parallel between two reference voltages. The plurality of resistor strings each include a plurality of weight units, and the plurality of weight units of each resistor string are coupled in series between the two reference voltages. The circuit configuration method includes: setting a plurality of weight values of the matrix vector operation circuit by the control circuit; determining a plurality of sequences based on the plurality of weight values by the control circuit, wherein the plurality of sequences correspond to the plurality of weight values respectively; and setting a state value of each weight unit based on the plurality of sequences by the control circuit. The plurality of weight units form a plurality of combinations corresponding to the plurality of weight values, and the plurality of weight units in each combination have the same order in the plurality of resistor strings respectively. The weight units corresponding to the most significant bits of the sequences are located in at least two of the resistor strings.

In some embodiments of the circuit configuration method, determining multiple sequences based on multiple weight values by the control circuit includes: dividing the multiple sequences into multiple odd sequences and multiple even sequences by the control circuit. Multiple weight units corresponding to multiple most significant bits of the multiple odd sequences are located in one of the multiple resistor strings, and multiple weight units corresponding to multiple most significant bits of the multiple even sequences are located in another one of the multiple resistor strings. The multiple odd sequences are different from the multiple even sequences.

In some embodiments of the circuit configuration method, the weight units corresponding to the most significant bits of the odd-numbered sequences and the weight units corresponding to the least significant bits of the even-numbered sequences are located in the same one of the resistor strings. The weight units corresponding to the most significant bits of the even-numbered sequences and the weight units corresponding to the least significant bits of the odd-numbered sequences are located in another same one of the resistor strings.

In some embodiments of the circuit configuration method, a plurality of weight units of a plurality of combinations corresponding to a plurality of odd-numbered sequences and a plurality of weight units of a plurality of combinations corresponding to a plurality of even-numbered sequences are alternately arranged in a plurality of resistor strings.

In some embodiments of the circuit configuration method, setting the state value of each weight unit based on multiple sequences by the control circuit includes: setting multiple state values of the multiple weight units to bit 0 or bit 1 by the control circuit. The multiple weight values correspond to the number of weight units having state values belonging to bit 1 in the multiple combinations.

In some embodiments of the circuit configuration method, the plurality of sequences belong to a unary coding array, and each weight value corresponds to the number of consecutive bits 1 starting from the most significant bit in a corresponding one of the plurality of sequences.

In some embodiments of the circuit configuration method, a weight unit corresponding to the least significant bit of one of the plurality of sequences and a weight unit corresponding to the most significant bit of an adjacent one of the plurality of sequences are located in the same one of the plurality of resistor strings.

In some embodiments of the circuit configuration method, each of the weight units has a resistance value, and the resistance value is related to the state value. Setting the state value of each weight unit based on multiple sequences by the control circuit includes: generating multiple input signals to the multiple weight units by the control circuit to control the resistance value of each weight unit.

In some embodiments of the circuit configuration method, each of the plurality of resistor strings further comprises an additional resistor, and the additional resistor is coupled in series to the plurality of weight units. The circuit configuration method further comprises: setting the resistance value of the additional resistor by a control circuit to prevent the plurality of resistor strings from undergoing rapid charging behavior.

In some embodiments of the circuit configuration method, each of the plurality of weight units has a resistance value, and the resistance value of the additional resistor is close to or greater than the resistance value of each weight unit.

Through the matrix vector operation circuit and the circuit configuration method disclosed in this document, the weight values inside the circuit can be configured more evenly, thereby improving the linearity of the output of the matrix vector operation circuit to output more accurate operation results.

The following will be used in conjunction with the relevant drawings to illustrate the embodiments of the present disclosure. In the drawings, the same reference numerals represent the same or similar elements or method flows.

In this disclosure document, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" may also be used to indicate the coordinated operation or interaction between two or more elements. Unless the text specifically limits the articles, "one" and "the" may refer to one or more. It will be further understood that the words "include", "including", "have" and similar words used in this article specify the features, regions, integers, steps, operations, elements and/or components recorded therein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components and/or groups thereof described therein or in addition.

FIG. 1 is a schematic diagram of a matrix vector operation circuit 100 according to some embodiments of the present disclosure. In some embodiments, the matrix vector operation circuit 100 includes resistor strings 110_1 to 110_M and a control circuit 120 for presenting multiple input values. The method for presenting multiple weight values by the matrix vector operation circuit 100 will be described in detail below.

The resistor strings 110_1 to 110_M each include a plurality of weight units. For example, the resistor string 110_1 includes weight units W ₁₁ to W _N1 , the resistor string 110_2 includes weight units W ₁₂ to W _N2 , the resistor string 110_M includes weight units W _1M to W _NM , and so on, where N and M are positive integers. In some embodiments, the resistor strings 110_1 to 110_M are coupled in parallel between the reference voltage V _ref1 and the reference voltage V _ref2 , and the plurality of weight units of each resistor string (e.g., the weight units W ₁₁ to W _N1 in the resistor string 110_1) are coupled in series between the reference voltage V _ref1 and the reference voltage V _ref2 , thereby forming a matrix circuit structure.

In some embodiments, each weight unit has a state value (e.g., bit 0, bit 1 in a binary mode, or bit 0, bit 1, bit 2, etc. in a multi-bit mode), and the state value determines the resistance value of the weight unit. For example, a weight unit with a state value of bit value 1 has a higher resistance value _RH , while a weight unit with a state value of bit value 0 has a lower resistance value _RL . According to the resistance value of each series/parallel weight unit, the equivalent resistance value _Req of the matrix circuit can be determined.

In addition, each weight unit is used to receive an input signal from the control circuit 120. For example, the weight units W ₁₁ -W _N1 receive input signals IN ₁₁ -IN _N1 respectively, the weight units W ₁₂ -W _N2 receive input signals IN ₁₂ -IN _N2 respectively, the weight units W _1M -W _NM receive input signals IN _1M -IN _NM respectively, and so on. The input signal received by each weight unit will affect its state value, thereby affecting its resistance value and the equivalent resistance value R _eq of the matrix circuit.

The control circuit 120 is coupled to each weight unit in the resistor strings 110_1 - 110_M for generating input signals IN ₁₁ -IN _N1 , IN ₁₂ -IN _N2 , . . . , IN _1M -IN _NM (collectively referred to as “IN”) to each weight unit in the resistor strings 110_1 - 110_M.

As described above, in some embodiments, the matrix vector operation circuit 100 is used to present a plurality of weight values. Please refer to FIG. 2, which is a schematic diagram of the relationship between the matrix vector operation circuit 200 and the weight values according to some embodiments of the present disclosure. It should be noted that the matrix vector operation circuit 200 in FIG. 2 is similar to the matrix vector operation circuit 100 in FIG. 1, so its internal structure is not repeated here.

In some embodiments, weight units with the same order in the resistor strings 210_1 - 210_5 form a combination, and the combination corresponds to the same weight value (ie, the weight value corresponding to a certain weight unit in FIG. 1 ). For example, the weight units W _{11_1} , W _{11_2} , W _{11_3} , W _{11_4} , and W _{11_5} at the top (i.e., closest to the reference voltage V _ref1 ) in the resistor string 210_1 to 210_5 form a combination, which corresponds to the first weight value (i.e., the weight value corresponding to the weight unit W ₁₁ in FIG. 1 ), and the weight units W _{21_1} , W _{21_2} , W _{21_3} , W _{21_4} , and W _{21_5} at the second top (i.e., second closest to the reference voltage V _ref1 ) in the resistor string 210_1 to 210_5 form another combination, which corresponds to the second weight value (i.e., the weight value corresponding to the weight unit W ₂₁ in FIG. 1 ), and so on.

In addition, each weight value determines the state value of the combination of weight units to which it corresponds. In some embodiments, the weight value can be represented by a unary code array, for example, a weight value of 0 can be represented by an array of "00000", a weight value of 1 can be represented by an array of "10000", a weight value of 2 can be represented by an array of "11000", a weight value of 3 can be represented by an array of "11100", a weight value of 4 can be represented by an array of "11110", and a weight value of 5 can be represented by an array of "11111". In other words, each weight value can be represented by an array having a continuous and corresponding number of bits 1 starting from the most significant bit.

Therefore, in the embodiment where the weight values are represented by a unary coded array, the array represented by the weight values can determine the state value of the combination of weight units corresponding thereto. Taking the embodiment of FIG. 2 as an example, the first weight value (i.e., the weight value corresponding to the weight unit _W11 in FIG. 1) is 0, so the state values of the weight units _{W11_1} to _{W11_5} are all 0; the second weight value (i.e., the weight value corresponding to the weight unit _W21 in FIG. 1) is 1, so the state values of the weight units _{W21_1} to _{W21_5} are 1, 0, 0, 0, 0, respectively; the third weight value (i.e., the weight value corresponding to the weight unit _W31 in FIG. 1) is 2, so the state values of the weight units _{W31_1} to _{W31_5} are 1, 1, 0, 0, 0, respectively; the fourth weight value (i.e., the weight value corresponding to the weight unit _W41 ) is 3, so the state values of the weight units _{W41_1} to W41_5 are 1, 1, 0, 0, 0, respectively. The state values of weight _{units W 41_5} are 1, 1, 1, 0, 0 respectively; the fifth weight value (i.e., the weight value corresponding to weight unit W ₅₁ ) is 4, so the state values of weight units W _{51_1} ~W _{51_5} are 1, 1, 1, 1, 0 respectively; the sixth weight value (i.e., the weight value corresponding to weight unit W ₆₁ ) is 5, so the state values of weight units W _{61_1} ~W _{61_5} are all 1.

It should be noted that the number of state values of the weight unit and the encoding method of the weight value described above are only examples and are not intended to limit this disclosure. Other numbers of state values of the weight unit and other weight value encoding methods are within the scope of this disclosure. In some embodiments, the weight unit can have more than three different state values. In some embodiments, the weight value can be represented by a binary array.

FIG. 3A is a schematic diagram of the configuration of the state value of the matrix vector operation circuit 200 according to some examples. It should be noted that for the sake of simplicity of the drawings, the labels of the resistor strings 210_1 to 210_5 and all weight units in FIGS. 3A to 3D are omitted.

The example of FIG. 3A is a common configuration of the state value of the weight unit. In detail, each weight value is represented as a unary coding array, and the bits from the most significant bit (MSB) to the least significant bit (LSB) in the unary coding array are sequentially represented by the state value of the weight unit in the corresponding combination, and the MSB in each unary coding array of each weight value is represented by the weight unit in the same resistor string.

In Figures 3A to 3C, the arrows next to each combination of weight units represent the order of weight units corresponding to the MSB to LSB of the unary coding array. Taking the example of Figure 3A as an example, the first weight value is 5, and the unary coding array represented is "11111", so the state values of weight units W _{11_1} to W _{11_5} are 1, 1, 1, 1, 1 in sequence; the third weight value is 2, and the unary coding array represented is "11000", so the state values of weight units W _{31_1} to W _{31_5} are 1, 1, 0, 0, 0 in sequence. In other words, all bits in the unary coding array are sequentially represented by the weight units in the resistor strings 210_1 to 210_5, so all MSBs correspond to the weight units of the resistor string 210_1.

As mentioned above, depending on the state value of the weight unit, the weight unit will have a higher resistance value _RH or a lower resistance value _RL . Therefore, due to the characteristic that the bit 1 in the unary coding array is concentrated in the front bit, in the circuit configuration method of FIG. 3A, the sum of the state values of the resistor strings 210_1 to 210_5 is 11, 9, 7, 3, and 2, showing a decreasing phenomenon, resulting in the problem of uneven resistance value distribution in the resistor strings 210_1 to 210_5. As shown in FIG. 2 , since the resistor strings 210_1 to 210_5 are connected in parallel between the reference voltages V _ref1 and V _ref2 , when the resistor strings 210_1 to 210_5 have uneven resistance distribution, the current will be concentrated on the resistor string with a smaller resistance value (i.e., the resistor string 210_5 ), causing the current to be easily dominated by the resistor string, thereby affecting the operation of the entire circuit.

To solve the above problems, the present disclosure provides a variety of configuration methods for the state values of the matrix circuit. Please refer to FIG. 1 again. The equivalent resistance value R _eq of the matrix circuit formed by the resistor string 110_1 to 110_M can be expressed by the following "Formula 1": "Formula One".

In Formula One, " represents the average resistance value of all weighted units, " " represents the standard deviation of the number of weighted cells with resistance value _RH in each resistor string, " " represents the average resistance value of all weighted cells divided by the difference between the resistance value _RH and the resistance value _RL , and " " represents the difference between the number of weight units with resistance value _RH in each resistor string and the average number of weight units with resistance value _RH in all resistor strings.

In order to simplify the calculation of "Formula 1", many current matrix circuit configuration methods have chosen to increase the " " (for example, by the arrangement method of Figure 3A) to simplify "Formula 1" into the following "Formula 2": Formula 2.

However, as mentioned above, the resistor string in the known matrix circuit configuration method (for example, the configuration method of FIG. 3A) is prone to uneven resistance distribution. Therefore, in the present disclosure, the selection is made to reduce the " "Simplify "Formula 1" into "Formula 2". "This method can not only simplify "Formula 1", but also improve the phenomenon of uneven resistance distribution of the resistor string mentioned above.

FIG. 3B to FIG. 3D are schematic diagrams of the configuration of the state value of the matrix vector operation circuit 200 according to different embodiments of the present disclosure. First, please refer to FIG. 3B. In FIG. 3B, the arrow symbols have two directions (from left to right and from right to left) and are arranged alternately. Therefore, for the odd-numbered weight values, the bits in the unary coding array are sequentially represented by the weight units in the resistor strings 210_1 to 210_5; for the even-numbered weight values, the bits in the unary coding array are sequentially represented by the weight units in the resistor strings 210_5 to 210_1.

In other words, the weight unit corresponding to the MSB of the unary coding array corresponding to the odd-numbered weight value and the weight unit corresponding to the LSB of the unary coding array corresponding to the even-numbered weight value are located in the same resistor string, and the weight unit corresponding to the MSB of the unary coding array corresponding to the even-numbered weight value and the weight unit corresponding to the LSB of the unary coding array corresponding to the odd-numbered weight value are located in another identical resistor string. Therefore, under the condition of the same weight value as FIG. 3A, the sum of the state values of the resistor string 210_1~210_5 in FIG. 3B is 6, 6, 7, 6, 7, showing a more even distribution, thereby obtaining a more even total resistance value configuration to reduce the " ".

Next, please refer to Figure 3C. In Figure 3C, the arrows are all from left to right. Unlike Figure 3A, the starting point of the arrow of the weight value in Figure 3C is the end point of the arrow of the previous weight value, which means that the configuration method of the unary coding array is different from that of Figure 3A. For example, in FIG. 3C , the third weight value is 2, and the corresponding unary coding array is “11000”. The state values of weight units W _{31_1} to W _{31_3} are sequentially configured as 1, 1, and 0, and the state values of weight units W _{31_4} and W _{31_5} are configured as 0, so the LSB corresponds to the resistor string 210_3 at this time; the fourth weight value is 1, and the corresponding unary coding array is “10000”. At this time, the configuration of the weight unit will start from the resistor string (i.e., the resistor string 210_3) corresponding to the LSB of the unary coding array of the previous weight value, so the state values of weight units W _{41_3} and W _{41_4} are sequentially configured as 1 and 0, and the state values of weight units W _{41_1} and W _{41_2} are sequentially configured as 1 and 0. , the state value of W _{41_5} is configured to 0, and the LSB corresponds to the resistor string 210_4; the fifth weight value is 3, and the corresponding unary coding array is "11100". At this time, the configuration of the weight unit will start from the resistor string corresponding to the LSB of the unary coding array of the previous weight value (that is, the resistor string 210_4), so the state values of the weight units W _{51_4} , W _{51_5} , W _{51_1} , W _{51_2} , and W _{51_3} are configured to 1, 1, 1, 0, 0 in sequence, and so on.

In other words, the weight unit corresponding to the MSB of the unary coded array of the current weight value is located in the same resistor string as the weight unit corresponding to the LSB of the unary coded array of the previous weight value. Therefore, under the same weight value as FIG. 3A, the sum of the state values of the resistor string 210_1~210_5 in FIG. 3C is 7, 7, 6, 6, 6, showing a more even distribution, thereby obtaining a more even total resistance value configuration to reduce the " ".

Finally, please refer to Figure 3D. In Figure 3D, the weight value represents the number of weight units with a state value of 1 in the corresponding combination, and these weight units with a state value of 1 are randomly distributed in their combination (so the weight units with a state value of 1 are not necessarily adjacent). Therefore, under the same weight value as Figure 3A, the sum of the state values of the resistor string 210_1~210_5 in Figure 3D is 7, 7, 7, 6, 5, showing a more even distribution, thereby obtaining a more even total resistance value configuration to reduce the " ".

In summary, under the configuration of the state values in FIGS. 3B to 3D , the MSBs of the unary encoding arrays of all weight values are located in at least two of the resistor strings 210_1 to 210_5 , thereby obtaining a more average total resistance value configuration (i.e., having a lower standard deviation of the sum of the state values, as shown in Table 1 below). Weight values: [5,0,2,1,3,3,3,4,5,3,1,2] Configuration Method The sum of the status values of the 5 resistor strings The average value of the sum of the state values of the resistor string Standard deviation of the sum of the state values of the resistor string Figure 3A [11,9,7,3,2] 6.4 3.34 Figure 3B [6,6,7,6,7] 6.4 0.49 Figure 3C [7,7,6,6,6] 6.4 0.49 Figure 3D [7,7,7,6,5] 6.4 0.8 Table 1

In some embodiments, a matrix vector operation circuit (e.g., the matrix vector operation circuit 100 in FIG. 1 ) may have multiple sets of resistor strings, and each set of resistor strings is used to process a set of weight values. Therefore, the weight values at this time may be a matrix rather than an array. This configuration of weight values and matrix vector operation circuits is called a mixing-mode configuration.

For example, Table 2 below lists the weight values of a matrix-vector operation circuit of an example mixed-mode configuration, wherein the matrix-vector operation circuit has eight sets of resistor strings, each set of resistor strings corresponds to 32 weight values, and each weight value is between and including 0 and 3. In addition, Table 3 below lists the configuration, average value, and standard deviation of the weight values in Table 2 when using the configuration method of FIGS. 3A to 3D. Example of weight values for matrix-vector operation circuits in mixed-mode configuration [1,2,0,0,2,3,1,2],[0,0,2,0,1,0,2,2],[3,0,1,0,3,2,0,0],[3,1,3,3,1,1,1,0], [1,3,1,2,2,2,1,0],[3,1,3,1,1,3,0,1],[2,2,3,2,2,1,2,0],[1,3,0,2,0,3,3,2], [1,1,3,3,0,1,1,3],[1,2,2,2,0,1,3,2],[2,3,1,0,2,2,1,0],[2,3,0,1,1,1,2,2], [0,3,0,2,2,3,3,0],[2,0,3,3,2,2,2,0],[3,2,0,1,0,0,0,0],[0,0,3,1,0,3,0,1], [1,3,1,3,0,0,1,0],[2,3,1,3,1,1,3,1],[1,0,1,1,3,3,3,1],[1,1,2,2,3,0,1,1], [1,3,3,0,0,3,3,2],[0,2,2,0,0,0,0,3],[1,2,1,1,0,3,3,2],[0,0,1,1,1,1,0,0], [3,0,0,3,2,0,2,1],[1,1,3,1,3,0,3,0],[1,0,2,1,3,2,0,0],[2,3,3,0,0,3,1,2], [2,2,0,1,3,3,3,0],[1,1,0,0,0,3,1,3],[0,2,0,3,0,1,2,1],[2,3,0,0,3,2,1,1] Table 2 Configuration Method The sum of the status values of the 24 resistor strings Average value of the sum of status values Standard deviation of the sum of state values Figure 3A [27,14,6,25,19,11,23,15,10,24,14,8,21,15,8,26,18,12,26,16,10,20,12,4] 16 6.708 Figure 3B [17,14,16,18,19,18,17,15,16,16,14,16,14,15,15,19,18,19,18,16,18,10,12,14] 16 2.236 Figure 3C [16,16,15,19,18,18,16,16,16,16,15,15,15,15,14,19,19,18,18,17,17,12,12,12] 16 2.062 Figure 3D [15,17,15,16,19,20,19,13,16,14,18,14,15,13,16,19,17,20,14,16,22,11,12,13] 16 2.769 Table 3

It can be seen from Tables 2 and 3 that, similar to Table 1, the standard deviation of the sum of state values obtained by the configuration method of Figures 3B to 3D is also significantly smaller than the standard deviation obtained by the configuration method of Figure 3A.

FIG. 4 is a diagram showing the relationship between the equivalent resistance value (i.e., the measured resistance value) and the estimated resistance value obtained according to the weight value combination in Table 2 and the configuration method in FIGS. 3A to 3D according to some embodiments of the present disclosure. It should be noted that for ease of explanation, the configuration methods in FIGS. 3A to 3D are respectively labeled as configuration methods 1 to 4 in FIG. 4.

When the measured resistance value is closer to the estimated resistance value (i.e., the distribution in the graph is closer to a straight line with a slope of 1), the linearity obtained by the configuration method is better. Therefore, from Figure 4, it can be seen that the linearity obtained by the configuration method of Figures 3B to 3D is significantly better than the linearity obtained by the configuration method of Figure 3A.

FIG. 5 is a schematic diagram of a matrix vector operation circuit 500 according to some embodiments of the present disclosure. The matrix vector operation circuit 500 is similar to the matrix vector operation circuit 100 in FIG. 1 . The difference is that each of the resistor strings 510_1 to 510_M of the matrix vector operation circuit 500 further includes an additional resistor _RS . The additional resistor _RS is coupled in series between the multiple weight units of the resistor string and the reference voltage V _ref2 to prevent the resistor string from being rapidly charged.

In some embodiments, in order for the additional resistor R _S to properly play the role of preventing fast charging, the resistance value of the additional resistor R _S is set to one or more times the resistance value of the weight unit with a higher resistance value (for example, a weight unit with a state value of 1 and a resistance value of _RH ), so the resistance value of the additional resistor R _S is approximately equal to or greater than the resistance value of each weight unit in the resistor string.

In some embodiments, each weight unit has a state value in a multi-bit mode, such as bit 0, bit 1, bit 2, ..., etc., and the state value determines the resistance value of the weight unit to be R _L , R _H1 , R _H2 , ..., etc. The resistance value of the additional resistor R _S is set to the resistance value of the weight unit with a higher resistance value, such as R _H1 , R _H2 , ..., etc. Therefore, the resistance value of the additional resistor R _S is approximately equal to or greater than the resistance value of the weight unit in the resistor string.

FIG. 6 is a flow chart of a circuit configuration method 600 according to some embodiments of the present disclosure. The circuit configuration method 600 is used to configure the state values of multiple weight units in a matrix vector operation circuit (e.g., the matrix vector operation circuit 100, 200, 500). In some embodiments, the circuit configuration method 600 includes steps S610, S620, S630, and S640.

In step S610, a plurality of weight values of the matrix vector operation circuit are set by a control circuit (eg, control circuit 120). Then, step S620 is executed.

In step S620, the control circuit determines a sequence of multiple state values (for example, the unary encoding array corresponding to the state values in FIG. 2) according to the multiple weight values set in step S610. These sequences correspond to each weight value respectively. Then, step S630 is executed.

In step S630, the state value of each weight unit is set based on multiple sequences by the control circuit (for example, using the configuration of the state value in Figures 3B to 3D). Then, step S640 is executed.

In step S640, an additional resistor is respectively set in the plurality of resistor strings to prevent the resistor strings from being rapidly charged, and the resistance value of the additional resistor is set by a control circuit.

It should be noted that the number and order of steps in the circuit configuration method 600 of the present disclosure are only examples and are not intended to limit the present disclosure. The number and order of other steps are within the scope of the present disclosure. In some embodiments, step S640 may be performed before step S630. In some embodiments, step S640 may be omitted.

Through the matrix vector operation circuit 100, 200, 500 and the circuit configuration method 600 of the present disclosure, the difference in resistance values between the resistor strings can be reduced, thereby improving the linearity of the output of the matrix vector operation circuit. In addition, the additional resistor in the resistor string can also prevent the resistor string from being quickly charged, thereby improving the performance of the matrix vector operation circuit.

The above is only the preferred embodiment of the present disclosure. Without departing from the scope or spirit of the present disclosure, the structure of the present disclosure can be modified and equivalently changed in various ways. In summary, all modifications and equivalent changes made to the present disclosure within the scope of the following claims are within the scope of the present disclosure.

100: Matrix vector operation circuit 110_1, 110_2, 110_M: resistor string 120: control circuit 200: Matrix vector operation circuit 210_1~210_5: resistor string 500: Matrix vector operation circuit 510_1, 510_2, 510_M: resistor string 600: circuit configuration method S610, S620, S630, S640: step IN: input signal IN ₁₁ , IN ₁₂ , IN _1M : input signal IN ₂₁ , IN ₂₂ , IN _2M : input signal IN ₃₁ , IN ₃₂ , IN _3M : input signal IN _N1 , IN _N2 , IN _NM : input signal W ₁₁ , W ₁₂ , W _1M : Weight unit W _21, W ₂₂ , W _2M : Weight unit W _31, W ₃₂ , W _3M : Weight unit W _41, W ₅₁ , W ₆₁ : Weight unit W _N1 , W _N2 , W _NM : Weight unit W _{11_1} ~ W _{11_5} : Weight unit W _{21_1} ~ W _{21_5} : Weight unit W _{31_1} ~ W _{31_5} : Weight unit W _{41_1} ~ W _{41_5} : Weight unit W _{51_1} ~ W _{51_5} : Weight unit W _{61_1} ~ W _{61_5} : Weight unit V _ref1 , V _ref2 : Reference voltage R _eq : Equivalent resistance R _S : Additional resistance

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure document more clearly understandable, the attached drawings are described as follows: Figure 1 is a schematic diagram of a matrix vector operation circuit drawn according to some embodiments of the present disclosure document; Figure 2 is a schematic diagram of the relationship between a matrix vector operation circuit and a weight value drawn according to some embodiments of the present disclosure document; Figure 3A is a schematic diagram of the configuration of the state value of the matrix vector operation circuit drawn according to some examples; Figure 3B is a schematic diagram of the configuration of the state value of the matrix vector operation circuit drawn according to some embodiments of the present disclosure document; Figure 3C is a schematic diagram of the configuration of the state value of the matrix vector operation circuit drawn according to some embodiments of the present disclosure document; FIG. 3D is a schematic diagram of the configuration of the state value of the matrix vector operation circuit according to some embodiments of the present disclosure document; FIG. 4 is a schematic diagram of the relationship between the equivalent resistance value and the estimated resistance value according to multiple configuration methods according to some embodiments of the present disclosure document; FIG. 5 is a schematic diagram of the matrix vector operation circuit according to some embodiments of the present disclosure document; and FIG. 6 is a flow chart of the circuit configuration method according to some embodiments of the present disclosure document.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Matrix vector operation circuit

110_1,110_2,110_M: resistor string

120: Control circuit

IN: Input signal

IN ₁₁ , IN ₁₂ , IN _1M : Input signal

IN ₂₁ , IN ₂₂ , IN _2M : Input signal

IN ₃₁ , IN ₃₂ , IN _3M : Input signal

IN _N1 , IN _N2 , IN _NM : Input signal

W ₁₁ ,W ₁₂ ,W _1M : weight unit

W _21, W ₂₂ , W _2M : weight unit

W _31, W ₃₂ , W _3M : weight unit

W _N1 ,W _N2 ,W _NM : weight unit

V _ref1 ,V _ref2 : reference voltage

R _eq : equivalent resistance

Claims (20)

A matrix vector operation circuit for presenting multiple weight values, the matrix vector operation circuit comprising: Multiple resistor strings, each comprising multiple weight units, wherein the multiple resistor strings are coupled in parallel between two reference voltages, and the multiple weight units of each resistor string are coupled in series between the two reference voltages, wherein the multiple weight units form multiple combinations, the multiple combinations correspond to the multiple weight values, the multiple weight units in each combination have a same order in the multiple resistor strings, wherein each weight unit has a state value, the multiple state values of the multiple weight units of the multiple combinations form multiple sequences, the multiple sequences correspond to the multiple weight values, and The multiple weight units corresponding to the multiple most significant bits of the multiple sequences are located in at least two of the multiple resistor strings. A matrix vector operation circuit as described in claim 1, wherein the weight units corresponding to the most significant bits of the odd sequences in the plurality of sequences are located in one of the plurality of resistor strings, and the weight units corresponding to the most significant bits of the even sequences in the plurality of sequences are located in another of the plurality of resistor strings, and wherein the odd sequences are different from the even sequences. A matrix vector operation circuit as described in claim 2, wherein the weight units corresponding to the most significant bits of the odd sequences and the weight units corresponding to the least significant bits of the even sequences are located in the same one of the resistor strings, and the weight units corresponding to the most significant bits of the even sequences and the weight units corresponding to the least significant bits of the odd sequences are located in another same one of the resistor strings. A matrix-vector operation circuit as described in claim 2, wherein the multiple weight units of the multiple combinations corresponding to the multiple odd-numbered sequences and the multiple weight units of the multiple combinations corresponding to the multiple even-numbered sequences are alternately arranged in the multiple resistor strings. A matrix-vector operation circuit as described in claim 1, wherein the multiple state values of the multiple weight units each belong to bit 0 or bit 1, and the multiple weight values respectively correspond to the number of weight units in the multiple combinations having the state value belonging to bit 1. A matrix-vector operation circuit as described in claim 5, wherein the multiple sequences belong to a unary code array, and each weight value corresponds to the number of consecutive bit 1s starting from the most significant bit in a corresponding one of the multiple sequences. A matrix-vector operation circuit as described in claim 6, wherein the weight unit corresponding to a least significant bit of one of the multiple sequences and the weight unit corresponding to the most significant bit of an adjacent one of the multiple sequences are located in the same one of the multiple resistor strings. The matrix vector operation circuit as described in claim 1 further includes a control circuit for generating multiple input signals to the multiple weight units respectively, wherein the multiple weight units each have a resistance value, and the resistance value is related to the state value and the multiple input signals. A matrix-vector operation circuit as described in claim 1, wherein each of the multiple resistor strings further includes an additional resistor, which is serially coupled to the multiple weight units to prevent the multiple resistor strings from undergoing rapid charging behavior. A matrix-vector operation circuit as described in claim 9, wherein the plurality of weight units and the additional resistor each have a resistance value, and the resistance value of the additional resistor is equal to or greater than the resistance value of the plurality of weight units. A circuit configuration method is used to configure a matrix vector operation circuit, wherein the matrix vector operation circuit includes a control circuit and a plurality of resistor strings coupled in parallel between two reference voltages, each of the plurality of resistor strings includes a plurality of weight units, and the plurality of weight units of each resistor string are coupled in series between the two reference voltages, wherein the circuit configuration method includes: Setting a plurality of weight values of the matrix vector operation circuit by the control circuit; Determining a plurality of sequences by the control circuit based on the plurality of weight values, wherein the plurality of sequences correspond to the plurality of weight values respectively; and Setting a state value of each weight unit by the control circuit based on the plurality of sequences, The plurality of weight units form a plurality of combinations corresponding to the plurality of weight values, the plurality of weight units in each combination have a same order in the plurality of resistor strings, and the plurality of weight units corresponding to the plurality of most significant bits of the plurality of sequences are located in at least two of the plurality of resistor strings. The circuit configuration method as described in claim 11, wherein determining the multiple sequences based on the multiple weight values by the control circuit includes: Dividing the multiple sequences into multiple odd sequences and multiple even sequences by the control circuit, wherein the multiple weight units corresponding to the multiple most significant bits of the multiple odd sequences are located in one of the multiple resistor strings, and the multiple weight units corresponding to the multiple most significant bits of the multiple even sequences are located in another one of the multiple resistor strings, and wherein the multiple odd sequences are different from the multiple even sequences. The circuit configuration method as described in claim 12, wherein the weight units corresponding to the most significant bits of the odd sequences and the weight units corresponding to the least significant bits of the even sequences are located in the same one of the resistor strings, and the weight units corresponding to the most significant bits of the even sequences and the weight units corresponding to the least significant bits of the odd sequences are located in another same one of the resistor strings. A circuit configuration method as described in claim 12, wherein the multiple weight units of the multiple combinations corresponding to the multiple odd-numbered sequences and the multiple weight units of the multiple combinations corresponding to the multiple even-numbered sequences are arranged alternately in the multiple resistor strings. The circuit configuration method as described in claim 11, wherein the state value of each weight unit is set by the control circuit based on the multiple sequences, including: The multiple state values of the multiple weight units are set to bit 0 or bit 1 respectively by the control circuit, wherein the multiple weight values correspond to the number of weight units having the state value belonging to bit 1 in the multiple combinations, respectively. A circuit configuration method as described in claim 15, wherein the multiple sequences belong to a unary coding array, and each weight value corresponds to the number of consecutive bit 1s starting from the most significant bit in a corresponding one of the multiple sequences. A circuit configuration method as described in claim 16, wherein the weight unit corresponding to a least significant bit of one of the multiple sequences and the weight unit corresponding to the most significant bit of an adjacent one of the multiple sequences are located in the same one of the multiple resistor strings. The circuit configuration method as described in claim 11, wherein each of the plurality of weight units has a resistance value, the resistance value is related to the state value, and the state value of each weight unit is set by the control circuit based on the plurality of sequences, including: Generating a plurality of input signals to the plurality of weight units by the control circuit to control the resistance value of each weight unit. The circuit configuration method as described in claim 11, wherein each of the plurality of resistor strings further comprises an additional resistor, and the additional resistor is coupled in series to the plurality of weight units, wherein the circuit configuration method further comprises: Setting a resistance value of the additional resistor by the control circuit to prevent the plurality of resistor strings from undergoing rapid charging behavior. A circuit configuration method as described in claim 19, wherein the multiple weight units each have a resistance value, and the resistance value of the additional resistor is equal to or greater than the resistance value of the multiple weight units.

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