TWI869130B - Memory structure, manufacturing method thereof, and operating method thereof - Google Patents

Abstract

A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.

Description

Memory structure, manufacturing method thereof and operation method thereof

The present disclosure relates to a memory structure, a method of manufacturing a memory structure, and a method of operating a memory structure.

Dynamic random access memory (DRAM) has the advantages of high density, low cost, and low power consumption, so it has been widely used. However, as memory technology gradually approaches physical limits, traditional DRAM (such as DRAM with one transistor and one capacitor (1T1C)) is facing many severe challenges in development. For example, DRAM size is not easy to be miniaturized, DRAM process tends to be complex, and the aspect ratio of capacitors increases significantly as the size is reduced. In view of the above, it is necessary to provide a new dynamic random access memory and its manufacturing method to overcome the above problems.

The present disclosure provides a memory structure, which includes a plurality of insulating layers, a plurality of gate layers, a first doped layer, a plurality of channel layers, a columnar channel, a plurality of second doped layers, a third doped layer, a fourth doped layer, a first dielectric layer, a plurality of second dielectric layers, a third dielectric layer, and a plurality of fourth dielectric layers. The insulating layers and the gate layers are alternately stacked. The first doped layer penetrates the insulating layers and the gate layers. The channel layers are each connected to the first doped layer, wherein the channel layers and the insulating layers are alternately stacked. The columnar channels penetrate the insulating layers and the gate layers. The second doped layers each surround the columnar channels, wherein the second doped layers each are connected to the channel layers. The third doped layer is coupled to the columnar channels. The fourth doped layer is coupled to the columnar channels. The first dielectric layer is disposed between the first doped layer and the gate layers. The second dielectric layers are each disposed between the second doped layers and the gate layers. The third dielectric layer is disposed between the columnar channel and the second doped layers. The fourth dielectric layers are respectively disposed between the channel layers and the gate layers.

In some implementations, the memory structure further includes a write bit line disposed on the first doped layer.

In some embodiments, the third doped layer is disposed under the columnar channel, and the fourth doped layer is disposed on the columnar channel.

In some implementations, the memory structure further includes a read bit line disposed on the fourth doped layer.

In some embodiments, the first doped layer and the second doped layers have a first conductivity type, the third doped layer and the fourth doped layer have a second conductivity type, and the first conductivity type is different from the second conductivity type.

In some implementations, the first conductivity type is N-type and the second conductivity type is P-type.

In some implementations, the first conductivity type is P-type and the second conductivity type is N-type.

In some embodiments, the channel layers have the second conductivity type and the columnar channels have the first conductivity type.

In some implementations, the first conductivity type is N-type and the second conductivity type is P-type.

In some embodiments, the channel layers and columnar channels are undoped.

The present disclosure provides a method for manufacturing a memory structure, which includes the following operations. A first hole is formed to penetrate a plurality of insulating layers and a plurality of first gate layers that are alternately stacked. A first dielectric layer is formed to cover the sidewalls of the first hole. A first doped layer is formed in the first hole. A second hole is formed to penetrate these insulating layers and these first gate layers. These first gate layers exposed from the second hole are partially removed to form a plurality of recessed portions. A plurality of second dielectric layers are formed in these recessed portions. A plurality of second doped layers are formed to cover these second dielectric layers. A third dielectric layer is formed in the second hole to cover the insulating layers and the second doped layers. A columnar channel is formed in the second hole. The first dielectric layer, the first gate layers and the second dielectric layers between the first doped layer and the second doped layers are removed to form a plurality of trenches. A plurality of channel layers are formed in the trenches to connect to the first doped layer and the second doped layers.

In some embodiments, after forming the columnar channels in the second holes, the channel layers are formed to connect to the first doped layer and the second doped layers.

In some implementations, the method for manufacturing a memory structure further includes: after forming the channel layers in the trenches, forming a plurality of fourth dielectric layers next to the channel layers; and forming a plurality of second gate layers next to the fourth dielectric layers.

In some embodiments, the method for manufacturing a memory structure further includes: forming a third doped layer in the substrate before forming the second hole through the insulating layers and the first gate layers, and forming the insulating layers and the first gate layers on the substrate, wherein the second hole exposes the third doped layer; and doping the top portion of the columnar channel to form a fourth doped layer.

In some implementations, the method for manufacturing a memory structure further includes: forming a write bit line on the first doped layer; and forming a read bit line on the fourth doped layer.

The present disclosure provides a method for operating a memory structure, which includes the following operations: receiving a memory structure of any of the aforementioned embodiments, wherein the gate layers, the first doping layer, the channel layers and the second doping layers form a plurality of write transistors, and the gate layers, the second doping layers, the third doping layer, the fourth doping layer and the columnar channels form a plurality of read transistors. A write operation is performed, the write operation comprising: applying a first voltage to the selection gates of the gate layers of the write transistors, wherein the first voltage is higher than the threshold voltage of the selection gate; and applying a second voltage to the first doped layers of the write transistors to charge or not charge one of the second doped layers corresponding to the selection gates, wherein the second voltage is a positive voltage or 0V.

In some implementations, the write transistors are N-type transistors and the read transistors are P-type transistors.

In some embodiments, the operating method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are negative voltages; and applying a fifth voltage to the third doped layer, wherein the fifth voltage is a positive voltage.

In some implementations, the write transistors are P-type transistors and the read transistors are N-type transistors.

In some embodiments, the operating method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are positive voltages; and applying a fifth voltage to the third doped layer, wherein the fifth voltage is a positive voltage.

The following multiple implementations are described and disclosed in detail with the attached drawings. For clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the content of this disclosure. In other words, in some implementations of the content of this disclosure, these practical details are not necessary. In addition, to simplify the drawings, some known structures and components will be shown in schematic form in the drawings.

In this article, it is understandable to use the terms first, second, and third, etc. to describe various elements, components, regions, layers, and/or blocks. However, these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer, and/or block. Therefore, a first element, component, region, layer, and/or block in the following text may also be referred to as a second element, component, region, layer, and/or block without departing from the original intention of the present disclosure.

In addition, it should be understood that when element A is referred to as being “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (for example, an intermediate element C (and/or other elements) may be disposed between element A and element B).

The present disclosure provides a memory structure, which is a three-dimensional (3D) dynamic random access memory (DRAM) structure. The memory structure includes a plurality of memory cells, each memory cell includes a write transistor and a read transistor to form a 2T0C DRAM structure. The memory structure of the present disclosure has a high density of memory cells, so it is beneficial to miniaturize the size of the memory structure. In addition, the process of manufacturing the memory structure is simple, so the manufacturing cost can be reduced, thereby replacing the traditional 1T1C DRAM structure.

FIG. 1 is a three-dimensional schematic diagram of a memory structure according to various embodiments of the present disclosure. FIG. 2 is a cross-sectional schematic diagram of a memory structure according to various embodiments of the present disclosure. FIG. 3 is a cross-sectional schematic diagram along the section line A-A' of FIG. 2. FIG. 4 is a cross-sectional schematic diagram along the section line B-B' of FIG. 2. As shown in FIGS. 1 to 4 , the memory structure 100 includes a substrate 110, an isolation structure STI, a plurality of gate layers 120, a plurality of insulating layers 130, a first doping layer SD1, a plurality of second doping layers SD2, a plurality of channel layers CL, a third doping layer SD3, a fourth doping layer SD4, a columnar channel CC, a first dielectric layer DL1, a plurality of second dielectric layers DL2, a third dielectric layer DL3, and a plurality of fourth dielectric layers DL4.

In some embodiments, the substrate 110 is a semiconductor substrate. In some embodiments, the substrate 110 includes any suitable semiconductor material and/or semiconductor material used to form a semiconductor structure. The semiconductor material includes, for example, one or more materials, such as crystalline silicon, silicon oxide, strained silicon, germanium silicon, doped or undoped polysilicon, doped or undoped silicon wafer, germanium, gallium arsenide, other suitable semiconductor materials or combinations thereof. In some embodiments, the substrate 110 is a silicon substrate. In some embodiments, the gate layer 120 includes a metal conductive material, a non-metal conductive material or a combination thereof, such as tungsten, copper, aluminum, gold, silver, other suitable metals, metal alloys, polysilicon or a combination thereof. In some embodiments, the insulating layer 130 includes an oxide, a nitride or a combination thereof, such as silicon dioxide, silicon nitride or a combination thereof. In some embodiments, the isolation structure STI is a shallow trench isolation (STI).

Please refer to FIG. 1 and FIG. 2 simultaneously. The insulating layer 130 and the gate layer 120 are alternately stacked. The number of the insulating layer 130 and the gate layer 120 can be adjusted arbitrarily and is not limited thereto. The first doped layer SD1 penetrates the insulating layer 130 and the gate layer 120. The channel layers CL are each connected to the first doped layer SD1, wherein the channel layers CL and the insulating layer 130 are alternately stacked. The columnar channel CC penetrates the insulating layer 130 and the gate layer 120. As shown in FIG. 2 and FIG. 3 , the second doped layer SD2 surrounds the columnar channel CC, wherein the second doped layer SD2 is connected to the channel layer CL. Therefore, the gate layer 120, the first doped layer SD1, the channel layer CL and the second doped layer SD2 form a plurality of write transistors. The gate layer 120 may also be referred to as a control gate. As shown in FIG. 2 , the first doped layer SD1 includes a first portion P1 and a second portion P2 connected to each other, wherein the first portion P1 penetrates the insulating layer 130 and the gate layer 120, and the second portion P2 is located in the substrate 110. As shown in FIG. 3 , each gate layer 120 includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 surrounds the first doped layer SD1, the second doped layer SD2 and the columnar channel CC. The second gate layer G2 is located on both sides of the channel layer CL. In some embodiments, the first doped layer SD1 is a source and the second doped layer SD2 is a drain. In other embodiments, the first doped layer SD1 is a drain and the second doped layer SD2 is a source.

Please continue to refer to FIG. 2 and FIG. 3, the third doped layer SD3 is coupled to the columnar channel CC, and the fourth doped layer SD4 is coupled to the columnar channel CC. In some embodiments, as shown in FIG. 2, the third doped layer SD3 is disposed under the columnar channel CC, and the fourth doped layer SD4 is disposed on the columnar channel CC, but the arrangement is not limited thereto. In some embodiments, the third doped layer SD3 is a source, and the fourth doped layer SD4 is a drain. In other embodiments, the third doped layer SD3 is a drain, and the fourth doped layer SD4 is a source. The gate layer 120, the second doping layer SD2, the third doping layer SD3, the fourth doping layer SD4 and the columnar channel CC form a plurality of read transistors. As shown in FIG. 2, these read transistors are connected to each other in the vertical direction. As shown in FIG. 3, the columnar channel CC of the read transistor is surrounded by the second doping layer SD2 and the gate layer 120, and the second doping layer SD2 and the gate layer 120 serve as the gate of the read transistor. The second doping layer SD2 is annular. A write operation can be performed by applying a gate voltage to a write transistor and applying a voltage or no voltage to the first doped layer SD1 so that the corresponding second doped layer SD2 surrounding the columnar channel CC has a high potential or a low potential. Thus, data 1 or data 0 is written into the read transistor. The second doped layer SD2 can store charge and is chargeable or dischargeable. The potential of the second doped layer SD2 can be adjusted by charging or discharging the second doped layer SD2. The second doped layer SD2 can also be called a storage node SN (SN), a floating gate (FG) or a gate node. The operation method of the memory structure will be further explained with a circuit diagram later.

As shown in FIGS. 2 to 4 , the first dielectric layer DL1 is disposed between the first doped layer SD1 and the gate layer 120 and between the first doped layer SD1 and the insulating layer 130, so that the gate layer 120 is electrically isolated from the first doped layer SD1. The second dielectric layer DL2 is disposed between the second doped layer SD2 and the gate layer 120, so that the gate layer 120 is electrically isolated from the second doped layer SD2. The third dielectric layer DL3 is disposed between the columnar channel CC and the second doped layer SD2 and between the columnar channel CC and the insulating layer 130, so that the columnar channel CC is electrically isolated from the second doped layer SD2. The third dielectric layer DL3 is annular. The fourth dielectric layer DL4 is respectively disposed between the channel layer CL and the gate layer 120, so that the gate layer 120 is electrically isolated from the channel layer CL. Please refer to FIG. 1 and FIG. 2 again. In some embodiments, the third dielectric layer DL3 is disposed between the fourth doped layer SD4 and one of the insulating layers 130. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include a gate oxide. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials, or combinations thereof.

Please refer to Figures 2 and 3 again. In some embodiments, the first doping layer SD1 and the second doping layer SD2 have a first conductivity type, and the third doping layer SD3 and the fourth doping layer SD4 have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N type, and the second conductivity type is P type. The write transistor including the first doping layer SD1 and the second doping layer SD2 is an N-type transistor, such as an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), and the read transistor including the third doping layer SD3 and the fourth doping layer SD4 is a P-type transistor, such as a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET). In some embodiments, the channel layer CL has the second conductivity type, and the columnar channel CC has the first conductivity type. In other embodiments, the channel layer CL and the columnar channel CC are undoped. In some embodiments, the first doped layer SD1 and the second doped layer SD2 are N+ doped regions, the channel layer CL is a P- doped region or an undoped silicon layer, the third doped layer SD3 and the fourth doped layer SD4 are P+ doped regions, and the columnar channel CC is an N- doped region.

In other embodiments, the first conductivity type is P type and the second conductivity type is N type. The write transistor including the first doping layer SD1 and the second doping layer SD2 is a P type transistor, such as a PMOSFET, and the read transistor including the third doping layer SD3 and the fourth doping layer SD4 is an N type transistor, such as an NMOSFET. In some embodiments, the channel layer CL has the second conductivity type and the columnar channel CC has the first conductivity type. In some embodiments, the channel layer CL and the columnar channel CC are undoped.

In some embodiments, the channel layer CL and the columnar channel CC are each made of silicon, germanium, polysilicon, semiconductor oxide (eg, indium oxide (In ₂ O ₃ ), indium gallium zinc oxide (IGZO), indium tin oxide (ITO)) or other suitable III-V materials.

The present disclosure provides a method for manufacturing a memory structure, see FIG. 3 and FIG. 5A to FIG. 6I. FIG. 5A and FIG. 5B are flow charts of a method 500 for manufacturing a memory structure according to various embodiments of the present disclosure. The manufacturing method 500 includes operations 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, and 544. FIG. 6A to FIG. 6I are cross-sectional schematic diagrams of intermediate stages of manufacturing a memory structure according to various embodiments of the present disclosure. The above operations 512 to 544 will be described below with reference to FIGS. 6A to 6I and FIG. 3. Although a series of operations or steps are used to illustrate the method disclosed herein, the order in which these operations or steps are shown should not be interpreted as a limitation of the present disclosure. For example, certain operations or steps may be performed in a different order and/or simultaneously with other steps. In addition, it is not necessary to perform all of the operations, steps and/or features shown in order to implement the present disclosure. In addition, each operation or step described herein may include a plurality of sub-steps or actions.

In operation 512, as shown in FIG. 6A, a first portion P1 of the first doped layer SD1 and a third doped layer SD3 are formed in the substrate 110. The first portion P1 of the first doped layer SD1 and the third doped layer SD3 are electrically isolated by an isolation structure STI embedded in the substrate 110. In some embodiments, the first portion P1 of the first doped layer SD1 and the third doped layer SD3 are each formed by doping a portion of the substrate 110. In operation 514, as shown in FIG. 6A, a plurality of insulating layers 130 and a plurality of first gate layers G1 are alternately stacked on the substrate 110. In operation 516, as shown in FIG6A, a first hole H1 is formed through the insulating layer 130 and the first gate layer G1 to expose the first portion P1 of the first doped layer SD1. In some embodiments, the first hole H1 is formed by an etching process.

In operation 518, as shown in FIG. 6B, a first dielectric layer DL1 is formed to cover the sidewall SW of the first hole H1. In operation 520, as shown in FIG. 6B, a second portion P2 of the first doped layer SD1 is formed in the first hole H1. In some embodiments, the second portion P2 of the first doped layer SD1 is formed by a deposition process. In some embodiments, the first doped layer SD1 has a first conductivity type, and the third doped layer SD3 has a second conductivity type, and the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

In operation 522, as shown in FIG. 6C, a second hole H2 is formed to penetrate the insulating layer 130 and the first gate layer G1. The second hole H2 exposes the third doping layer SD3. In some embodiments, the second hole H2 is formed by an etching process. In operation 524, as shown in FIG. 6D, the first gate layer G1 exposed from the second hole H2 is partially removed. After operation 524, the sidewall of the second hole H2 has a plurality of recessed portions RP. In some embodiments, the partial removal of the first gate layer G1 is performed by a wet etching process.

In operation 526, as shown in FIG. 6E, a plurality of second dielectric layers DL2 are formed in the recess RP to cover the partially removed first gate layer G1. Specifically, each of the second dielectric layers DL2 is formed in the recess RP and does not fill the recess RP. In operation 528, as shown in FIG. 6F, a plurality of second doping layers SD2 are formed to cover the second dielectric layer DL2. Specifically, each of the second doping layers SD2 is formed in the recess RP and fills the recess RP. In operation 530, as shown in FIG. 6F, a third dielectric layer DL3 is formed in the second hole H2 to cover the insulating layer 130 and the second doping layer SD2. The third dielectric layer DL3 does not fill up the second hole H2. In operation 532, as shown in FIG. 6F, a columnar channel CC is formed in the second hole H2. The columnar channel CC fills up the second hole H2.

In operation 534, as shown in FIG. 6G, the first dielectric layer DL1, the first gate layer G1, and the second dielectric layer DL2 between the first doping layer SD1 and the second doping layer SD2 are removed to form a plurality of trenches T. Specifically, a plurality of portions of the first dielectric layer DL1, a plurality of portions of the first gate layer G1, and a plurality of portions of the second dielectric layer DL2 are removed to form the trenches T. In operation 536, as shown in FIG. 6H, a plurality of channel layers CL are formed in the trenches T to connect to the first doping layer SD1 and the second doping layer SD2. See FIG. 3 for a cross section along the section line A-A'. In some embodiments, the channel layer CL is formed by a deposition process. In some embodiments, as shown in FIGS. 6F to 6H, operations 528, 530, 532, 534, and 536 are sequentially performed. After forming the columnar channel CC in the second hole H2, a channel layer CL is formed to connect to the first doping layer SD1 and the second doping layer SD2. In other embodiments, after forming the channel layer CL to connect to the first doping layer SD1 and the second doping layer SD2, a columnar channel CC is formed in the second hole H2. In operation 538, as shown in FIG. 3, a plurality of fourth dielectric layers DL4 are formed next to the channel layer CL. In operation 540, as shown in FIG. 3, a plurality of second gate layers G2 are formed next to the fourth dielectric layer DL4. In operation 542, as shown in FIG. 6H, the top portion of the columnar channel CC is doped to form a fourth doping layer SD4.

In operation 544, as shown in FIG6I, a write bit line WBL is formed on the first doping layer SD1 and a read bit line RBL is formed on the fourth doping layer SD4. The difference between the memory structure 1400 of FIG6I and the memory structure 100 of FIG2 is that the memory structure 1400 further includes a write bit line WBL disposed on the first doping layer SD1 and a read bit line RBL disposed on the fourth doping layer SD4.

The present disclosure provides a method for operating a memory structure, which includes the following operations. A memory structure of any of the above-mentioned embodiments, such as the memory structure 1400, is received and a write operation is performed. Referring to FIG. 6I, in the memory structure 1400, the gate layer 120, the first doping layer SD1, the channel layer CL and the second doping layer SD2 form a plurality of write transistors. In addition, the gate layer 120, the second doping layer SD2, the third doping layer SD3, the fourth doping layer SD4 and the columnar channel CC form a plurality of read transistors. FIG. 7 is a circuit diagram of a memory array according to various embodiments of the present disclosure. Circuit 1500 is an equivalent circuit diagram of memory structure 1400. FIG. 8 is a circuit diagram of a memory cell MC and its surrounding circuits according to various implementations of the present disclosure. Memory cell MC includes a write transistor WT and a read transistor RT. It can be seen that the memory array of FIG. 7 includes multiple memory cells.

Referring to FIG. 7 , the memory array includes a plurality of write word lines (WWL), a plurality of write bit lines (WBL), a plurality of read word lines (RWL), and a plurality of read bit lines (RBL). The write word lines include write word lines WWL0, WWL1, … WWLn. The write bit lines include write bit lines WBL0, … WBLn. The read word lines include read word lines RWL0, … RWLn. The read bit lines include read bit lines RBL0, … RBLn. The write word lines and the write bit lines are arranged alternately. As shown in FIG. 6I , the read transistors are connected to each other vertically, so in circuit 1500 , the read word line RWL0 and the read bit line RBL0 are connected to the first and last of these read transistors.

Please refer to FIG. 6I and FIG. 8 simultaneously. FIG. 8 shows an equivalent circuit diagram of a memory cell in the memory structure 1400. The memory cell MC includes a write transistor WT and a read transistor RT. The write transistor WT is coupled to the write word line WWL, and the first doping layer SD1 is coupled to the write bit line WBL. A second doping layer SD2 serves as a storage node SN of the read transistor RT, and the storage node SN is also a floating gate FG. The read transistor RT is coupled to the read word line RWL and the read bit line RBL.

Please refer to Figures 6I to 8 at the same time. The write operation includes the following operations. Apply a first voltage to a selection gate of a gate layer 120 of a plurality of write transistors. The first voltage is higher than the threshold voltage of the selection gate. The gate layer 120 includes a selection gate and a plurality of unselected gates, wherein the selection gate is a gate to which the first voltage is applied, and the unselected gate is a gate to which the first voltage is not applied. In other words, the first voltage is applied only to the selected write word line, and the first voltage is not applied to other write word lines. A second voltage is applied to the first doped layers SD1 of the write transistors to charge or not charge one of the corresponding selection gates in the second doped layers SD2, wherein the second voltage is a positive voltage or 0V.

Please refer to the memory cell MC in Figure 8. The logical state of the memory cell MC depends on whether the storage node SN of the read transistor RT stores charge. In other words, the logical state depends on whether the storage node SN is at a high potential or a low potential. In some embodiments, the write transistor WT is an N-type transistor and the read transistor RT is a P-type transistor. Figure 9 is a current-voltage diagram of the write transistor according to various embodiments of the present disclosure, wherein the write transistor is an N-type transistor. When a write operation is performed, the gate voltage is higher than the threshold voltage, and the write transistor WT is in an on state. When performing a read operation, the gate voltage is 0V or lower than the threshold voltage, and the write transistor WT is in the off state. FIG. 10 is a current-voltage diagram of a read transistor according to various embodiments of the present disclosure, wherein the read transistor is a P-type transistor. The magnitude of the current depends on the voltage of the storage node SN of the read transistor RT. In FIG. 10, the current higher than I _sense is I _read1 , and I _read1 corresponds to data 1. The current lower than I _sense is I _read0 , and I _read0 corresponds to data 0.

When data 0 is to be written to a P-type transistor, a first voltage is applied to one of the gate layers 120 of the N-type transistor, and a second voltage (positive voltage) is applied to the first doping layer SD1 of the N-type transistor. Therefore, the storage node SN (second doping layer SD2) of the P-type transistor is charged, so that the storage node SN is at a high potential. When the storage node SN of the P-type transistor is at a high potential, the P-type transistor is in a closed state. Therefore, during the read operation, no current flows through the P-type transistor or only a current less than I _sense flows through the P-type transistor.

When data 1 is to be written to a P-type transistor, a first voltage is applied to one of the gate layers 120 of the N-type transistor, and a second voltage (0V) is applied to the first doping layer SD1 of the N-type transistor. Since the storage node SN (second doping layer SD2) of the P-type transistor is not charged, the storage node SN is at a low potential. When the storage node SN of the P-type transistor is at a low potential, the P-type transistor is in an on state, so during a read operation, a current of the P-type transistor, such as a current higher than I _sense, is measured.

Please refer to Figures 6I to 8 and 10 at the same time. In some embodiments, the operating method of the memory structure further includes: performing a read operation. In the memory structure 1400, the write transistor is an N-type transistor, and the read transistor is a P-type transistor. The read operation includes: applying a third voltage to the selection gate of the N-type transistor, the third voltage is 0V or lower than the threshold voltage of the selection gate. Therefore, the selection gate is in a closed state. Applying a plurality of fourth voltages to a plurality of unselected gates of the gate layer 120 of the N-type transistor, the fourth voltage is a negative voltage, so that the unselected gates are in a closed state. A fifth voltage is applied to the third doped layer SD3 of the P-type transistor, and the fifth voltage is a positive voltage, so as to measure the current value of the P-type transistor. If the current value is higher than I _sense , it can be known that the P-type transistor stores data 1. If the current value is lower than I _sense , it can be known that the P-type transistor stores data 0.

Next, an operation method of the memory structure is described by way of example with an embodiment. Please refer to FIG. 6I, FIG. 7 and Table 1 below. In the memory array, the write transistor is an N-type transistor and the read transistor is a P-type transistor. When writing data 0, a voltage of 3V is applied to the selected write word line and the write bit line respectively, and no voltage is applied to the unselected write word line, read word line and read bit line. When writing data 1, a gate voltage of 3V is applied to the selected write word line, and no voltage is applied to the unselected write word line, write bit line, read word line and read bit line. When reading, no voltage is applied to the selected write word line, so that the write transistor coupled to the selected write word line is in the off state. A negative voltage is applied to the unselected write word line to achieve the following two purposes. Purpose (1) is to turn off the write transistor coupled to the unselected write word line. Purpose (2) is as follows. From Figure 6I, it can be seen that these read transistors on the right are adjacent to the gate layer 120, so they are also controlled by negative voltage. Since the read transistors are P-type transistors, the channels of these read transistors are in the open state, allowing current to flow through. In addition, when reading, a 1V voltage is applied to the read word line, and the current size depends on the storage node voltage of the read transistor. Table 1 Write data 0 Write data 1 Read Selected write word line 3V 3V 0V Unselected write word lines 0V 0V -3V Write bit line 3V 0V 0V Read character line 0V 0V 1V Read bit line 0V 0V 0V

Please refer to Figures 6I to 8 and 10 at the same time. In other embodiments, the write transistor is a P-type transistor and the read transistor is an N-type transistor. The operating principle of this embodiment can be inferred by referring to the principle of the aforementioned embodiment (the write transistor is an N-type transistor and the read transistor is a P-type transistor), which will not be repeated. In some embodiments, the operating method of the memory structure further includes: performing a read operation. The read operation includes: applying a third voltage to the selection gate of the P-type transistor, the third voltage is 0V or lower than the threshold voltage of the selection gate. Therefore, the selection gate is in a closed state. A plurality of fourth voltages are applied to a plurality of unselected gates of the gate layer 120 of the P-type transistor. The fourth voltage is a positive voltage, so the unselected gates are in a closed state. A fifth voltage is applied to the third doped layer SD3 of the N-type transistor, and the fifth voltage is a positive voltage, thereby measuring the current value of the N-type transistor.

Based on the above, the present disclosure provides a memory structure, a manufacturing method thereof, and an operating method thereof. In the memory structure, the read transistors are connected to each other in the vertical direction, so that the density of the memory unit can be increased, which is beneficial to the miniaturization of the memory structure. In addition, the manufacturing method of the present disclosure has a simple process, so the manufacturing cost can be reduced.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the attached patent applications.

100: memory structure 110: substrate 120: gate layer 130: insulating layer 500: manufacturing method 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544: operation 1400: memory structure 1500: circuit A-A’, B-B’: section line CC: columnar channel CL: channel layer DL1: first dielectric layer DL2: second dielectric layer DL3: third dielectric layer DL4: fourth dielectric layer FG: floating gate G1: First gate layer G2: Second gate layer H1: First hole H2: Second hole P1: First part P2: Second part RBL, RBL0, RBLn: Read bit line RP: Recess RWL, RWL0, RWLn: Read word line RT: Read transistor MC: Memory cell SD1: First doping layer SD2: Second doping layer SD3: Third doping layer SD4: Fourth doping layer SN: Storage node STI: Isolation structure SW: Sidewall T: Trench WBL, WBL0, WBLn: Write bit line WT: Write transistor WWL, WWL0, WWL1, WWLn: write character line

By reading the detailed description of the following implementation methods and referring to the attached figures, the present disclosure can be more fully understood. FIG. 1 is a three-dimensional schematic diagram of a memory structure according to various implementation methods of the present disclosure. FIG. 2 is a cross-sectional schematic diagram of a memory structure according to various implementation methods of the present disclosure. FIG. 3 is a cross-sectional schematic diagram along the section line A-A' of FIG. 2. FIG. 4 is a cross-sectional schematic diagram along the section line B-B' of FIG. 2. FIG. 5A and FIG. 5B are flow charts of a method for manufacturing a memory structure according to various implementation methods of the present disclosure. FIG. 6A to FIG. 6I are cross-sectional schematic diagrams of intermediate stages of manufacturing a memory structure according to various implementation methods of the present disclosure. FIG. 7 is a circuit diagram of a memory array according to various embodiments of the present disclosure. FIG. 8 is a circuit diagram of a memory cell and its surrounding circuits according to various embodiments of the present disclosure. FIG. 9 is a current-voltage diagram of a write transistor according to various embodiments of the present disclosure. FIG. 10 is a current-voltage diagram of a read transistor according to various embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

1400:Memory structure

110: Substrate

120: Gate layer

130: Insulation layer

CC: Columnar Channel

CL: Channel layer

DL1: First dielectric layer

DL2: Second dielectric layer

DL3: The third dielectric layer

G1: First gate layer

P1: Part 1

P2: Part 2

RBL: Read Bit Line

SD1: First doping layer

SD2: Second doping layer

SD3: The third doping layer

SD4: Fourth doping layer

STI: Isolation Structure

WBL: Write Bit Line

Claims (19)

A memory structure includes: a plurality of insulating layers and a plurality of gate layers stacked alternately; a first doped layer penetrating the insulating layers and the gate layers; a plurality of channel layers, each connected to the first doped layer, wherein the channel layers and the insulating layers are stacked alternately; a columnar channel penetrating the insulating layers and the gate layers; a plurality of second doped layers, each surrounding the columnar channel, wherein the second doped layers are each connected to the channel layers; a A third doped layer coupled to the columnar channel; a fourth doped layer coupled to the columnar channel; a first dielectric layer disposed between the first doped layer and the gate layers; a plurality of second dielectric layers, each disposed between the second doped layers and the gate layers; a third dielectric layer disposed between the columnar channel and the second doped layers and the insulating layers; and a plurality of fourth dielectric layers, each disposed between the channel layers and the gate layers. The memory structure as described in claim 1 further includes a write bit line disposed on the first doped layer. A memory structure as described in claim 1, wherein the third doped layer is disposed under the columnar channel, and the fourth doped layer is disposed on the columnar channel. The memory structure as described in claim 3 further includes a read bit line disposed on the fourth doped layer. A memory structure as described in any one of claim 1 to claim 4, wherein the first doped layer and the second doped layers have a first conductivity type, the third doped layer and the fourth doped layer have a second conductivity type, and the first conductivity type is different from the second conductivity type. A memory structure as described in claim 5, wherein the first conductivity type is N-type and the second conductivity type is P-type. A memory structure as described in claim 5, wherein the first conductivity type is P type and the second conductivity type is N type. A memory structure as described in claim 5, wherein the channel layers have the second conductivity type and the columnar channel has the first conductivity type. A memory structure as described in claim 8, wherein the first conductivity type is N-type and the second conductivity type is P-type. A memory structure as described in claim 1, wherein the channel layers and the columnar channels are undoped. A method for manufacturing a memory structure includes: forming a third doped layer in a substrate; forming a plurality of insulating layers and a plurality of first gate layers stacked alternately on the substrate; forming a first hole penetrating the insulating layers and the first gate layers; forming a first dielectric layer covering a side wall of the first hole; forming a first doped layer in the first hole, wherein the first dielectric layer is disposed between the first doped layer and the first gate layer; The invention relates to a method for forming a first gate layer and a second dielectric layer between the insulating layers; forming a second hole penetrating the insulating layers and the first gate layers to expose the third doped layer; partially removing the first gate layers exposed from the second hole to form a plurality of recessed portions; forming a plurality of second dielectric layers in the recessed portions; forming a plurality of second doped layers covering the second dielectric layers, wherein the second dielectric layers are respectively disposed between the second doped layers and the gate layers; The invention relates to a method for forming a first dielectric layer, a second dielectric layer, a first gate layer, and a second doped layer in the second hole to cover the insulating layers and the second doped layers; a columnar channel is formed in the second hole to couple to the third doped layer, wherein the third dielectric layer is disposed between the columnar channel and the second doped layers and the insulating layers; and the first dielectric layer, the first gate layer, and the second doped layer are removed. Second dielectric layers are formed to form a plurality of trenches; a plurality of channel layers are formed in the trenches to connect to the first doped layer and the second doped layers; a plurality of fourth dielectric layers are formed beside the channel layers, wherein the fourth dielectric layers are respectively disposed between the channel layers and the gate layers; and a top portion of the columnar channel is doped to form a fourth doped layer, wherein the fourth doped layer is coupled to the columnar channel. A method for manufacturing a memory structure as described in claim 11, wherein after forming the columnar channel in the second hole, the channel layers are formed to connect to the first doped layer and the second doped layers. The manufacturing method of the memory structure as described in claim 11 further includes: after forming the channel layers in the trenches, forming a plurality of second gate layers next to the fourth dielectric layers. The method for manufacturing the memory structure as described in claim 11 further includes: forming a write bit line on the first doped layer; and forming a read bit line on the fourth doped layer. A method for operating a memory structure, comprising: receiving the memory structure as described in claim 1, wherein the gate layers, the first doping layer, the channel layers and the second doping layers form a plurality of write transistors, and the gate layers, the second doping layers, the third doping layer, the fourth doping layer and the columnar channel form a plurality of read transistors; and performing a write operation, The write operation includes: applying a first voltage to a selection gate of the gate layers of the write transistors, wherein the first voltage is higher than a threshold voltage of the selection gate; and applying a second voltage to the first doped layer of the write transistors to charge or not charge one of the second doped layers corresponding to the selection gate, wherein the second voltage is a positive voltage or 0V. The method for operating a memory structure as described in claim 15, wherein the write transistors are N-type transistors and the read transistors are P-type transistors. The operating method of the memory structure as described in claim 16 further includes: performing a read operation, the read operation including: applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are negative voltages; and applying a fifth voltage to the third doped layer, wherein the fifth voltage is a positive voltage. The operating method of the memory structure as described in claim 15, wherein the write transistors are P-type transistors and the read transistors are N-type transistors. The operating method of the memory structure as described in claim 18 further includes: performing a read operation, the read operation including: applying a third voltage to the selection gate, wherein the third voltage is 0V or lower than the threshold voltage of the selection gate; applying a plurality of fourth voltages to a plurality of unselected gates of the gate layers of the write transistors, wherein the fourth voltages are positive voltages; and applying a fifth voltage to the third doped layer, wherein the fifth voltage is a positive voltage.

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