TWI867792B - Thin film transistor substrate and electronic device comprising same - Google Patents

Abstract

A thin film transistor substrate includes: a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes active regions, and the first insulating layer includes first openings. The gate pattern overlaps the active area, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first openings in the first insulating layer.

Description

Thin film transistor substrate and electronic device including the same

The present invention relates to a semiconductor technology, in particular to a thin film transistor substrate.

Liquid crystal display (LCD) has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (CRT), and is widely used in information products such as notebook computers, personal digital assistants (PDA), flat-screen TVs, or mobile phones. However, large-size LCDs have the disadvantage of insufficient pixel charging due to excessive scan line loading.

The present disclosure provides a thin film transistor substrate and an electronic device comprising the same.

According to some embodiments of the present disclosure, a thin film transistor substrate is provided. The thin film transistor substrate includes: a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening of the first insulating layer.

According to some embodiments of the present disclosure, an electronic device including a thin film transistor substrate is provided. The thin film transistor substrate includes: a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening of the first insulating layer.

The following is a detailed description of the electronic device of the disclosed embodiment. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the disclosed embodiment. The specific components and arrangements described below are only for the purpose of simply and clearly describing some embodiments of the disclosed embodiment. Of course, these are only used for exemplification and are not limitations of the disclosed embodiment. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing some embodiments of the disclosed embodiment, and do not represent any correlation between the different embodiments and/or structures discussed.

Here, the terms "about", "approximately", and "generally" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meaning of "about", "approximately", and "generally" can still be implied. Here, the term "a to b" means greater than or equal to a and less than or equal to b.

It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions, layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or part discussed below may be referred to as a second element, component, region, layer, and/or part without departing from the teachings of some embodiments of the present disclosure.

In some embodiments of the present disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientation shown in the paragraph and related drawings. This relative terminology is only for the convenience of explanation and does not mean that the device described therein needs to be manufactured or operated in a specific orientation. It is understood that if the device in the attached figure is turned upside down, the elements described on the "lower" side will become elements on the "upper" side. The embodiments of the present disclosure can be understood in conjunction with the attached figures, and the attached figures of the present disclosure are also considered part of the specification. It should be understood that the attached figures of the present disclosure are not drawn according to scale. In fact, the size of the elements may be arbitrarily enlarged or reduced in order to clearly show the characteristics of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

Certain terms are used in the specification and the attached patent claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and patent claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to..."

The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a touch display, a packaging device, a curved display, or a non-rectangular display, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. The packaging device may be a packaging device suitable for wafer-level package (WLP) technology or panel-level package (PLP) technology, such as a chip first process or a chip later process (RDL first) process. It should be noted that the electronic device may be any combination of the aforementioned arrangements, but is not limited thereto. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may include electronic components. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device, or a splicing device.

FIG1 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG2 is a partial cross-sectional schematic diagram of the thin film transistor substrate shown in FIG1 taken along line I-I'. The thin film transistor substrate of the present disclosure includes a substrate 10, a first metal layer 11 disposed on the substrate 10, a second metal layer 13 disposed on the first metal layer 11, a semiconductor 15 disposed between the substrate 10 and the first metal layer 11, and a first insulating layer 17 disposed between the first metal layer 11 and the second metal layer 13. The first metal layer 11 includes a gate pattern 111, the second metal layer 13 includes a scan line pattern 131, the semiconductor 15 includes an active region 151G, and the first insulating layer 17 includes a first opening VH1. The gate pattern 111 may overlap the active region 151G, and the thin film transistor 20 includes the semiconductor 15 and the gate pattern 111. The scanning line pattern 131 of the second metal layer 13 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17. In some embodiments, the thin film transistor substrate may further include a light shielding layer 12 disposed between the substrate 10 and the semiconductor 15, and the light shielding layer 12 may overlap the active region 151G. In some embodiments, the thin film transistor substrate may further include a second insulating layer 19 disposed on the second metal layer 13, a first electrode layer 31 disposed on the second insulating layer 19, a second electrode layer 33 disposed on the first electrode layer 31, and a third insulating layer 35 disposed between the first electrode layer 31 and the second electrode layer 33, as shown in Figures 1 and 2. "Overlap" herein refers to overlapping in the normal direction of the substrate.

The material of the second insulating layer 19 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The second insulating layer 19 may have a single-layer structure or a multi-layer stacked structure. For example, the second insulating layer 19 may include a single-layer silicon oxide, or the second insulating layer 19 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto. In some embodiments, the second insulating layer 19 may include a third opening VH3 that exposes a portion of the second metal layer 13 .

The first electrode layer 31 is disposed on the second insulating layer 19 and may include a fourth opening VH4. In some embodiments, the fourth opening VH4 may be larger than the third opening VH3 and may be located in the fourth opening VH4 together with the third opening VH3. In some embodiments, the fourth opening VH4 may expose a portion of the second metal layer 13. The material of the first electrode layer 31 may include a transparent conductive metal oxide. Examples of the transparent conductive metal oxide may include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), fluorine-doped tin oxide, graphene nanoribbons, or metal nanowires, but the present disclosure is not limited thereto.

The material of the third insulating layer 35 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The third insulating layer 35 may have a single-layer structure or a multi-layer stacked structure. For example, the third insulating layer 35 may include a single-layer silicon nitride, or the third insulating layer 35 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto. The third insulating layer 35 may have a fifth opening VH5. In some embodiments, the fifth opening VH5 may be smaller than the fourth opening VH4 and the third opening VH3 and be located in the third opening VH3 and the fourth opening VH4, as shown in FIG2. The fifth opening VH5 may expose a portion of the second metal layer 13.

The material of the second electrode layer 33 may include a transparent conductive metal oxide. Examples of the transparent conductive metal oxide may include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), fluorine-doped tin oxide, graphene nanoribbons or metal nanowires, but the present disclosure is not limited thereto. The materials of the first electrode layer 31 and the second electrode layer 33 may be the same or different. In some embodiments, the second electrode layer 33 has a grid structure, that is, the second electrode layer 33 has a grid shape in a top view of the thin film transistor substrate, as shown in FIG. 1 . In some embodiments, the second electrode layer 33 is electrically connected to the semiconductor 15 through the fifth opening VH5 and the second metal layer 13.

FIG. 3(a) to FIG. 3(e) are partial top views of a structure in which a light shielding layer 12, a semiconductor 15, a first metal layer 11, a first insulating layer 17, and a second metal layer 13 are sequentially formed on a substrate 10 according to an embodiment of the present disclosure. FIG. 4 is a cross-sectional view of the structure shown in FIG. 3(e) taken along line II-II'. The structure of a thin film transistor substrate according to an embodiment of the present disclosure is further described below with reference to FIG. 3(a) to FIG. 3(e) and FIG. 4.

FIG3(a) is a schematic top view of a structure in which a light shielding layer 12 is formed on a substrate 10 according to an embodiment of the present disclosure. The light shielding layer 12 may include a plurality of island patterns, as shown in FIG3(a), but the present disclosure is not limited thereto. In some embodiments, the substrate 10 may include a transparent or opaque organic material or an inorganic material, and may also include a hard material or a flexible material. Examples of organic materials may include polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), liquid crystal polymer (LCP), other known suitable materials or combinations thereof, but the present disclosure is not limited thereto. Examples of inorganic materials may include dielectric materials or metal materials, but the present disclosure is not limited thereto. Examples of hard materials may include glass, quartz, sapphire, ceramics or plastics, or any suitable material. The "flexible material" herein refers to a material that can be bent, bent, folded, rolled, flexible, stretched and/or other similar deformations. Examples of flexible materials may include one of the above-mentioned organic materials, but the flexible materials referred to in the present disclosure are not limited to the above-mentioned materials. The substrate may further include a through hole penetrating the substrate along the normal direction of the substrate, a drive circuit, a compensation circuit, an optical fiber or a wire material may be disposed in the through hole, but the present disclosure is not limited thereto. The shading layer 12 may include a black matrix and a metal, wherein the material of the black matrix may include an organic insulating material (e.g., a photosensitive resin) or a metal material, but the present disclosure is not limited thereto.

The semiconductor 15 is formed on the structure of FIG. 3( a) and at least partially overlaps the light shielding layer 12, as shown in FIG. 3( b). The semiconductor 15 may include a body 151 and an end 153. The body 151 may have various shapes. In some embodiments, the body 151 may have an L-shaped structure, as shown in FIG. 3( b), but the present disclosure is not limited thereto. In some embodiments, the body 151 may have an I-shaped structure, a U-shaped structure, a Y-shaped structure, or a T-shaped structure, but the present disclosure is not limited thereto. The "L-shaped structure", "I-shaped structure", "U-shaped structure", "Y-shaped structure", or "T-shaped structure" herein refers to an L-shaped, I-shaped, U-shaped, Y-shaped, or T-shaped structure in a top view perpendicular to the thin film transistor substrate. The body 151 is connected to the end 153 along an extension direction. In one embodiment, in a direction perpendicular to the extending direction, the width of the end 153 of the semiconductor 15 is greater than the width of the body 151 of the semiconductor 15, but the present disclosure is not limited thereto. Specifically, in some embodiments, in an embodiment where the body 151 has an L-shaped structure, the semiconductor 15 may include a body 151 having a horizontal portion extending along a first direction D1 and an end 153 connected to the horizontal portion and a vertical portion extending along a second direction D2 and an end 153 connected to the vertical portion, as shown in FIG. 3(b). In a second direction D2 perpendicular to the first direction D1, a width W1 of the end 153 connected to the horizontal portion of the body 151 is greater than a width W2 of the horizontal portion of the body 151. In the first direction D1 perpendicular to the second direction D2, the width W1' of the end portion 153 connected to the vertical portion of the body 151 is greater than the width W2' of the vertical portion of the body 151. The width W1 of the end portion 153 connected to the horizontal portion of the body 151 may be the same as or different from the width W1' of the end portion 153 connected to the vertical portion of the body 151. The width W2 of the horizontal portion of the body 151 may be the same as or different from the width W2' of the vertical portion of the body 151.

The body 151 of the semiconductor 15 may include a source/drain region 151D and an active region 151G disposed between the source/drain region 151D. The body 151 of the semiconductor 15 may include a plurality of active regions 151G according to the portion overlapping with the first metal layer 11 and the second metal layer 13. For example, one semiconductor 15 of the thin film transistor substrate shown in FIG. 1 includes two active regions 151G, but the present disclosure is not limited thereto. The semiconductor 15 may include amorphous silicon (A-Si), low temperature polysilicon (LTPS), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), or other metal oxide semiconductor materials commonly used in the art, or any combination thereof, but the present disclosure is not limited thereto. The source/drain region 151D may be doped with n-type dopants (eg, phosphorus, arsenic) and/or p-type dopants (eg, boron or BF ₂ ). The source/drain region 151D may be formed by implanting dopant atoms, in-situ doping epitaxial growth, other suitable techniques, or a combination thereof.

In some embodiments, a first interlayer insulating layer 16 is further formed between the semiconductor 15 and the light shielding layer 12, as shown in FIG1 and FIG4. In some embodiments, the material of the first interlayer insulating layer 16 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The first interlayer insulating layer 16 may have a single-layer structure or a multi-layer stacked structure. For example, the first interlayer insulating layer 16 may include a single layer of silicon oxide, or the first interlayer insulating layer 16 may include a silicon nitride layer and a silicon oxide layer stacked along a normal direction of the substrate, but the present invention is not limited thereto.

The first metal layer 11 is formed on the structure of FIG. 3( b), as shown in FIG. 3( c). The first metal layer 11 includes a gate pattern 111 that at least partially overlaps the active region 151G of the semiconductor 15 and a first conductive pattern 113. The gate pattern 111 may have various shapes. In some embodiments, the gate pattern 111 may have a U-shaped structure, as shown in FIG. 3( c), but the present disclosure is not limited thereto. The gate pattern 111 may have an I-shaped structure, an L-shaped structure, a Y-shaped structure, or a T-shaped structure. The first conductive pattern 113 is electrically insulated from the gate pattern 111 and is spaced a distance apart. In some embodiments, the first conductive pattern 113 does not overlap the semiconductor 15. The first conductive pattern 113 may have various shapes. In some embodiments, the first conductive pattern 113 may have an I-shaped structure, as shown in FIG. 3( c), but the present disclosure is not limited thereto. The first conductive pattern 113 may have a U-shaped structure, an L-shaped structure, a Y-shaped structure, or a T-shaped structure. The definitions of "L-shaped structure", "I-shaped structure", "U-shaped structure", "Y-shaped structure", or "T-shaped structure" herein are the same as those described above.

The gate pattern 111 constitutes a gate electrode of the thin film transistor 20. The semiconductor 15 constitutes an active layer of the thin film transistor 20. That is, the thin film transistor 20 includes at least a portion of the semiconductor 15 and the gate pattern 111 of the first metal layer 11.

In some embodiments, the material of the first metal layer 11 may include copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), other suitable metal materials or combinations thereof. In some embodiments, the first metal layer 11 may have a single-layer structure or a multi-layer stacked structure. For example, the first metal layer 11 may include a single layer of metal copper, or the first metal layer 11 may include a metal titanium layer and a metal copper layer stacked along the normal direction of the substrate, but is not limited thereto.

In some embodiments, a second interlayer insulating layer 18 is further formed between the semiconductor 15 and the first metal layer 11 to electrically insulate the first metal layer 11 from the semiconductor 15, as shown in FIG1 and FIG4. In some embodiments, the material of the second interlayer insulating layer 18 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The second interlayer insulating layer 18 may have a single layer structure or a multi-layer stacked structure. For example, the second interlayer insulating layer 18 may include a single layer of silicon oxide, or the second interlayer insulating layer 18 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto.

The first insulating layer 17 is formed on the structure of FIG. 3( c ) to cover the first metal layer 11, as shown in FIG. 3( c ) and FIG. 4 . The first insulating layer 17 includes a first opening VH1. The first opening VH1 penetrates the first insulating layer 17. In some embodiments, the first opening VH1 may overlap a portion of the first metal layer 11. The portion of the first metal layer 11 is exposed through the first opening VH1. In some embodiments, the thin film transistor substrate includes a second opening VH2. The second opening VH2 penetrates the first insulating layer 17 and the second interlayer insulating layer 18. In some embodiments, the second opening VH2 may overlap an end 153 of the semiconductor 15. The end portion 153 of the semiconductor 15 is exposed through the second opening VH2.

In some embodiments, the material of the first insulating layer 17 may include nitride, oxide, oxynitride, perfluoroalkoxyalkane (PFA), resin, photosensitive polyimide (PSPI), polyimide (PI), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), other suitable materials, or any combination thereof, but the present disclosure is not limited thereto. The first insulating layer 17 may have a single-layer structure or a multi-layer stacked structure. For example, the first insulating layer 17 may include a single-layer silicon oxide, or the first insulating layer 17 may include a silicon nitride layer and a silicon oxide layer stacked along the normal direction of the substrate, but is not limited thereto.

The second metal layer 13 is formed on the structure of FIG. 3( d ), as shown in FIG. 3( e ). The second metal layer 13 includes a scan line pattern 131 and a second conductive pattern 133. The scan line pattern 131 and the second conductive pattern 133 are electrically insulated from each other and are spaced apart by a distance. The scan line pattern 131 at least partially overlaps with the active region 151G of the semiconductor 15 and the gate pattern 111 of the first metal layer 11. In some embodiments, the scan line pattern 131 at least partially overlaps with the first conductive pattern 113 of the first metal layer 11 (see FIG. 1 ). In some embodiments, the scan line pattern 131 extends along an extension direction. In a direction perpendicular to the extending direction, the width of at least the portion of the scan line pattern 131 overlapping the gate pattern 111 is greater than the width of the remaining portion of the scan line pattern 131. In some embodiments, as shown in FIG. 4 , the scan line pattern 131 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17.

In some embodiments, the second conductive pattern 133 includes a first portion 133A overlapping the first metal layer 11 but not overlapping the semiconductor 15, a second portion 133B overlapping the semiconductor 15 but not overlapping the first metal layer 11, and a third portion 133C overlapping the first metal layer 11 and the semiconductor 15. In some embodiments, the first portion 133A is electrically connected to the first conductive pattern 113 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17. The second portion 133B is electrically connected to the semiconductor 15 through the second opening VH2. More specifically, the second portion 133B of the second conductive pattern 133 is electrically connected to the source/drain region 151D of the semiconductor 15 through the second opening VH2, as shown in FIG. 4 . The third portion 133C is electrically connected to the first conductive pattern 113 and the semiconductor 15 through the first opening VH1 and the second opening VH2, respectively. In some embodiments, as shown in FIG. 4 , the first portion 133A and the third portion 133C of the second conductive pattern 133 are electrically connected through the first conductive pattern 113 of the first metal layer 11. In some embodiments, the second conductive pattern 133 may include a portion of a data line to provide a data signal to the semiconductor layer 15. In some embodiments, the first portion 133A and a portion of the third portion 133C of the second conductive pattern 133 may be used as a data line to provide a data signal to the semiconductor layer 15.

In some embodiments, the material of the second metal layer 13 may include a metal material having a resistance greater than 0 and less than 7 μΩ·m. The material of the second metal layer 13 may include aluminum (Al). The material of the second metal layer 13 may be the same as or different from the material of the first metal layer 11. In some embodiments, the second metal layer 13 may have a single-layer structure or a multi-layer stacked structure. For example, the second metal layer 13 may include a single layer of metal aluminum, but is not limited thereto.

The second insulating layer 19, the first electrode layer 31 disposed on the second insulating layer 19, the second electrode layer 33 disposed on the first electrode layer 31, and the third insulating layer 35 disposed between the first electrode layer 31 and the second electrode layer 33 may be further formed on the structure formed in FIG. 3( e) to complete the preparation of the thin film transistor substrate, but the present disclosure is not limited thereto. In some embodiments, the second insulating layer 19, the first electrode layer 31, the second electrode layer 33, the third insulating layer 35 or any combination thereof may be omitted.

The above-mentioned FIGS. 1 to 4 are exemplified by a semiconductor having an L-shaped structure in a thin film transistor substrate having two active regions, but the present disclosure is not limited thereto. In some embodiments, the body of the semiconductor may have a U-shaped structure. In some embodiments, the semiconductor may have three active regions. Other embodiments of the thin film transistor substrate disclosed in the present disclosure are described below with reference to FIGS. 5(a) to 8.

FIG. 5( a ) is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG. 5( b ) is a partial cross-sectional schematic diagram of the structure shown in FIG. 5( a ) taken along line III-III’. Except for the first metal layer 11, the second metal layer 13, the semiconductor 15, and the first insulating layer 17 having a single-layer structure, the other components of the thin film transistor substrate are substantially the same as the thin film transistor substrate described with reference to FIGS. 1 to 4 , so only the structures of the first metal layer 11, the second metal layer 13, and the semiconductor 15 are described below.

The semiconductor 15 is formed on the substrate 10, the first metal layer 11 is formed on the semiconductor 15, and the second metal layer 13 is formed on the first metal layer 11, as shown in FIG. 5(b).

As shown in FIG5(a), the body 151 of the semiconductor 15 has a U-shaped structure. The first metal layer 11 includes a gate pattern 111 and a first conductive pattern 113 that at least partially overlap the active region 151G of the semiconductor 15, and the gate pattern 111 has an I-shaped structure. The second metal layer 13 includes a scan line pattern 131 and a second conductive pattern 133, wherein a portion of the scan line pattern 131 overlaps the active region 151G of the semiconductor 15. According to the overlap of the semiconductor 15 with the first metal layer 11 and the second metal layer 13, the body 151 of the semiconductor 15 may include three active regions 151G, as shown in FIG5(a). The gate pattern 111 and part of the scan line pattern 131 constitute the gate electrode of the thin film transistor 20. The semiconductor 15 constitutes the active layer of the thin film transistor 20. In the embodiment shown in FIG. 5(a), the scan line pattern 131 of the second metal layer 13 is electrically connected to the gate pattern 111 of the first metal layer 11 through the first opening VH1 of the first insulating layer 17.

FIG. 6( a ) is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG. 6( b ) is a cross-sectional schematic diagram of the structure shown in FIG. 6( a ) taken along line IV-IV’. Except that the body 151 of the semiconductor 15 has a U-shaped structure, the gate pattern 111 of the first metal layer 11 has an L-shaped structure, and the first insulating layer 17 has a single-layer structure, the other elements of the thin film transistor substrate are substantially the same as the thin film transistor substrate described with reference to FIGS. 1 to 4 , and thus will not be described in detail here. FIG. 7 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. Except that the body 151 of the semiconductor 15 has a U-shaped structure and the gate pattern 111 of the first metal layer 11 has an L-shaped structure, the other components of the thin film transistor substrate are substantially the same as the thin film transistor substrate described with reference to Figures 1 to 4, so they are not described here in detail. Figure 8 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. Except that the body 151 of the semiconductor 15 has an L-shaped structure and the gate pattern 111 of the first metal layer 11 has an L-shaped structure, the other components of the thin film transistor substrate are substantially the same as the thin film transistor substrate described with reference to Figures 1 to 4, so they are not described here in detail.

Another aspect of the present disclosure provides an electronic device including a thin film transistor substrate including a thin film transistor.

The structure of the thin film transistor substrate including the thin film transistor is similar to the structure of any of the above-mentioned thin film transistor substrates, so it will not be described in detail here.

Through the above structure, the thin film transistor substrate disclosed in the present invention can significantly reduce the scan line load and is suitable for large-size panels. In addition, the thin film transistor substrate disclosed in the present invention can be manufactured with a smaller number of masks, thereby simplifying the manufacturing process or reducing the manufacturing cost. The electronic device including the thin film transistor substrate disclosed in the present invention can also have the advantages of low scan line load, low manufacturing cost, or simplified process.

Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure content of some embodiments of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described here, they can be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each patent application and the embodiment. The features between the embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

10: Substrate

11: First metal layer

111: Gate pattern

113: First conductive pattern

12: Shading layer

13: Second metal layer

131: Scan line pattern

133: Second conductive pattern

133A: Part 1

133B: Part 2

133C: Part 3

15: Semiconductor

151: Body

151G: Active Zone

151D: Source/Drain Region

153: End

16: First layer insulation layer

17: First insulation layer

18: Second interlayer insulation layer

19: Second insulation layer

20: Thin Film Transistor

VH1, VH2, VH3, VH4, VH5: Open

31: First electrode layer

33: Second electrode layer

35: The third insulating layer

In order to make the above-mentioned purpose, features and advantages of the present disclosure more clearly understandable, the specific implementation methods of the present disclosure are described in detail below in conjunction with the attached figures. FIG. 1 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG. 2 is a partial cross-sectional schematic diagram of the thin film transistor substrate shown in FIG. 1 taken along line I-I'. FIG. 3(a) is a partial top view schematic diagram of a structure in which a light shielding layer is formed on a substrate according to an embodiment of the present disclosure. FIG. 3(b) is a partial top view schematic diagram of a structure in which a semiconductor is further formed on the structure of FIG. 3(a) according to an embodiment of the present disclosure. FIG. 3(c) is a partial top view schematic diagram of a structure in which a first metal layer is further formed on the structure of FIG. 3(b) according to an embodiment of the present disclosure. FIG. 3(d) is a partial top view schematic diagram of a structure in which a first insulating layer is further formed on the structure in FIG. 3(c) according to an embodiment of the present disclosure. FIG. 3(e) is a partial top view schematic diagram of a structure in which a second metal layer is further formed on the structure in FIG. 3(d) according to an embodiment of the present disclosure. FIG. 4 is a partial cross-sectional schematic diagram of the structure shown in FIG. 3(e) taken along line II-II'. FIG. 5(a) is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG. 5(b) is a partial cross-sectional schematic diagram of the structure shown in FIG. 5(a) taken along line III-III'. FIG. 6(a) is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG6(b) is a partial cross-sectional schematic diagram of the structure shown in FIG6(a) taken along line IV-IV'. FIG7 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure. FIG8 is a partial top view schematic diagram of a thin film transistor substrate according to an embodiment of the present disclosure.

10: Substrate

11: First metal layer

111: Gate pattern

113: First conductive pattern

12: Shading layer

13: Second metal layer

131: Scan line pattern

133: Second conductive pattern

133B: Part 2

133C: Part 3

15: Semiconductors

151G: Active zone

151D: Source/Drain Region

16: The first interlayer insulation layer

17: First insulating layer

18: Second interlayer insulation layer

19: Second insulation layer

20: Thin Film Transistor

VH1, VH2, VH3, VH4, VH5: Open

31: First electrode layer

33: Second electrode layer

35: The third insulating layer

Claims (10)

A thin film transistor substrate comprises: a substrate; a first metal layer disposed on the substrate and comprising a gate pattern and a first conductive pattern; a second metal layer disposed on the first metal layer and comprising a scan line pattern and a data line; a semiconductor disposed between the substrate and the first metal layer and comprising an active region; and a first insulating layer disposed Between the first metal layer and the second metal layer and including a first opening; wherein the gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening, wherein the data line is electrically connected to the first conductive pattern and the scan line pattern at least partially overlaps with the first conductive pattern. A thin film transistor substrate as described in claim 1, wherein the semiconductor includes a body and an end, wherein the body has an L-shaped structure, an I-shaped structure, a U-shaped structure, a Y-shaped structure, or a T-shaped structure. A thin film transistor substrate as described in claim 2, wherein the body is connected to the end along an extension direction, and in a direction perpendicular to the extension direction, the width of the end of the semiconductor is greater than the width of the body of the semiconductor. A thin film transistor substrate as described in claim 1, wherein the first conductive pattern and the gate pattern are electrically insulated from each other and spaced a distance apart, and the first conductive pattern and the semiconductor do not overlap. A thin film transistor substrate as described in claim 4, wherein the second metal layer further includes a second conductive pattern, and the second conductive pattern includes a first portion overlapping with the first metal layer but not overlapping with the semiconductor, a second portion overlapping with the semiconductor but not overlapping with the first metal layer, and a third portion overlapping with the first metal layer and the semiconductor. A thin film transistor substrate as described in claim 5, wherein the first portion is electrically connected to the first conductive pattern of the first metal layer through a second opening of the first insulating layer. The thin film transistor substrate as described in claim 1 further includes a first electrode layer disposed on the second metal layer and a second electrode layer disposed on the first electrode layer, wherein the second electrode layer is electrically connected to the semiconductor. A thin film transistor substrate as described in claim 1, wherein the second metal layer comprises a metal material having a resistance greater than 0 and less than 7μΩ.m. An electronic device includes a thin film transistor substrate, wherein the thin film transistor substrate includes: a substrate; a first metal layer disposed on the substrate and including a gate pattern and a first conductive pattern; a second metal layer disposed on the first metal layer and including a scan line pattern and a data line; a semiconductor disposed between the substrate and the first metal layer and including an active region; and A first insulating layer is disposed between the first metal layer and the second metal layer and includes a first opening; wherein the gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening, wherein the data line is electrically connected to the first conductive pattern and the scan line pattern at least partially overlaps with the first conductive pattern. An electronic device as described in claim 9, wherein the second metal layer comprises a metal material having a resistance greater than 0 and less than 7 μΩ.m.