TWI867374B - Memory device and sense amplifier capable of performing logical not operation - Google Patents

Abstract

A sense amplifier capable of performing a logical NOT operation is provided, which includes a sense circuit, configured to sense a first voltage of a bitline and a second voltage of an inverse bitline complementary to the bitline; a first transistor, coupled between a first terminal of the sense circuit and the bitline; a second transistor, coupled between a second terminal of the sense circuit and the inverse bitline; and a third transistor, coupled between the bitline and the inverse bitline. A first memory cell and a second memory cell are respectively controlled by a first wordline and a second wordline, and are connected to the bitline. When the sense amplifier is in an inverse writing state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. A first logical state of the first voltage is complementary to a second logical state of the second voltage.

Description

Memory device and sense amplifier capable of performing logical non-operation

The present invention relates to a memory device, and more particularly to a memory device and a sense amplifier capable of performing logical negation operations.

Traditional computer devices usually use the Von Neumann architecture to transfer data between the CPU and the memory device. However, when the data transfer volume between the CPU and the memory device is extremely large, a data transfer bottleneck often occurs between the CPU and the memory device, which is called the Von Neumann bottleneck. Therefore, a memory device and a sense amplifier that can perform in-memory operations are needed to solve the above problem.

The present invention provides a sense amplifier capable of performing a logical negation operation, comprising: a sense circuit for sensing a first voltage of a bit line and a second voltage between an inverted bit line relative to the bit line; a first transistor coupled between a first end of the sense circuit and the bit line; a second transistor coupled between a second end of the sense circuit and the inverted bit line; and a third transistor coupled between the bit line and the inverted bit line. A first memory cell and a second memory cell are controlled by a first word line and a second word line, respectively, and the first memory cell and the second memory cell are connected to the bit line. When the sense amplifier is in an inverted write state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. The first logic state of the first voltage is inverted to the second logic state of the second voltage.

The present invention further provides a memory device capable of performing logical non-operation, comprising: a memory cell array, comprising a plurality of memory cells arranged in a two-dimensional array, wherein the memory cells on each row of the memory cell array are connected to a corresponding word line, and the memory cells on each column of the memory cell array are connected to a corresponding bit line; and a sense amplifier. The sense amplifier includes: a sense circuit for sensing a first voltage of a bit line and a second voltage between an inverted bit line relative to the bit line; a first transistor coupled between a first end of the sense circuit and the bit line; a second transistor coupled between a second end of the sense circuit and the inverted bit line; and a third transistor coupled between the bit line and the inverted bit line. A first memory cell and a second memory cell are controlled by a first word line and a second word line, respectively, and the first memory cell and the second memory cell are connected to the bit line. When the sense amplifier is in an inverted write state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. The first logic state of the first voltage is opposite to the second logic state of the second voltage.

FIG. 1 is a schematic diagram of a computing device according to an embodiment of the present invention. As shown in FIG. 1, the computing device 10 includes a central processing unit 110 and a memory device 120. The central processing unit 110 is electrically connected to the memory device 120, wherein the memory device 120 includes, for example, one or more dynamic random access memory (DRAM) chips, but the present invention is not limited thereto. The memory device 120 includes, for example, a plurality of memory banks, and each memory bank includes a plurality of memory cell arrays, wherein each memory cell array is arranged in a two-dimensional array (e.g., M rows*N columns), wherein each column and each row of the memory cell array are connected to corresponding word lines and bit lines, respectively. In addition, each memory cell can store 1 bit or M bits of data, wherein M is an integer greater than 1.

The CPU 110 includes, for example, a memory controller 111, an arithmetic logic unit (ALU) 112, and a cache memory 113. The memory controller 111 is used to control data access of the memory device 120. It should be noted that the control signal 115 sent by the memory controller 111 to the memory device 120 can control the memory device 120 to perform in-memory computing, such as performing a bitwise NOT operation. The memory controller 111 can also receive data processed by bitwise computing or general data that has not been processed by logical computing from the memory device 120.

The ALU 112 performs corresponding arithmetic operations and/or logic operations according to the instructions executed by the CPU 110. In some embodiments, in order to reduce the data bandwidth requirement between the CPU 110 and the memory device 120, the memory controller 111 of the CPU 110 sends a corresponding control signal 115 to the memory device 120 to transfer part of the logical operation (for example, bitwise NOT operation) to the memory device 120 for execution, and receives the data processed by the above logical operation from the memory device 120 (for example, through the data bus 116), and then transmits the above data to the arithmetic logic unit 112 for subsequent processing.

The memory device 120 includes, for example, a plurality of memory banks 121 - 12N, and each of the memory banks 121 - 121N includes a plurality of memory unit arrays 1211 - 121N.

FIG. 2 is a circuit diagram of a memory cell array according to the embodiment of FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 2 simultaneously.

In FIG. 2, a memory cell array 1211 is used for illustration, and the circuit diagrams of other memory cell arrays 1212 to 121N are similar to FIG. Memory cell array 1211 includes a plurality of memory cells 201 arranged in a two-dimensional array, and each row of memory cells 201 is connected to a corresponding word line 202, and each row of memory cells 201 is connected to a corresponding bit line 203. In addition, each bit line 203 is connected to a corresponding sense amplifier 204.

FIG. 3A is a block diagram of a sense amplifier according to the embodiment of FIG. 2 of the present invention. FIG. 3B is a circuit diagram of a sense circuit according to the embodiment of FIG. 3A of the present invention. Please refer to FIG. 2 and FIG. 3A-3B at the same time.

The sense amplifier 204 of FIG. 2 can be implemented by the sense amplifier 400 of FIG. 3A. As shown in FIG. 3A, the sense amplifier 400 includes transistors 411, 441, and 442, and a sense circuit 420. The control terminal of the transistor 411 is connected to the bypass signal BYPASS, and the first terminal and the second terminal of the transistor 411 are respectively connected to the reverse bit line bBL (e.g., node N7) and the bit line BL (e.g., node N6).

The control terminals of transistors 441 and 442 are connected to isolation signals ISO_L and ISO_R, respectively. The first terminal of transistor 441 (e.g., node N4) is connected to the sensing circuit 420, and the second terminal of transistor 441 (e.g., node N6) is connected to the bit line BL. The first terminal of transistor 442 (e.g., node N7) is connected to the reverse bit line bBL, and the second terminal of transistor 442 (e.g., node N5) is connected to the sensing circuit 420. Transistor Q0 in memory cell 430 is controlled by word line WL0, and transistor Q0 is also connected to bit line BL (e.g., node N6). Transistor Q1 in memory cell 435 is controlled by word line WL1, and transistor Q1 is also connected to bit line BL (e.g., node N6).

Please refer to FIG. 3B again. The sensing circuit 420 includes transistors Q2 to Q9, wherein transistors Q4 and Q5 form a balanced circuit. For example, when the balanced signal EQL is in a high logic state, transistors Q4 and Q5 are both turned on, so the voltages at nodes N4 and N5 are balanced through transistor Q4, wherein the bit line balanced voltage V _BLEQ can be obtained at nodes N4 and N5 through transistor Q5, for example. Transistors Q2 to Q3 and Q6 to Q7 form an inverter loop. In detail, transistors Q2 and Q7 form an inverter, whose input is coupled to node N4 and whose output is coupled to node N5; transistors Q3 and Q6 form another inverter, whose input is coupled to node N5 and whose output is coupled to node N4; therefore, these two inverters form an inverter loop circuit. Transistors Q8 and Q9 are used to generate control signals PCS and NCS respectively.

For example, when the sensing enable signal SA_EN is in a low logic state, the control signal PCS and the control signal NCS do not change. At this time, the sensing circuit 420 is in a closed state. When the sensing enable signal SA_EN is in a high logic state, the control signal PCS is in a high logic state, and the control signal NCS is in a ground state. At this time, the sensing circuit 420 can operate normally.

Please refer to Figure 3A again. In one embodiment, when the sense amplifier 400 is used to sense the data voltage stored in the capacitor C1 of the memory cell 435, it is still necessary to perform the pre-charge state, the start state and the sense state in sequence. In the pre-charge state, the word line WL1 and the sense enable signal SA_EN are in a low logic state, and the isolation signals ISO_L and ISO_R, the bypass signal BYPASS and the balance signal EQL are all in a high logic state. At this time, the voltage level of the bit line BL is pre-charged to a voltage .

In the activation state, the word line WL1 switches to a high logic state, the isolation signals ISO_L and ISO_R are also in a high logic state, and the sense enable signal SA_EN, the bypass signal BYPASS and the balance signal EQL are all in a low logic state. At this time, the data voltage stored in the capacitor C1 of the memory cell 435 is transmitted to the bit line BL to change the voltage level of the bit line BL.

In the sensing state, the word line WL1 is maintained in a high logic state, and the isolation signals ISO_L and ISO_R are also in a high logic state. The bypass signal BYPASS and the balance signal EQL are both in a low logic state, but the sense enable signal SA_EN switches to a high logic state to enable the sense circuit 420 to sense the voltage level on the bit line BL.

FIG. 4 is a waveform diagram of the sense amplifier performing a logical negation operation according to the embodiment of FIG. 3A of the present invention. Please refer to FIG. 3A and FIG. 4 at the same time.

The sense amplifier 400 can also be used to perform a NOT logic operation. For example, when the sense amplifier 400 wants to perform a NOT logic operation on the data voltage stored in the capacitor C1 of the memory cell 435, the sense amplifier 400 will still enter the pre-charge state to pre-charge the bit line BL to a predetermined voltage level, such as voltage At this time, the isolation signals ISO_L and ISO_R, the bypass signal BYPASS, and the balance signal EQL are all in a high logic state, and the sense enable signal SA_EN, the word lines WL0 and WL1 are all in a low logic state.

Then, the sense amplifier 400 performs the following operations in sequence:

Operation (1A): The sense amplifier 400 enters the activation state to enable the word line WL1, and then enables the sense enable signal SA_EN in operation (1B). For example, the word line decoder (not shown) in the memory cell array 1211 enables the word line WL1 (e.g., a high logic state) according to the address signal in the control signal 115. At this time, the data voltage stored in the capacitor C1 will be latched in the sense circuit 420. It should be noted that at this time, the isolation signals ISO_L and ISO_R are also in a high logic state, and the bypass signal BYPASS and the balance signal EQL are both in a low logic state. The sense enable signal SA_EN will switch from a low logic state to a high logic state.

Operation (2): Switch the isolation signal ISO_L to a low logic state and maintain the isolation signal ISO_R in a high logic state.

Operation (3): Switch word line WL0 to a high logic state.

Operation (4): Switch the bypass signal BYPASS to high logic state.

Therefore, after operations (1) to (4), the sense amplifier 400 enters the reverse write state to transmit the voltage level on the reverse bit line bBL to the node N8 via the transistor 442 and the transistor 411 in sequence. Therefore, the data voltage finally stored in the capacitor C0 of the memory cell 430 is the voltage level on the reverse bit line bBL, which is the opposite (NOT) value of the logical level of the data voltage stored in the capacitor C1 of the memory cell 435. In some embodiments, the order of operations (3) and (4) can be reversed.

For example, when the data voltage stored in the capacitor C1 of the memory cell 435 is in a high logic state, the voltage level on the bit line BL sensed by the sensing circuit 420 will also be in a high logic state. At this time, the voltage level on the reverse bit line bBL will be in a low logic state. Therefore, after operations (1) to (4), the voltage level on the reverse bit line bBL will be transmitted to the node N8 through the transistor 442 and the transistor 411 in sequence, so the data voltage finally stored in the capacitor C0 of the memory cell 430 will be in a low logic state. On the contrary, when the data voltage stored in the capacitor C1 of the memory cell 435 is in a low logic state, the voltage level on the bit line BL sensed by the sensing circuit 420 will also be in a low logic state. At this time, the voltage level on the reverse bit line bBL will be in a high logic state. Therefore, after operations (1) to (4), the voltage level on the reverse bit line bBL will be transmitted to the node N8 through the transistor 442 and the transistor 411 in sequence, so the data voltage finally stored in the capacitor C0 of the memory cell 430 will be in a high logic state.

In some embodiments, word lines WL1 and WL0 may be adjacent word lines or non-adjacent word lines.

Please refer to FIG. 1, FIG. 2 and FIG. 3A again. In one embodiment, a sense amplifier 400 is disposed between two memory cell arrays (e.g., memory arrays 1211 and 1212, memory arrays 1212 and 1213, and so on). In other words, on the right side of the sense amplifier 400 in FIG. 3A, there is a word line (e.g., word line WL2) to which the memory cells of another memory cell array are connected. Therefore, when a logical negation operation is to be performed on the logical level of the data voltage stored in the capacitor C0 in the memory cell 430, the memory cell in the memory cell array on the right side of the sense amplifier 400 can be used to store the inverted value. In this embodiment, the details of operations (1) to (4) are slightly different. For example, operation (2) can be changed to operation (2A) to switch the isolation signal ISO_L to a high logic state and maintain the isolation signal ISO_R in a low logic state. Therefore, the voltage level on the bit line BL is written into the capacitance of the memory cell in the memory cell array on the right side of the sense amplifier 400 through the transistor 411 to achieve a logical NOT operation.

In summary, the present invention provides a sense amplifier capable of performing logical negation operation, which can be arranged in a plurality of memory cell arrays of a memory device to perform logical negation operation on the logical level of the data voltage stored in the memory cell according to a control signal from a memory controller.

10: Computing device 110: Central processor 111: Memory controller 112: Arithmetic logic unit 113: Cache memory 115: Control signal 116: Data bus 120: Memory device 121-12N: Memory bank 1211-121N: Memory cell array 201: Memory cell 202: Word line 203: Bit line 204: Sensor Sense amplifier 2011: transistor 2012: capacitor 400: sense amplifier 411, 441, 442: transistor 420: sense circuit 430, 435: memory cell C0, C1: capacitor WL: word line BL: bit line bBL: reverse bit line ISO_L, ISO_R: isolation signal EQL: balance signal SA_EN: sense enable signal : Reverse sense enable signal BYPASS: Bypass signal N1~N9: Nodes WL, WL0, WL1: Word lines PCS, NCS: Control signal V _BLH : Voltage V _BLEQ : Bit line balance voltage (1A), (1B), (2), (3), (4): Operation

FIG. 1 is a schematic diagram of an operation device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a memory cell array according to the embodiment of FIG. 1 of the present invention. FIG. 3A is a block diagram of a sense amplifier according to the embodiment of FIG. 2 of the present invention. FIG. 3B is a circuit diagram of a sense circuit according to the embodiment of FIG. 3A of the present invention. FIG. 4 is a waveform diagram of a sense amplifier performing a logical non-operation according to the embodiment of FIG. 3A of the present invention.

10: Computing device

110: Central Processing Unit

111:Memory controller

112: Arithmetic Logic Unit

113: Cache memory

115: Control signal

116: Data bus

120: Memory device

121-12N: Memory library

1211-121N: memory cell array

Claims (11)

A sense amplifier capable of performing a logical negation operation comprises: a sense circuit for sensing a first voltage of a bit line and a second voltage of an inverted bit line relative to the bit line; a first transistor having a first end connected to the first end of the sense circuit and a second end connected to the bit line, and a control end of the first transistor being connected to a first isolation signal; a second transistor having a first end connected to the second end of the sense circuit and a second end connected to the inverted bit line, and a control end of the second transistor being connected to a second isolation signal, wherein the second isolation signal is different from the first isolation signal; and a third transistor having a first end connected to the first end of the sense circuit and a second end connected to the inverted bit line, and a control end of the second transistor being connected to a second isolation signal. to the bit line, and a second end is connected to the inverted bit line, and the control end of the third transistor is connected to a bypass signal; wherein a first memory cell and a second memory cell are controlled by a first word line and a second word line respectively, and the first memory cell and the second memory cell are connected to the bit line, wherein when the sense amplifier is in an inverted write state, the sense amplifier writes the second voltage to the second memory cell through the second transistor and the third transistor, so that the second data voltage stored in the second memory cell is equal to the second voltage, and the first logic state of the first voltage is inverted to the second logic state of the second voltage. The sense amplifier capable of performing a logical negation operation as claimed in claim 1 further includes a third memory cell, the third memory cell is controlled by a third word line, and the third memory cell is connected to the inverted bit line, wherein when the sense amplifier is in the inverted write state, the sense amplifier writes the first voltage to the third memory cell through the first transistor and the third transistor, so that the third data voltage stored in the third memory cell is equal to the first voltage. A sense amplifier capable of performing a logical negation operation as claimed in claim 1, wherein when the sense amplifier is in a precharge state, the first isolation signal, the second isolation signal and the bypass signal are in a high logic state, the balance signal and the sense enable signal of the sense circuit are in the high logic state and the low logic state respectively, and the first word line and the second word line are both in the low logic state, so as to precharge the bit line to a predetermined voltage. A sense amplifier capable of performing a logical non-operation as claimed in claim 3, wherein when the sense amplifier enters an activation state, the bypass signal and the balance signal are switched to the low logic state, the sense enable signal is in the low logic state, and the first word line is switched to the high logic state to transmit the first data voltage stored in the first memory cell to the bit line to change the first voltage of the bit line. A sense amplifier capable of performing a logical negation operation as claimed in claim 4, wherein when the sense amplifier enters a sensing state, the first word line is maintained in the high logic state, the bypass signal and the balance signal are both in the low logic state, and the sense enable signal is switched to the high logic state, so that the sense circuit senses the first voltage of the bit line. A sense amplifier capable of performing a logical non-operation as claimed in claim 5, wherein when the sense amplifier enters the reverse write state, the first isolation signal is switched to the low logic state to turn off the first transistor, the second isolation signal is maintained in the high logic state to turn on the second transistor, the side signal is switched to the high logic state to turn on the third transistor, and the second word line is switched to the high logic state to turn on the second memory cell, so as to transmit the second voltage on the reverse bit line to the second memory cell via the second transistor and the third transistor in sequence, so that the second data voltage stored in the second memory cell is equal to the second voltage. A sense amplifier capable of performing a logical negation operation as claimed in claim 1, wherein the sense circuit comprises a first inverter and a second inverter, wherein the input terminal of the first inverter is connected to the second terminal of the sense circuit, and the output terminal of the first inverter is connected to the first terminal of the sense circuit, wherein the input terminal of the second inverter is connected to the first terminal of the sense circuit, and the output terminal of the second inverter is connected to the second terminal of the sense circuit. As claimed in claim 7, the sense amplifier capable of performing logical non-operation, wherein the sense circuit further comprises a balancing circuit, the balancing circuit comprises a fourth transistor and a fifth transistor, wherein when the balancing signal is in the high logic state, the fourth transistor and the fifth transistor are turned on to balance the voltage of the first end of the first transistor and the voltage of the first end of the second transistor through the fourth transistor, and to obtain a bit line balancing voltage at the first end of the first transistor and the first end of the second transistor through the fifth transistor. A memory device capable of performing logical non-operation comprises: a memory cell array, comprising a plurality of memory cells arranged in a two-dimensional array, wherein the memory cells on each row of the memory cell array are connected to corresponding word lines, and the memory cells on each row of the memory cell array are connected to corresponding bit lines; and a sense amplifier, comprising: a sense circuit for sensing a first transistor having a first end connected to the first end of the sensing circuit and a second end connected to the bit line, and a control end of the first transistor is connected to a first isolation signal; a second transistor having a first end connected to the second end of the sensing circuit and a second end connected to the reverse bit line, and the ... first end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the second end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the first end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the first end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the first end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the first end of the sensing circuit and a second end connected to the reverse bit line, and the second transistor having a first end connected to the first end of the sensing circuit and a second end connected The control end of the transistor is connected to a second isolation signal, wherein the second isolation signal is different from the first isolation signal; and a third transistor has a first end connected to the bit line and a second end connected to the inverting bit line, and the control end of the third transistor is connected to a bypass signal; wherein a first memory cell and a second memory cell are controlled by a first word line and a second word line, respectively, and the first memory cell The memory cell and the second memory cell are connected to the bit line, wherein when the sense amplifier is in a reverse write state, the sense amplifier writes the second voltage to the second memory cell through the second transistor and the third transistor, so that the second data voltage stored in the second memory cell is equal to the second voltage, and the first logic state of the first voltage is reverse to the second logic state of the second voltage. A memory device capable of performing a logical negation operation as claimed in claim 9, wherein the sense amplifier further comprises a third memory cell, the third memory cell is controlled by a third word line, and the third memory cell is connected to the inverted bit line, wherein when the sense amplifier is in the inverted write state, the sense amplifier writes the first voltage to the third memory cell through the first transistor and the third transistor, so that the third data voltage stored in the third memory cell is equal to the first voltage. A memory device capable of performing logical non-operation as claimed in claim 9, wherein the sensing circuit comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected to the second end of the sensing circuit, and the output end of the first inverter is connected to the first end of the sensing circuit, wherein the input end of the second inverter is connected to the first end of the sensing circuit, and the output end of the second inverter is connected to the second end of the sensing circuit.

Images