TWI867016B - Method for manufacturing wiring board - Google Patents

Abstract

The manufacturing method of the wiring substrate disclosed in the present invention comprises: (A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening portion on the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing an anti-etching agent pattern on the surface of the seed layer; (E) forming a wiring portion including a solder pad and wiring; (F) removing the anti-etching agent pattern; (G) a step of removing the seed layer; (H) a step of performing a first surface treatment on the surface of the pad; (I) a step of forming a second insulating material layer; (J) a step of forming a second opening in the second insulating material layer; (K) a step of performing a second surface treatment on the surface of the pad; and (L) a step of heating the second insulating material layer to a temperature above the glass transition temperature of the second insulating material layer.

Description

Method for manufacturing wiring board

This disclosure relates to a method for manufacturing a wiring board.

With the goal of achieving high density and high performance of semiconductor packaging, a method of mixing and installing chips with different performances in one package has been proposed, and high-density interconnect technology between chips with excellent cost performance has become important (for example, refer to Patent Document 1).

In smart phones and tablet terminals, a package-on-package method is widely used in which different packages are stacked and connected on a package using flip-chip mounting (see, for example, Non-Patent Documents 1 and 2). Furthermore, as a method for mounting at a higher density, packaging technology using an organic substrate with high-density wiring (organic interposer), fan-out packaging technology with through mold via (TMV) (fan-out wafer-level package (FO-WLP)), packaging technology using silicon interposer or glass interposer, packaging technology using through silicon via (TSV), and packaging technology using chips buried in a substrate for inter-chip transfer have been proposed. In particular, in the case of mounting semiconductor chips in parallel with each other in organic interposer and FO-WLP, a fine wiring layer is required in order to make the semiconductor chips electrically connected to each other at a high density (for example, refer to patent document 2).

[Prior art literature] [Patent Literature]

[Patent document 1] Japanese Patent Publication No. 2003-318519

[Patent Document 2] U.S. Patent Application Publication No. 2001/0221071

[Non-patent literature]

[Non-patent document 1] "Application of Through Mold Via (TMV) as PoP Base Package", Electronic Components and Technology Conference (ECTC), 2008

[Non-patent document 2] "Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology", ECTC, 2012

In the technology described in the patent document 1, after the desmear treatment, the wiring is formed through the steps of electroless plating, anti-etching agent pattern formation, electrolytic plating, anti-etching agent stripping, seed crystal etching and insulating material formation. In order to ensure the close contact between the wiring and the insulating material, it is necessary to make the wiring surface moderately rough by etching, etc., and the insulating material is firmly fixed to the wiring by the anchoring effect.

However, in recent years, wiring substrates have been required to reduce transmission loss in high frequency bands. As described above, if the wiring surface is roughened, the transmission loss increases due to the surface effect. However, in the manufacturing method of the wiring substrate, when the insulating material layer is formed without going through the step of roughening the wiring surface, another problem arises that the adhesion with the wiring surface deteriorates and the electrical insulation deteriorates. Therefore, the subject of the present invention is to manufacture a wiring substrate that exhibits excellent electrical insulation while ensuring the adhesion between the wiring and the insulating material.

In addition, even if the wiring and the insulating material are in close contact immediately after the wiring board is assembled, a thick oxide layer (such as a CuO layer) will be formed on the wiring surface through long-term heat resistance tests such as high-temperature placement test, moisture absorption resistance test, reflow resistance test, and accelerated test, resulting in reduced adhesion with the insulating material. As a result, the problem of deterioration of electrical insulation occurs. Furthermore, as an example of an accelerated test, the Highly Accelerated Stress Test (HAST) can be cited.

This disclosure is made in view of the above-mentioned subject, and its purpose is to provide a method for manufacturing a wiring substrate in which the wiring part and the insulating material layer have sufficient adhesion and heat resistance and have sufficient insulation reliability.

The manufacturing method of the wiring substrate disclosed herein includes the following steps.

(A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening in the first insulating material layer; (C) forming a seed layer on the surface of the first insulating material layer by electroless plating; (D) providing an anti-etching agent pattern for forming a wiring portion on the surface of the seed layer; (E) forming a wiring portion including a pad and wiring by electrolytic plating in an area exposed from the anti-etching agent pattern on the surface of the seed layer; (F) removing the anti-etching agent pattern; (G) removing the seed layer exposed by the removal of the anti-etching agent pattern; (H) performing a first surface treatment on the surface of the wiring portion; (I) forming a second insulating material layer in a manner covering the wiring portion; (J) forming a second opening at a position corresponding to the solder pad in the second insulating material layer; (K) performing a second surface treatment on the surface of the solder pad; and (L) heating the second insulating material layer to a temperature above the glass transition temperature of the second insulating material layer.

In the step (H), the adhesion between the wiring portion and the second insulating material layer can be improved by performing a treatment (first surface treatment) on the surface of the wiring portion to improve the adhesion with the second insulating material layer. As a specific example of the first surface treatment, a treatment using a surface treatment agent can be cited, wherein the surface treatment agent contains an organic component that improves the adhesion between the wiring portion including the metal material and the second insulating material layer. The average roughness Ra of the surface of the wiring portion subjected to the first surface treatment is, for example, 40nm to 80nm. By performing the first surface treatment on the surface of the wiring portion, the adhesion between the wiring portion and the second insulating material layer can be sufficiently improved even if the surface of the wiring portion is not excessively rough. After step (J), the peel strength of the second insulating material layer relative to the wiring is, for example, 0.2kN/m~0.7kN/m. In addition, since the surface of the wiring part is not too rough, the transmission loss can be sufficiently reduced. When a fine wiring pattern is formed on the first insulating layer, in the step (D), for example, an anti-etching agent pattern with a groove opening having a line width of 0.5μm~20μm can be formed.

According to the present disclosure, by performing a second surface treatment on the surface of the solder pad in the step (K), excellent conductivity of the solder pad can be obtained. That is, even if the surface treatment layer is formed on the surface of the solder pad by the first surface treatment in the step (H), the conductivity of the solder pad can be restored by, for example, performing a treatment to remove the layer in the step (K). In addition, according to the present disclosure, by performing both the step (H) and the step (L), the adhesion between the wiring portion and the second insulating material layer can be further improved, and a wiring board with excellent insulation reliability can be manufactured.

The manufacturing method may further include a step of removing residues on the first insulating material layer and/or in the first opening between step (B) and step (C). The process of removing residues is sometimes referred to as desmearing. At least one of the first insulating material layer and the second insulating material layer may include a photosensitive resin. When the insulating material layer includes a photosensitive resin, the opening may be formed, for example, by a photolithography process.

The second opening is preferably formed at a position corresponding to the pad. In this case, the manufacturing method may further include a step of performing a second surface treatment on the surface of the pad in the second opening. In the step of performing the first surface treatment, when a surface treatment agent containing an organic component as described above is used, the surface treatment agent can be removed from the surface of the pad by the second surface treatment. The second surface treatment is, for example, at least one selected from the group consisting of oxygen plasma treatment, argon plasma treatment, and desmear treatment.

According to the present disclosure, a method for manufacturing a wiring substrate having sufficient adhesion and heat resistance between the wiring portion and the insulating material layer and sufficient insulation reliability is provided.

1: First insulating material layer

2: Second insulating material layer

3: The third insulating material layer

5: Surface treatment layer

6: Surface treatment agent removal section

7: Firing layer

8A, 8B: Wiring layer

10, 20, 30: Wiring board

40: Multi-layer wiring board

C: Wiring department

C1: Solder pad

C2: Wiring

F: Surface treated with desmear treatment

H: Opening

H1: First opening

H2: Second opening

R: Anti-corrosion agent pattern

R1, R2: Opening part

S: Supporting substrate

Sa: Conductive layer

T: Seed layer

FIG1(a) is a cross-sectional view schematically showing a state where a first insulating material layer is formed on a supporting substrate, FIG1(b) is a cross-sectional view schematically showing a state where a first opening portion is provided on the first insulating material layer, FIG1(c) is a cross-sectional view schematically showing a state where a desmear treatment is performed on the first insulating material layer and the first opening portion, and FIG1(d) is a cross-sectional view schematically showing a state where a seed crystal layer is formed on the first insulating material layer.

FIG2 (a) is a cross-sectional view schematically showing a state where an anti-etching agent pattern for forming a wiring portion is formed on a seed layer, FIG2 (b) is a cross-sectional view schematically showing a state where a wiring portion is formed by electrolytic plating, FIG2 (c) is a cross-sectional view schematically showing a state where the anti-etching agent pattern is removed, and FIG2 (d) is a cross-sectional view schematically showing a state where the seed layer exposed by the removal of the anti-etching agent pattern is removed.

FIG3 (a) is a cross-sectional view schematically showing a state where a first surface treatment is applied to the surface of a wiring portion, FIG3 (b) is a cross-sectional view schematically showing a state where a second insulating material layer having a second opening is formed on a first insulating material layer, and FIG3 (c) is a cross-sectional view schematically showing a state where a second surface treatment is applied to the surface of a pad.

FIG4 is a cross-sectional view schematically showing a state in which a fired layer is formed between the second insulating material layer and the wiring portion by heating the second insulating material layer at a temperature above its glass transition temperature.

FIG5 is a cross-sectional view schematically showing an embodiment of a wiring substrate having a multi-layered wiring layer.

In the following, the implementation method of the present disclosure is described in detail with reference to the drawings. In the following description, the same symbols are marked for the same or equivalent parts, and repeated descriptions are omitted. In addition, unless otherwise specified, the positional relationship of up, down, left, right, etc. is based on the positional relationship shown in the drawings. The dimensional ratio in the drawings is not limited to the ratio shown in the drawings.

When the terms "left", "right", "front", "back", "up", "down", "above", "below" and the like are used in the description and claims of this specification, these terms are intended for explanation and do not necessarily refer to permanent relative positions. In addition, the word "layer" includes not only the structure of the shape formed by the entire surface but also the structure of the shape formed by a part when viewed in a plan view. "A or B" only needs to include either A or B, and may include both.

In this manual, the term "step" refers not only to independent steps, but also to steps that cannot be clearly distinguished from other steps as long as the intended effect of the step can be achieved. In addition, the numerical range represented by "~" indicates a range that includes the numerical values before and after "~" as the minimum and maximum values, respectively.

In this specification, when there are multiple substances equivalent to each component in the composition, unless otherwise specified, the content of each component in the composition refers to the total amount of the multiple substances in the composition. In addition, unless otherwise specified, the exemplified materials can be used alone or in combination of two or more. In addition, in the numerical ranges recorded in stages in this specification, the upper limit or lower limit of a numerical range in a certain stage can also be replaced by the upper limit or lower limit of the numerical range in another stage. In addition, in the numerical ranges recorded in this specification, the upper limit or lower limit of the numerical range can also be replaced by the value shown in the embodiment.

The manufacturing method of the wiring substrate of the embodiment of the present disclosure is described with reference to the drawings. The manufacturing method of the wiring substrate of the present embodiment includes at least the following steps.

(A) forming a first insulating material layer 1 on a supporting substrate S; (B) forming a first opening H1 in the first insulating material layer 1; (C) forming a seed layer T on the surface of the first insulating material layer 1 by electroless plating; (D) providing an anti-etching agent pattern R for forming a wiring portion on the surface of the seed layer T; (E) forming a wiring portion C including a pad C1 and a wiring C2 by electrolytic plating in an area on the surface of the seed layer T exposed from the anti-etching agent pattern R; (F) removing the anti-etching agent pattern R; (G) removing the anti-etching agent pattern R; (H) a step of performing a first surface treatment on the surface of the pad C1 and the wiring C2; (I) a step of forming a second insulating material layer 2 in a manner covering the pad C1 and the wiring C2; (J) a step of forming a second opening H2 on the second insulating material layer 2; (K) a step of performing a second surface treatment on the surface of the pad C1 in the second opening H2; and (L) a step of heating the second insulating material layer 2 to a temperature above the glass transition temperature of the second insulating material layer 2.

The wiring substrate of this embodiment is suitable for the form that requires miniaturization and multi-pin, and is particularly suitable for the package form that requires an interposer for mixed mounting of different chips. More specifically, the manufacturing method of this embodiment is suitable for the package form in which the spacing between needles is less than 200μm (for example, 30μm~100μm in a more microscopic case) and the number of needles is more than 500 (for example, 1000~10000 in a more microscopic case). The following describes each step.

<Step of forming a first insulating material layer on a supporting substrate>

A first insulating material layer 1 is formed on a supporting substrate S (Fig. 1(a)). The supporting substrate S is not particularly limited, but is preferably a silicon plate, a glass plate, a stainless steel (Steel Use Stainless, SUS) plate, a substrate with glass cloth, and a substrate with high rigidity including a sealing resin with a semiconductor element. As shown in Fig. 1(a), the supporting substrate S may have a conductive layer Sa formed on the surface on which the insulating material layer is formed. The supporting substrate S may also be a substrate having wiring and/or pads on the surface instead of the conductive layer Sa.

The thickness of the support substrate S is preferably in the range of 0.2mm to 2.0mm. If it is thinner than 0.2mm, the operation becomes difficult. On the other hand, if it is thicker than 2.0mm, the material cost tends to be higher. The support substrate S can be a wafer or a panel. There is no special limit on the size. It is better to use a wafer with a diameter of 200mm, a diameter of 300mm or a diameter of 450mm, or a rectangular panel with a side of 300mm~700mm.

As the material constituting the first insulating material layer 1, a photosensitive resin material is preferably used. As the photosensitive insulating material, liquid or film-like materials can be cited. From the perspective of film thickness flatness and cost, a film-like photosensitive insulating material is preferred. In addition, in terms of being able to form fine wiring, the photosensitive insulating material preferably contains a filler (filler) with an average particle size of 500nm or less (preferably 50nm~200nm). The filler content of the photosensitive insulating material is preferably 0 mass parts to 70 mass parts relative to 100 mass parts of the mass of the photosensitive insulating material excluding the filler, and more preferably 10 mass parts to 50 mass parts.

When using a film-like photosensitive insulating material, the lamination step is preferably carried out at the lowest possible temperature. It is better to use a photosensitive insulating film that can be laminated at 40℃~120℃. Photosensitive insulating films that can be laminated at a temperature lower than 40℃ have strong viscosity at room temperature (about 25℃) and tend to be less handleable. Photosensitive insulating films that can be laminated at a temperature higher than 120℃ tend to warp more after lamination.

From the viewpoint of suppressing warp, the thermal expansion coefficient of the first insulating material layer 1 after curing is preferably 80×10 ^-6 /K or less, and more preferably 70×10 ^-6 /K or less in terms of obtaining high reliability. In terms of stress relaxation of the insulating material and the ability to obtain a high-precision pattern, it is preferably 20×10 ^-6 /K or more.

The thickness of the first insulating material layer 1 is preferably less than 10 μm, more preferably less than 5 μm, and further preferably less than 3 μm. From the perspective of insulation reliability, the thickness of the first insulating material layer 1 is preferably within the above range.

<Step of forming a first opening on the surface of the first insulating material layer>

A first opening H1 is formed on the surface of the first insulating material layer 1 and extends to the supporting substrate S or the conductive layer Sa (Fig. 1(b)). In the present embodiment, the first opening H1 is formed to pass through the first insulating material layer 1 along its thickness direction and is composed of a bottom surface (the surface of the conductive layer Sa) and a side surface (insulating material layer 1). When the first insulating material layer 1 is formed of a photosensitive resin material, the first opening H1 can be formed by a photolithography process (exposure and development).

As the exposure method of the photosensitive resin material, the usual projection exposure method, contact exposure method, direct writing exposure method, etc. can be used. As the developing method, it is preferable to use an alkaline aqueous solution of sodium carbonate or tetramethylammonium hydroxide (TMAH). After forming the first opening H1, the first insulating material layer 1 can also be further heated and hardened. For example, it is implemented at a heating temperature of 100°C to 200°C and a heating time of 30 minutes to 3 hours.

The first opening H1 may also be formed on the first insulating material layer 1 by a method other than the photolithography process (e.g., laser ablation, sandblast, water jetting, embossing, etc.). For example, when the first insulating material layer 1 is formed of a thermosetting resin material, laser ablation is preferred from the viewpoint of being able to form the first opening H1. As an opening method by laser ablation, _CO2 laser, UV-YAG laser, etc. may be included, but from the viewpoint of cost, an opening method using _CO2 laser is preferred. The resin residue on the surface of the conductive layer Sa exposed from the first opening H1 may be removed by desmearing treatment. The desmearing treatment may also be used to roughen the surface of the first insulating material layer 1. The surface F shown in FIG1(c) is a surface subjected to the desmearing treatment.

<Step of forming a seed layer on the surface of the first insulating material layer>

A seed layer T is formed on the surface of the first insulating material layer 1 by electroless plating (Fig. 1(d)). In this embodiment, palladium, which serves as a catalyst for electroless copper plating, is first adsorbed on the surface of the first insulating material layer 1, and the surface of the first insulating material layer 1 is cleaned with a pretreatment solution. The pretreatment solution may be a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is 1% to 30%. The immersion time in the pretreatment solution is 1 minute to 60 minutes. The immersion temperature in the pretreatment solution is 25°C to 80°C. After pre-treatment, in order to remove the redundant pre-treatment liquid, tap water, pure water, ultrapure water or organic solvent can be used for cleaning. Furthermore, before the seed crystal layer T is formed on the surface of the first insulating material layer 1, the surface of the first insulating material layer 1 can be modified by ultraviolet irradiation, electron beam irradiation, ozone water treatment, coma discharge treatment, plasma treatment and other methods.

After removing the pre-treatment solution, in order to remove alkaline ions from the surface of the first insulating material layer 1, it is immersed and cleaned with an acidic aqueous solution. The acidic aqueous solution can be a sulfuric acid aqueous solution, which is implemented at a concentration of 1% to 20% and an immersion time of 1 minute to 60 minutes. In order to remove the acidic aqueous solution, tap water, pure water, ultrapure water or an organic solvent can also be used for cleaning.

Then, palladium is attached to the surface of the first insulating material layer 1 after being immersed and cleaned with an acidic aqueous solution. The palladium can be a commercially available palladium-tin colloid solution, an aqueous solution containing palladium ions, a palladium ion suspension, etc., but preferably an aqueous solution containing palladium ions that are effectively adsorbed on the modified layer.

When immersed in an aqueous solution containing palladium ions, the temperature of the aqueous solution containing palladium ions is 25℃~80℃, and the immersion time for adsorption is 1 minute~60 minutes. After adsorbing palladium ions, in order to remove redundant palladium ions, it can also be washed with tap water, pure water, ultrapure water or organic solvent.

After the palladium ions are adsorbed, activation is performed to enable the palladium ions to function as a catalyst. The reagent for activating the palladium ions can be a commercially available activator (activation treatment solution). The activator is immersed in the palladium ion at a temperature of 25°C to 80°C and the immersion time for activation is 1 minute to 60 minutes. After the palladium ion activation, in order to remove the excess activator, it can also be washed with tap water, pure water, ultrapure water or an organic solvent.

Next, electroless copper plating is performed on the surface of the first insulating material layer 1 to form a seed layer T. The seed layer T becomes a power supply layer for electrolytic plating. Examples of electroless copper plating include electroless pure copper plating (purity 99 mass % or more), electroless copper nickel phosphorus plating (nickel content: 1 mass % to 10 mass %, phosphorus content: 1 mass % to 13 mass %), etc. From the perspective of self-adhesion, electroless copper nickel phosphorus plating is preferred. The electroless copper nickel phosphorus plating solution can be a commercially available plating solution, for example, an electroless copper nickel phosphorus plating solution (manufactured by JCU Co., Ltd., trade name "AISL-570") can be used. The electroless copper-nickel-phosphorus plating is carried out in an electroless copper-nickel-phosphorus plating solution at 60°C to 90°C. The thickness of the seed layer T is preferably 20nm to 200nm, more preferably 40nm to 200nm, and even more preferably 60nm to 200nm.

After electroless copper plating, in order to remove the redundant plating solution, tap water, pure water, ultrapure water or organic solvent can be used for cleaning. In addition, after electroless copper plating, in order to improve the adhesion between the seed layer T and the first insulating material layer 1, thermal curing (annealing: aging treatment by heating) can be performed. It is better to heat at a thermal curing temperature of 80℃~200℃. In order to further accelerate the reactivity, it is better to heat at 120℃~200℃, and further preferably at 120℃~180℃. The thermal curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and further preferably 20 minutes to 60 minutes.

<Step of forming an anti-etching agent pattern for wiring section formation>

An anti-etching agent pattern R for forming a wiring portion is formed on the seed layer T (Fig. 2 (a)). The anti-etching agent pattern R may be a commercially available anti-etching agent, for example, a negative film-shaped photosensitive anti-etching agent (manufactured by Hitachi Chemical Co., Ltd., Photec RY-5107UT) may be used. As shown in Fig. 2 (a), the anti-etching agent pattern R has an opening R1 and an opening R2. The opening R1 is provided at a position corresponding to the first opening H1 of the first insulating material layer 1, and is used to form the pad C1. The opening H is formed by the first opening H1 and the opening R1. The opening R2 is, for example, a groove-shaped opening with a line width of 0.5μm to 20μm, and is used to form the wiring C2.

The anti-etching agent pattern R can be formed through the following steps. First, the anti-etching agent is formed into a film using a roll laminator, then the photo tool forming the pattern is brought into close contact, and an exposure machine is used for exposure, and then a sodium carbonate aqueous solution is sprayed for development, thereby forming the anti-etching agent pattern. Furthermore, a positive photosensitive anti-etching agent can also be used instead of a negative one.

<Steps for forming the wiring section>

The seed layer T is used as a power supply layer, for example, electrolytic copper plating is performed to form a wiring portion C including a pad C1 and wiring C2 (Fig. 2 (b)). The thickness of the wiring portion C is preferably 1μm~10μm, more preferably 3μm~10μm, and further preferably 5μm~10μm. Furthermore, the wiring portion C can also be formed by electrolytic plating other than electrolytic copper plating.

<Steps for removing the anti-etching agent pattern>

After electrolytic copper plating, the anti-etching agent pattern R is removed (Fig. 2(c)). The anti-etching agent pattern R can be stripped using a commercially available stripping solution.

<Steps to remove the seed layer>

After removing the anti-etching agent pattern R, the seed layer T is removed (Fig. 2 (d)). While removing the seed layer T, the residual palladium under the seed layer T can be removed. The removal can be performed using a commercially available removal solution (etching solution). As a specific example, an acidic etching solution (manufactured by JCU Co., Ltd., BB-20, PJ-10, SAC-700W3C) can be cited.

<Step of performing the first surface treatment on the surface of the pad C1 and the wiring C2>

The first surface treatment is performed on the surfaces of the pad C1 and the wiring C2 to form a surface treatment layer 5 on these surfaces ( FIG. 3( a )). The first surface treatment can be performed using a commercially available surface treatment solution. As the surface treatment liquid, for example, a liquid containing an organic component that improves the adhesion between the wiring portion C and the second insulating material layer 2 formed in the subsequent step (for example, manufactured by Shikoku Chemical Industries, Ltd., trade name "GliCAP"), or a liquid containing an organic component that micro-etches the surface of the wiring portion C and improves the adhesion between the wiring portion C and the second insulating material layer 2 (for example, manufactured by Atotech Co., Ltd., trade name "NovaBond" and manufactured by MEC Co., Ltd., trade name "CZ8401", "CZ-8402") can be used.

The average roughness Ra of the surface of the wiring portion C (pad C1 and wiring C2) after the first surface treatment is, for example, 40nm~80nm, or 50nm~80nm or 60nm~80nm. By making the average roughness Ra of the surface of the wiring portion C above 40nm, the adhesion between the wiring portion C and the second insulating material layer 2 can be fully ensured. On the other hand, by making the average roughness Ra of the surface of the wiring portion C below 80nm, the transmission loss of the wiring substrate can be fully reduced.

<Step of forming the second insulating material layer>

The second insulating material layer 2 is formed in a manner covering the wiring portion C. The material constituting the second insulating material layer 2 may be the same as or different from that of the first insulating material layer 1.

<Step of forming a second opening on the second insulating material layer>

A second opening portion H2 is formed on the second insulating material layer 2 (Fig. 3(b)). The second opening portion H2 is disposed at a position corresponding to the pad C1. The method for forming the second opening portion H2 may be the same as or different from the method for forming the first opening portion H1. After this step, the peeling strength of the second insulating material layer 2 relative to the wiring C2 is, for example, 0.2 kN/m to 0.7 kN/m, or may be 0.4 kN/m to 0.65 kN/m or 0.5 kN/m to 0.6 kN/m. The peeling strength mentioned here refers to the value measured under the conditions of a peeling angle of 90° and a peeling speed of 10 mm/min. By going through these steps, the wiring substrate 10 shown in Fig. 3(b) is obtained. The wiring substrate 10 includes a supporting substrate S, a pad C1 provided so as to penetrate the first insulating material layer 1 and the second insulating material layer 2, and a wiring layer 8A having wiring C2 embedded in the second insulating material layer 2.

<Step of performing a second surface treatment on the surface of the pad>

By performing a second surface treatment on the surface of the pad C1 in the second opening H2, the surface treatment layer 5 is removed (Fig. 3(c)). As described above, the surface treatment layer 5 contains, for example, an organic component that can hinder the conductivity of the pad C1. By removing at least a portion of the surface treatment layer 5, that is, as shown in Fig. 3(c), by providing a surface treatment agent removal portion 6 on the surface of the pad C1, the reduction in the conductivity of the pad C1 caused by the surface treatment layer 5 can be improved. As treatments for removing the surface treatment layer 5, for example, plasma treatment and desmear treatment (treatment using an alkaline solution) can be listed. The types of gases used in the desmear treatment are, for example, oxygen, argon, nitrogen, and mixed gases thereof. After this step, a wiring board 20 having the structure shown in FIG. 3 (c) is obtained. The wiring board 20 is different from the wiring board 10 shown in FIG. 3 (b) in that a surface treatment agent removal portion 6 is provided on the surface of the pad C1.

<Step of heating the second insulating material layer>

By heating the second insulating material layer 2 to a temperature above the glass transition temperature (Tg) of the second insulating material layer 2, a sintered layer 7 (FIG. 4) is formed at the interface between the wiring portion C and the second insulating material layer 2. Thereby, the adhesion between the wiring portion C and the second insulating material layer 2 is further improved. The sintered layer 7 is, for example, a layer formed by the reaction between the surface treatment agent contained in the surface treatment layer 5 and the second insulating material layer 2 and the modification. The heating temperature is above the glass transition temperature (Tg) of the second insulating material layer 2, for example, below 250°C. The heating time is preferably 30 minutes to 3 hours. By setting the heating temperature to be above Tg and the heating time to be above 30 minutes, the effect of improving the adhesion between the wiring portion C and the second insulating material layer 2 can be fully exerted. On the other hand, by setting the heating temperature to be below 250°C and the heating time to be below 3 hours, the decomposition of the surface treatment agent remaining between the wiring portion C and the second insulating material layer 2 can be suppressed, thereby maintaining the excellent adhesion between the wiring portion C and the second insulating material layer 2. In addition, by setting the heating temperature to be below 250°C, the warping of the wiring substrate can be suppressed. After this step, the wiring substrate 30 having the structure shown in FIG. 4 can be obtained. The wiring substrate 30 is different from the wiring substrate 20 shown in FIG. 3(c) in that a sintered layer 7 is formed at the interface between the wiring portion C and the second insulating material layer 2.

Furthermore, the glass transition temperature of the second insulating material layer mentioned here is the midpoint glass transition temperature value when the hardened second insulating material layer is measured using differential scanning calorimetry (Differential Scanning Calorimeter (DSC), such as "Thermo Plus 2" manufactured by Rigaku). Specifically, the glass transition temperature is the midpoint glass transition temperature calculated by measuring the heat change under the conditions of a heating rate of 10°C/min and a measuring temperature of 30°C~250°C according to Japanese Industrial Standard (JIS) K 7121:1987.

In the above, an embodiment of the method for manufacturing a wiring substrate is described, but the present invention is not necessarily limited to the embodiment described above, and can be appropriately modified within the scope of the gist thereof. For example, although the manufacturing method of a wiring substrate having a single wiring layer 8A is illustrated in the embodiment described above, a wiring substrate having a multi-layered wiring layer can also be manufactured. The multi-layer wiring substrate 40 shown in FIG5 includes, in addition to the structure of the wiring substrate 30, a third insulating material layer 3 and a wiring layer 8B composed of wiring C2 embedded in the third insulating material layer 3. The pad C1 of the multi-layer wiring substrate 40 is arranged to penetrate the first insulating material layer 1, the second insulating material layer 2 and the third insulating material layer 3.

[Implementation example]

The present disclosure is described in more detail by the following examples, but the present invention is not limited to these examples.

[Implementation Example 1]

<Preparation of photosensitive resin film>

Use the following ingredients to prepare a photosensitive resin composition for forming an insulating material layer.

． Photoreactive resin containing carboxyl and ethylenically unsaturated groups: 50 parts by weight of acid-modified cresol novolac type epoxy acrylate (CCR-1219H, manufactured by Nippon Kayaku Co., Ltd., trade name)

． Photopolymerization initiator ingredients: 2,4,6-trimethylbenzyl-diphenyl-phosphine oxide (Darocur TPO, manufactured by BASF Japan Co., Ltd., trade name) and acetone, 1-[9-ethyl-6-(2-methylbenzyl)-9H-carbazole-3-yl]-, 1-(o-acetyl oxime) (IRGACURE OXE-02, manufactured by BASF Japan Co., Ltd., trade name) 5 parts by mass

．Thermosetting agent ingredients: 10 parts by mass of biphenol type epoxy resin (YX-4000, manufactured by Mitsubishi Chemical Co., Ltd., trade name)

． Inorganic filler ingredients: (average particle size: 50nm, obtained by silane coupling treatment with vinyl silane)

The inorganic filler component was formulated in an amount of 10 parts by volume relative to 100 parts by volume of the resin component. Furthermore, the particle size distribution was measured using a dynamic light scattering type Nanotrac particle size distribution meter "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering type Microtrac particle size distribution meter "MT-3100" (manufactured by Nikkiso Co., Ltd.), and it was confirmed that the maximum particle size was less than 1μm.

The solution of the photosensitive resin composition is applied on the surface of a polyethylene terephthalate film (G2-16, manufactured by Teijin Co., Ltd., trade name, thickness: 16 μm). It is dried at 100°C for about 10 minutes using a hot air convection dryer. The thickness of the photosensitive resin film formed in this way is 10 μm.

<Formation of wiring layer with fine wiring>

As a supporting substrate, a wiring substrate with glass cloth (size: 200 mm square, thickness 1.5 mm) was prepared. A copper layer with a thickness of 20 μm was formed on the surface of the wiring substrate.

．Step (A)

The photosensitive resin film (first insulating material layer) is laminated on the surface of the copper layer of the wiring substrate. Specifically, the photosensitive resin film is first placed on the surface of the copper layer of the wiring substrate. Then, a press-type vacuum laminating machine (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.) is used for laminating. The pressing conditions are set as a pressing hot plate temperature of 80°C, a vacuum suction time of 20 seconds, a laminating pressing time of 60 seconds, an air pressure of less than 4kPa, and a pressing pressure of 0.4MPa.

．Step (B)

The insulating material layer after pressing was subjected to exposure and development, thereby providing an opening (first opening) in the first insulating material layer that reaches the copper layer of the wiring substrate. Exposure was performed by placing the patterned optical tool in close contact with the insulating material layer using an i-ray stepper (product name: S6CK exposure machine, lens: ASC3 (Ck), manufactured by Cerma Precision) at an energy of 30 mJ/ ^cm2 . Next, spray development was performed for 45 seconds using a 1 mass% sodium carbonate aqueous solution at 30°C to provide the opening. Next, the surface of the insulating material layer after development was subjected to post-UV exposure at an energy of 2000 mJ/ ^cm2 using a mask exposure machine (EXM-1201 exposure machine, manufactured by ORC Manufacturing Co., Ltd.) and then thermally cured at 170°C for 1 hour in a clean oven.

．Step (C)

A seed layer was formed on the surface of the insulating material layer by electroless copper plating. That is, first, as an alkaline cleaner, it was immersed in a 110 mL/L aqueous solution of an alkaline cleaner (manufactured by JCU Co., Ltd., trade name: EC-B) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as a conditioner, it was immersed in a mixed solution of a conditioning solution (manufactured by JCU Co., Ltd., trade name: PB-200) and EC-B (PB-200 concentration: 70 mL/L, EC-B concentration: 2 mL/L) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as soft etching, the surface was immersed in a mixture of a soft etching solution (manufactured by JCU Co., Ltd., trade name: PB-228) and 98% sulfuric acid (PB-228 concentration: 100 g/L, sulfuric acid concentration: 50 mL/L) at 30°C for 2 minutes, and then immersed in pure water for 1 minute. Next, as descaling, it was immersed in 10% sulfuric acid at room temperature for 1 minute. Next, as a catalyst, the sample was immersed in a mixed solution of Catalyst Reagent 1 (manufactured by JCU Co., Ltd., trade name: PC-BA), Catalyst Reagent 2 (manufactured by JCU Co., Ltd., trade name: PB-333) and EC-B (PC-BA concentration: 5 g/L, PB-333 concentration: 40 mL/L, EC-B concentration: 9 mL/L) at 60°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as an accelerator, the sample was immersed in a mixed solution of Accelerator Reagent (manufactured by JCU Co., Ltd., trade name: PC-66H) and PC-BA (PC-66H concentration: 10 mL/L, PC-BA concentration: 5 g/L) at 30°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as electroless copper plating, it was immersed in a mixture of electroless copper plating solution (manufactured by JCU Co., Ltd., trade name: AISL-570B, AISL-570C, AISL-570MU) and PC-BA (AISL-570B concentration: 70mL/L, AISL-570C concentration: 24mL/L, AISL-570MU concentration: 50mL/L, PC-BA concentration: 13g/L) at 60°C for 7 minutes, and then immersed in pure water for 1 minute. Then dried on a heating plate at 85°C for 5 minutes. Then, thermal annealed in an oven at 180°C for 1 hour.

．Step (D)

Using a vacuum laminating machine (V-160 manufactured by Nichigo Morton Co., Ltd.), a wiring forming anti-etching agent (RY-5107UT manufactured by Hitachi Chemical Co., Ltd.) was vacuum laminated on a 200 mm□ substrate with or without electrolytic copper film. The laminating temperature was 110°C, the laminating time was 60 seconds, and the laminating pressure was 0.5 MPa.

After vacuum lamination, the film was left for 1 day, and then exposed to the wiring forming resist using an i-ray stepper (product name: S6CK exposure machine, lens: ASC3 (Ck), manufactured by Cerma Precision Co., Ltd.). The exposure amount was 140 mJ/cm ² , and the focus was -15 μm. After exposure, the film was left for 1 day, and the protective film of the wiring forming resist was peeled off. The film was developed using a spray developer (Mikasa Co., Ltd., AD-3000). The developer was a 1.0% sodium carbonate aqueous solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa. Thereby, a resist pattern for forming the following L/S (line/space) wiring is formed on the seed layer.

．L/S=20μm/20μm (Number of wiring lines: 10)

．L/S=15μm/15μm (Number of wiring lines: 10)

．L/S=10μm/10μm (Number of wiring lines: 10)

．L/S=7μm/7μm (Number of wiring lines: 10)

．L/S=5μm/5μm (Number of wiring: 10)

．L/S=3μm/3μm (Number of wiring lines: 10)

．L/S=2μm/2μm (Number of wiring lines: 10)

．Step (E)

The surfaces were immersed in a 100 mL/L aqueous solution of a cleaning agent (manufactured by OKUNO CHEMICAL CO., LTD., trade name: ICP CLEAN S-135) at 50°C for 1 minute, immersed in pure water at 50°C for 1 minute, immersed in pure water at 25°C for 1 minute, and immersed in a 10% sulfuric acid aqueous solution at 25°C for 1 minute. Next, electrolytic plating was performed at 25°C and a current density of 1.5 A/dm 2 for 10 minutes in an aqueous solution obtained by adding 0.25 mL of hydrochloric acid, 10 mL of TOP LUCINA GT-3, a trade name of Okuno Pharmaceutical Co., Ltd., and 1 mL of TOP LUCINA GT-2, a trade name of Okuno Pharmaceutical Co., Ltd., to 7.3 L of an aqueous solution of ¹²⁰ g/L of copper sulfate pentahydrate and 220 g/L of 96% sulfuric acid. Then, the surface was immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes.

．Step (F)

A spray developer (Mikasa AD-3000) was used to strip the anti-etching agent used for wiring formation. The stripping liquid was a 2.38% TMAH aqueous solution, the stripping temperature was 40°C, and the spray pressure was 0.2MPa.

．Step (G)

The electroless copper and palladium catalysts used as the seed layer were removed. For electroless Cu etching, the sample was immersed in an etchant (SAC-700W3C manufactured by JCU Co., Ltd.), 98% sulfuric acid, 35% hydrogen peroxide, and an aqueous solution of copper sulfate-pentahydrate (SAC-700W3C concentration: 5 volume%, sulfuric acid concentration: 4 volume%, hydrogen peroxide concentration: 5 volume%, copper sulfate-pentahydrate concentration: 30 g/L) at 35°C for 1 minute. Next, for palladium catalyst removal, the sample was immersed in an FL aqueous solution (FL-A 500 mL/L, FL-B 40 mL/L manufactured by JCU Co., Ltd.) at 50°C for 1 minute. Then, immerse in pure water at 25°C for 5 minutes and dry on a hot plate at 80°C for 5 minutes.

．Step (H)

The surface of the pad and wiring was treated with GliCAP (manufactured by Shikoku Chemical Industries, Ltd.) (first surface treatment). As an acid wash, immerse in a 3.5% hydrochloric acid aqueous solution at 25°C for 1 minute. Then, wash with pure water at 25°C for 1 minute. Then, immerse in a soft etching liquid (manufactured by Shikoku Chemical Industries, Ltd., GB-1000) at 30°C for 1 minute. Then, wash with pure water at 25°C for 1 minute. Then, immerse in a surface treatment agent (manufactured by Shikoku Chemical Industries, Ltd., GliCAP) at 30°C for 15 minutes. Then, wash with pure water at 25°C for 1 minute. Then, dry on a 100°C hot plate for 5 minutes.

．Step (I)

The photosensitive resin film (second insulating material layer) is laminated so as to cover the solder pads and wirings that have been surface treated in step (H). Specifically, the photosensitive resin film is first placed on the first insulating material layer so as to cover the solder pads and wirings. Then, a press-type vacuum laminating press (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.) is used for laminating. The pressing conditions are a pressing hot plate temperature of 80°C, a vacuum suction time of 20 seconds, a laminating time of 60 seconds, an air pressure of 4 kPa or less, and a pressing pressure of 0.4 MPa.

．Step (J)

The insulating material layer after pressing is subjected to exposure and development, thereby setting an opening (second opening) to the pad on the second insulating material layer. Exposure is performed by bringing the optical tool formed with the pattern into close contact with the insulating material layer, using an i-ray stepper (product name: S6CK exposure machine, lens: ASC3 (Ck), manufactured by Cerma Precision) with an energy of 30mJ/ ^cm2 . Then, spray development is performed for 45 seconds using a 1 mass% sodium carbonate aqueous solution at 30°C to set the opening. Next, the surface of the developed insulating material layer was subjected to post-UV exposure at an energy of 2000mJ/ ^cm2 using a mask exposure machine (EXM-1201 exposure machine, manufactured by ORC Manufacturing Co., Ltd.). Then, heat curing was performed at 170°C for 1 hour in a clean oven. The glass transition temperature (Tg) of the cured second insulating material layer was 160°C.

[Example 2]

A wiring board was obtained in the same manner as in Example 1, except that in step (H), NovaBond (manufactured by Atotech Japan Co., Ltd.) was used for surface treatment instead of GliCAP. That is, first, it was immersed in a 15 mL/L aqueous solution of NovaBond IT Stabilizer (manufactured by Atotech Japan Co., Ltd.) at 50°C for 1 minute. Then, it was washed with pure water at 25°C for 1 minute. Then, it was immersed in a 30 mL/L aqueous solution of NovaBond IT (manufactured by Atotech Japan Co., Ltd.) at 50°C for 1 minute. Then, it was washed with pure water at 25°C for 1 minute. Then, immerse in 20 mL/L of an aqueous solution of NovaBond IT Reducer (manufactured by Atotech Co., Ltd., Japan) at 30°C for 5 minutes. Then, wash with pure water at 25°C for 1 minute. Then, immerse in 10 mL/L of an aqueous solution of NovaBond IT Protector MK (manufactured by Atotech Co., Ltd., Japan) at 35°C for 1 minute. Then, wash with pure water at 25°C for 1 minute. Then, dry with a 100°C hot plate for 5 minutes.

[Implementation Example 3]

A wiring board was obtained in the same manner as in Example 1, except that in step (H), CZ8401 (manufactured by MEC Co., Ltd.) was used instead of GliCAP for surface treatment. That is, first, as an acid wash, a 5% hydrochloric acid aqueous solution was sprayed at a water pressure of 0.2 MPa at 25°C for 30 seconds. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a CZ8401 treatment solution at a water pressure of 0.2 MPa at 25°C for 1 minute. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a 10% sulfuric acid aqueous solution at a water pressure of 0.1 MPa at 25°C for 20 seconds. Next, wash with pure water at 25°C for 1 minute. Then, dry with a hot plate at 100°C for 5 minutes.

[Implementation Example 4]

A wiring board was obtained in the same manner as in Example 1, except that in step (H), CZ8402 (manufactured by MEC Co., Ltd.) was used instead of GliCAP for surface treatment. That is, first, as an acid wash, a 5% hydrochloric acid aqueous solution was sprayed at a water pressure of 0.2 MPa at 25°C for 30 seconds. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a CZ8402 treatment solution at a water pressure of 0.2 MPa at 25°C for 1 minute. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a 10% sulfuric acid aqueous solution at a water pressure of 0.1 MPa at 25°C for 20 seconds. Next, wash with pure water at 25°C for 1 minute. Then, dry with a hot plate at 100°C for 5 minutes.

[Comparison Example 1]

A wiring board was obtained in the same manner as in Example 1 except that no surface treatment agent was used in step (H). That is, first, as an acid cleaning, a 5% hydrochloric acid aqueous solution was sprayed at a water pressure of 0.2 MPa at 25°C for 30 seconds. Then, pure water was used for running water cleaning at 25°C for 1 minute. Then, it was dried on a heating plate at 100°C for 5 minutes.

[Comparison Example 2]

A wiring board was obtained in the same manner as in Example 1, except that in step (H), CZ8101 (manufactured by MEC Co., Ltd.) was used instead of GliCAP for surface treatment. That is, first, as an acid cleaning, a 5% hydrochloric acid aqueous solution was sprayed at a water pressure of 0.2 MPa at 25°C for 30 seconds. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a CZ8101 treatment solution at a water pressure of 0.2 MPa at 25°C for 1 minute. Then, it was washed with pure water at 25°C for 1 minute. Then, it was sprayed with a 10% sulfuric acid aqueous solution at a water pressure of 0.1 MPa at 25°C for 20 seconds. Then, it was washed with pure water at 25°C for 1 minute. Next, as a rust-proof treatment, immersion treatment was performed at 25°C for 30 seconds using CL-8300 (manufactured by MEC Co., Ltd.). Next, washing was performed using pure water at 25°C for 1 minute. Then, drying was performed using a 100°C hot plate for 5 minutes.

<Measurement of the average roughness Ra of the copper layer surface>

The average roughness Ra of the copper layer surface of Example 1 (surface treatment by Glicap), Example 2 (surface treatment by NovaBond), Example 3 (surface treatment by CZ-8401), Example 4 (surface treatment by CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a surface roughness meter (OLS-4000 manufactured by Olympus Corporation). The results are shown in Table 1.

<Determination of peel strength at the interface between copper layer and insulating material layer>

The peel strength of the interface between the copper layer and the insulating material layer of Example 1 (surface treatment by Glicap), Example 2 (surface treatment by NovaBond), Example 3 (surface treatment by CZ-8401), Example 4 (surface treatment by CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a peel strength measuring device (ES-Z manufactured by Shimadzu Corporation). The measuring conditions were set to a peel angle of 90° and a peel speed of 10 mm/min. The results are shown in Table 1.

<Evaluation of wiring formativeness>

For the wiring formation properties of L/S of 20μm/20μm, 15μm/15μm, 10μm/10μm, 7μm/7μm, 5μm/5μm, 3μm/3μm, and 2μm/2μm, the case where there were no wiring collapses, wiring peeling, or wiring disconnections among 10 wirings was set as "A", the case where there were 1 to 2 wirings was set as "B", and the case where there were 3 or more wirings was set as "C". The results are shown in Table 1.

．Step (K)

The solder pad surfaces of the wiring substrates of Examples 1 to 4 and Comparative Examples 1 and 2 were subjected to desmear treatment (second surface treatment). That is, first, in order to perform a swelling treatment, the pads were immersed in 40 mL/L of SWELLA (Cleaner Securiganth 902 manufactured by Atotech) at 70°C for 5 minutes. Then, the pads were immersed in pure water for 1 minute. Next, in order to remove the surface treatment agent, the pads were immersed in 40 mL/L of desmear liquid (Compact CP manufactured by Atotech) at 70°C. The immersion time was 3 minutes. Then, the pads were immersed in pure water for 1 minute. Then, dry on a hot plate at 80°C for 5 minutes.

<Evaluation of the removability of surface treatment agents>

The surface treatment agent removability of Examples 1 to 4 and Comparative Examples 1 and 2 was evaluated. For the openings of Φ100μm, Φ50μm, Φ30μm, Φ20μm, and Φ10μm, a micro-Raman device (product name: DXR2 Microscope, manufactured by Thermo Fisher Scientific Co., Ltd.) was used to check whether there was a peak of 900cm ^-1 on the exposed copper surface. Among the 10 pads, the case with 0 peaks (slag) was set as "A", the case with 1 to 2 peaks was set as "B", and the case with 3 or more peaks was set as "C". The results are shown in Table 2.

[Example 1a~Example 4d and Comparative Example 1a~Comparative Example 2d]

．Step (L)

Prepare multiple wiring substrates of Examples 1 to 4 and Comparative Examples 1 and 2, as shown in Table 3, and heat them at 200°C or 250°C for 30 minutes or 3 hours, respectively.

<Evaluation of electrical insulation>

The electrical insulation of the wiring substrates of Example 1a to Example 4d and Comparative Example 1a to Comparative Example 2d was evaluated. For wirings with L/S of 20μm/20μm, 15μm/15μm, 10μm/10μm, 7μm/7μm, 5μm/5μm, 3μm/3μm, and 2μm/2μm, the test was conducted using a highly accelerated life tester (HAST CHAMBER) (EHS-222MD, manufactured by ESPEC) and an ion migration evaluation system (AM-150-U-5, manufactured by ESPEC), under the conditions of electrical insulation of 130°C, relative humidity of 85%, and applied voltage of 3.3V. Among the 10 wirings, 10 wirings with a resistance value of 1×10 ⁶ Ω and an insulation retention time of 200 hours or more were designated as "A", 7 or more wirings were designated as "B", and 5 or more wirings were designated as "C". The results are shown in Table 3.

<Evaluation of heat resistance>

The heat resistance of the wiring substrates of Example 1a to Example 4d and Comparative Example 1a to Comparative Example 2d was evaluated. For wirings with L/S of 20μm/20μm, 15μm/15μm, 10μm/10μm, 7μm/7μm, 5μm/5μm, 3μm/3μm, and 2μm/2μm, the test was conducted using a highly accelerated life tester (HAST CHAMBER) (EHS-222MD, manufactured by ESPEC) at a temperature of 130°C, a relative humidity of 85%, and a holding time of 500 hours. After the heat resistance test, the wiring cross section was observed with a scanning electron microscope (Regulus 8230 manufactured by Hitachi High-tech) to observe the copper oxide (CuO) film thickness on the wiring surface and whether the wiring and insulating material were peeled off. When the thickness of copper oxide (CuO) was less than 50nm, it was set as "A", when it was less than 80nm, it was set as "B", and when it was less than 150nm, it was set as "C". The evaluation results of copper oxide thickness are shown in Table 4. After the heat resistance test, among 10 wirings, 10 wirings without peeling were set as "A", 7 or more wirings were set as "B", and 5 or more wirings were set as "C". The evaluation results of peeling are shown in Table 5.

[Table 5]

[Industrial availability]

According to the present disclosure, a method for manufacturing a wiring substrate having sufficient adhesion and heat resistance between the wiring portion and the insulating material layer and sufficient insulation reliability is provided.

1: First insulating material layer

2: Second insulating material layer

6: Surface treatment agent removal part

7: Firing layer

8A: Wiring layer

30: Wiring board

C1: Solder pad

C2: Wiring

H2: Second opening

S: Supporting substrate

Sa: Conductive layer

T: Seed layer

Claims (8)

A method for manufacturing a wiring substrate comprises: (A) forming a first insulating material layer on a supporting substrate; (B) forming a first opening portion on the first insulating material layer; (C) forming a seed layer on the surface of the first insulating material layer by electroless plating; (D) providing an anti-etching agent pattern for forming a wiring portion on the surface of the seed layer; (E) forming a wiring portion including a pad and wiring by electrolytic plating on the surface of the seed layer and in the area exposed from the anti-etching agent pattern; (F) removing the anti-etching agent pattern; (G) removing the seed layer exposed by the removal of the anti-etching agent pattern; (H) performing a first surface treatment on the surface of the wiring portion (I) forming a second insulating material layer in a manner covering the wiring portion; (J) forming a second opening portion in the second insulating material layer at a position corresponding to the solder pad; (K) performing a second surface treatment on the surface of the solder pad; and (L) heating the second insulating material layer to a temperature above the glass transition temperature of the second insulating material layer, wherein in the step of performing the first surface treatment, a surface treatment layer containing an organic component for improving the adhesion between the wiring portion and the second insulating material layer is formed on the surface of the wiring portion, and in the step of heating the second insulating material layer, a sintered layer is formed at the interface between the wiring portion and the second insulating material layer. A method for manufacturing a wiring board as described in claim 1, wherein, in the step of performing the second surface treatment, the surface treatment layer is removed from the surface of the pad. A method for manufacturing a wiring board as described in claim 1 or claim 2, wherein the second surface treatment is at least one selected from the group consisting of oxygen plasma treatment, argon plasma treatment, and desmear treatment. A method for manufacturing a wiring substrate as described in claim 1 or claim 2, wherein the average roughness Ra of the surface of the wiring portion subjected to the first surface treatment is 40nm~80nm. A method for manufacturing a wiring substrate as described in claim 1 or claim 2, wherein after step (J), the peeling strength of the second insulating material layer relative to the wiring is 0.2 kN/m to 0.7 kN/m. The method for manufacturing a wiring board as described in claim 1 or claim 2, wherein between step (B) and step (C), a step of removing residues on the first insulating material layer and/or in the first opening is further included. A method for manufacturing a wiring board as described in claim 1 or claim 2, wherein at least one of the first insulating material layer and the second insulating material layer contains a photosensitive resin. A method for manufacturing a wiring board as described in claim 1 or claim 2, wherein the anti-etching agent pattern has a groove-shaped opening with a line width of 0.5μm to 20μm.