TWI865124B - Method for preparing memory array with contact enhancement cap - Google Patents

Abstract

The present disclosure provides a method for preparing a dynamic random access memory (DRAM) array with a contact enhancement cap. The method includes: forming a trench at a front side of a semiconductor substrate, wherein the trench defines laterally separate active areas formed of surface regions of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than top surfaces of the active areas; recessing a first group of the active areas from top surfaces of the first group of the active areas, while having top surfaces of a second group of the active areas covered; and integrally forming contact enhancement sidewall spacers to laterally surround top portions of the active areas, respectively and contact enhancement layers on the top surfaces of the active areas.

Description

Method for preparing memory array with contact enhancement top cover

This application is a division of application No. 111103756 filed on January 27, 2022. Application No. 111103756 claims priority and benefits to U.S. formal application No. 17/528,505 and U.S. formal application No. 17/528,617 filed on November 17, 2021, the contents of which are incorporated herein by reference in their entirety.

The present disclosure provides a memory array and a preparation method thereof, and more particularly, relates to a dynamic random access memory (DRAM) array with a contact enhanced top cover and a preparation method thereof.

In recent decades, with the continuous improvement of electronic products, the demand for storage capacity has also increased. In order to increase the storage capacity of memory devices (e.g., DRAM devices), more memory cells are arranged in the memory device, and the size of each memory cell in the memory device becomes smaller. These memory cells are respectively manufactured on an active region, which can be a part of the semiconductor substrate. Scaling of the active region is an option to reduce the size of each memory cell.

Each DRAM cell may include a storage capacitor disposed on an active area and connected to the active area via a capacitor contact. A reduction in the active area may result in a reduction in the landing area of the capacitor contact. Therefore, due to the semiconductor lithography overlay problem, the contact resistance between the capacitor contact and the active area may increase. In other words, pursuing high storage density by minimizing the active area may compromise the performance of the DRAM element. The art needs a method for increasing the landing area of the capacitor contact without expanding the layout pattern of the active area.

The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not set the prior art of the present disclosure, and any description of the above “prior art” should not be used as any part of the present case.

In one embodiment of the present disclosure, a method for preparing a memory array is provided, comprising: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface area of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of one of the active regions; A first group of active areas of the active areas is recessed from a top surface, and a second group of active areas of the plurality of active areas is covered at the same time; and a plurality of contact-enhanced side wall spacers and a plurality of contact-enhanced top covers are integrally formed, wherein the contact-enhanced side wall spacers laterally surround the tops of the active areas, and the contact-enhanced top covers cover the upper surfaces of the active areas.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages of the subject matter of the disclosure patent scope of the present disclosure will be described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached disclosure patent scope.

The following disclosure provides a number of different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the size of the component is not limited to the disclosed range or value, but may depend on the process conditions and/or the desired properties of the component. In addition, the following description of forming a first feature "above" or "on" a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, thereby making the first feature and the second feature not in direct contact. For the sake of brevity and clarity, some features may be arbitrarily drawn in different proportions. In the accompanying figures, some layers/features may be omitted for simplicity.

Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation shown in the figure. The element may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

FIG1A is a circuit diagram illustrating a memory cell 100 in a memory array of one of some embodiments of the present disclosure. Referring to FIG1A , the memory array may be a dynamic random access memory (DRAM) array structure. Each memory cell 100 in the memory array may include an access transistor AT and a storage capacitor SC. The access transistor AT may be a field effect transistor (FET). One terminal of the storage capacitor SC is coupled to the source and/or drain terminal of the access transistor AT, and the other terminal of the storage capacitor SC may be coupled to a reference voltage (e.g., a ground voltage as described in FIG1A ). When the access transistor AT is turned on, the storage capacitor SC can be accessed. On the other hand, when the access transistor AT is in the off state, the storage capacitor SC cannot be accessed.

During a write operation, the access transistor AT is turned on by establishing that the word line WL is coupled to a gate terminal of the access transistor AT, and the voltage applied to the bit line BL (coupled to a source/or drain terminal of the access transistor AT) can be transferred to the storage capacitor SC (coupled to the other source/or drain terminal of the access transistor AT). Therefore, the storage capacitor SC can be charged or discharged, and a logic state "1" or a logic state "0" can be stored in the storage capacitor SC. During a read operation, the access transistor AT is also turned on, and the pre-charged bit line BL can be pulled high or low according to the charge state of the storage capacitor SC. By comparing the voltage of the bit line BL and the precharge voltage, the charge state of the storage capacitor SC can be sensed, and the logic state of the memory cell 100 can be identified.

FIG. 1B is a structural diagram illustrating a memory array 10 including a plurality of memory cells 100 according to some embodiments of the present disclosure. Referring to FIG. 1B , the memory array 10 has rows and columns. The memory cells 100 of each row may be arranged along a first direction, and the memory cells 100 of each column may be arranged along a second direction intersecting the first direction. A plurality of bit lines BL may be coupled to a row of the memory cells 100, respectively. On the other hand, a plurality of word lines WL may be coupled to a row of the memory cells 100, respectively. In some embodiments, during a write operation, a word line WL coupled to a selected memory cell 100 is asserted, and a storage capacitor SC in the selected memory cell 100 is programmed by providing a voltage to a bit line coupled to the selected memory cell 100. In addition, during a read operation, all bit lines BL are precharged, and a word line WL coupled to a selected memory cell 100 is asserted, and then the precharged bit line BL is pulled up or down by the storage capacitor SC coupled to the asserted word line WL, respectively. By detecting a voltage change of the bit line BL coupled to the selected memory cell 100, the logic state of the selected memory cell 100 can be identified. Due to the high/low precharge bit line BL, the storage charge in the storage capacitor SC of the memory cell 100 coupled to the established word line WL is changed. In order to restore the logic state of these memory cells 100, a write operation can be performed after the read operation to program the previous logic state to these memory cells 100. This write operation can also be called a refresh operation.

FIG. 2A is a plan view illustrating a partial layout of a memory array 10 according to some embodiments of the present disclosure.

1B and 2A , the memory array 10 may be built on a semiconductor substrate 200. The semiconductor substrate 200 may be, for example, a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. The semiconductor substrate 200 has surface portions that are laterally separated from each other, referred to as active areas AA. An isolation structure 202 extending in the semiconductor substrate 200 may laterally surround each active area AA to physically and electrically isolate the active areas AA from each other. In other words, the active area AA is defined by the isolation structure 202.

According to some embodiments, the active area AA may be arranged in an array having a plurality of rows and a plurality of columns. Word lines WL may be formed in the semiconductor substrate 200, and each word line laterally penetrates a row of the active area AA. On the other hand, bit lines BL may be formed on the semiconductor substrate 200, and each intersects a column of the active area AA.

The access transistor AT in each memory cell 100 of the memory array 10 is defined near the intersection of the active area AA with the penetrating word line WL and the intersecting bit line BL. The word line WL serves as the gate terminal of the access transistor AT, and the portion of the active area AA located on opposite sides of the word line WL can serve as the source and/or drain terminal of the access transistor AT. The bit line BL is coupled to one of the source and/or drain terminals. In addition, the other source and/or drain terminal can be coupled to one of the storage capacitors SC formed above the semiconductor substrate 200. It should be understood that the storage capacitor SC is depicted as an independent pattern to represent an independent bottom electrode of the storage capacitor SC. Although not shown, the storage capacitors SC may actually have a common top electrode.

In some embodiments, the word lines WL extend along a first direction. In addition, the bit lines BL may extend along a second direction substantially perpendicular to the first direction. Optionally, each bit line BL may form a curve along its extension direction (e.g., the second direction). In addition, the active areas AA may each extend along a third direction intersecting the first direction and the second direction.

In some embodiments, each active area AA is shared by two access transistors AT having a common source and/or drain terminal. In these embodiments, each active area AA is penetrated by two word lines WL and intersects with one of the bit lines BL. In addition, each active area AA can overlap with two storage capacitors SC. The bit line BL overlaps with and is electrically connected to a portion of the active area AA spanning between the two word lines WL, and this portion of the active area AA can serve as a common source and/or drain terminal of the two access transistors AT. The other portions of the active area AA located on opposite sides of the two word lines WL can serve as separate source and/or drain terminals of the two access transistors AT, and can overlap and be electrically connected to two covering storage capacitors SC, respectively.

FIG. 2B is a cross-sectional view illustrating edge portions of two adjacent active areas AA and a portion of an isolation structure 202 extending between the adjacent active areas AA according to some embodiments of the present disclosure.

2B , the isolation structure 202 is formed in a trench TR of the semiconductor substrate 200, the trench TR extending from the top surface of the semiconductor substrate 200 into the semiconductor substrate 200 and laterally separating the active areas AA. In addition, some active areas AA may be recessed relative to other active areas AA, and the top surface of the semiconductor substrate 200 in some areas of those recessed active areas AA may be lower than other areas of the non-recessed active areas AA. As shown in the example depicted in FIG. 2B , one active area AA (also referred to as active area AA1) is recessed relative to an adjacent active area AA (also referred to as active area AA2). Therefore, a height H1 of the active area AA1 (measured from a depth flush with the bottom end of the isolation structure 202 to a top surface TS1 of the active area AA1) is smaller than a height H2 of the active area AA2 (measured from a depth flush with the bottom end of the isolation structure 202 to a top surface TS2 of the active area AA2).

Since the active areas AA1 and AA2 have different heights, the trench TR extending between the active areas AA1 and AA2 may have an asymmetric shape. As shown in the example depicted in FIG. 2B , i.e., the active area AA1 is concave relative to the active area AA2, the sidewall SW1 of the trench TR defining the boundary of the active area AA1 may be lower than the sidewall SW2 of the trench TR defining the boundary of the active area AA2. The heights of the sidewalls SW1 and SW2 are substantially equal to the heights of H1 and H2, respectively. To avoid redundancy, the ratio and range of the heights H1 and H2 are not repeated.

According to some embodiments, the top surface TS ₂₀₂ of the isolation structure 202 filled in the trench TR is lower than the top surface TS1 of the active area AA1 and lower than the top surface TS2 of the active area AA2. In these embodiments, the height H ₂₀₂ of the isolation structure 202 (measured from the bottom of the isolation structure 202 to the top surface TS ₂₀₂ of the isolation structure 202) is smaller than the height H1 of the active area AA1 and smaller than the height H2 of the active area AA2. Since the isolation structure 202 does not fill the trench TR, the tops of the sidewalls SW1 and SW2 of the trench TR are not covered by the isolation structure 202. Since the sidewall SW2 is higher than the sidewall SW1, the top of the sidewall SW2 crossing over the isolation structure 202 may be larger (higher) than the top of the sidewall SW1 crossing over the isolation structure 202.

In some embodiments, the top of each active area AA is laterally surrounded by a contact enhancement cap 204, and the rest of each active area AA is laterally surrounded by an isolation structure 202. The contact enhancement cap 204 is semi-conductive or conductive and can serve as an additional portion of the active area AA. By having such an additional portion, the active area AA can provide a larger landing area for the capacitor contact CC connecting the active area AA and the upper storage capacitor SC, as shown in FIG. 2A. Therefore, the allowance for the setting tolerance of the capacitor contact CC can be increased, and good electrical contact between the capacitor contact CC and the active area AA can be ensured. For example, the contact enhancement cap 204 includes silicon fabricated using an epitaxy process.

Since the active area AA1 protrudes less than the active area AA2 relative to the isolation structure 202, the height H _204-1 of the contact enhancement top cap 204-1 laterally surrounding the top of the active area AA1 can be shorter than the height H _204-2 of the contact enhancement top cap 204-2 laterally surrounding the top of the active area AA2. The height _H204-1 is measured from the bottom end of the contact enhancement top cap 204-1, which can be flush with the top surface TS ₂₀₂ of the isolation structure 202, to the top end of the contact enhancement top cap 204-1. Likewise, height H _204-2 is measured from the bottom of the contact enhancement cap 204-2, which may be flush with the top surface TS ₂₀₂ of the isolation structure 202, to the top of the contact enhancement cap 204-2. Because the contact enhancement caps 204-1, 204-2 extend to different heights from the top surface TS ₂₀₂ of the isolation structure 202, the top corners of the contact enhancement caps 204-1, 204-2 may have a significant lateral thickness (not shown) and may be more spaced apart in the vertical direction. Therefore, the contact enhancement caps 204-1 and 204-2 can be prevented from merging, especially when the width of the trench TR between the active areas AA1 and AA2 is further reduced. Therefore, interference between the memory cells 100 formed on the adjacent active areas AA can be avoided.

In some embodiments, the top surface of each active area AA is covered by a self-assembly monolayer (SAM) 206. The self-assembly monolayer 206 may be selectively formed on the top surface of each active area AA and may not extend to the sidewalls of each active area AA. That is, the top of the sidewall of each active area AA across the isolation structure 202 will not be covered by the SAM 206. Therefore, the contact enhancement top cap 204 formed after the SAM 206 may be disposed on the top of the sidewall of the active area AA. According to some embodiments, the contact enhancement top cap 204 may further extend to the sidewalls of the SAM 206. In these embodiments, the top of the contact enhancement cap 204 can be substantially flush with the top surface of the SAM 206.

Since the active area AA1 is concave relative to the active area AA2, the top surface TS1 of the active area AA1 is lower than the top surface TS2 of the active area AA2. Therefore, the SAM 206 (also referred to as SAM 206-1) covering the top surface TS1 of the active area AA1 is lower than the SAM 206 (also referred to as SAM 206-2) covering the top surface TS2 of the active area AA2.

Self-assembled monolayers (SAMs) are well known in the art. For example, see "Reactive Monolayers in Directed Additive Manufacturing - Area Selective Atomic Layer Deposition" Rudy J. Wojtecki et al., Journal of Photopolymer Science and Technology, 2018 Volume 31 Issue 3 Pages 431-436, which is incorporated herein by reference. In some embodiments, SAMs 206 include organic molecules. According to some embodiments, SAMs 206 include a plurality of molecules having a chemical formula selected from X-R1-SH, X-R1-SS-R2-Y, R1-S-R2, and combinations thereof, wherein R1 and R2 are independent carbon chains or carbon chains interrupted by at least one impurity atom, wherein H is hydrogen, wherein S is sulfur, and wherein X and Y are chemical groups that do not substantially react with the copper surface. In some embodiments, at least one of R1 and R2 is a chain of n carbon atoms, wherein n is an integer from 1 to 30. In some embodiments, the chemical formula of SAMs 206 is SH(CH ₂ ) ₉ CH ₃ .

In some embodiments, the SAM is made by a self-assembled monolayer of polymerizable compounds. The thickness of the monolayer corresponds to the length of one molecule of the compound in the densely packed structure of the monolayer. The densely packed structure is assisted by the functional groups of the compound, which bind to the surface groups of the substrate through electrostatic interactions and/or one or more covalent bonds. The portion of the compound that binds to the surface of the substrate is referred to herein as the "head" of the compound. The remaining portion of the compound is referred to as the "tail". The tail extends from the head of the compound to the air interface on the top of the SAM. The tail has a non-polar peripheral end group at the air interface. Therefore, a good SAM has few defects in its densely packed structure and can show a high contact angle.

The head of the SAM-forming compound can be selectively bonded to a portion of a substrate top surface that includes a region of a different composition, leaving other portions of the substrate top surface without or substantially without the SAM-forming compound disposed thereon. In this case, a patterned initial SAM can be formed in one step by immersing the substrate in a solution of a given SAM-forming compound (dissolved by an appropriate solvent). In some embodiments, the wavelength of the ultraviolet radiation can be from about 4 nanometers (nm) to 450 nanometers. The wavelength of the deep ultraviolet (DUV) radiation can be from 124 nanometers to 300 nanometers. The wavelength of the extreme ultraviolet (EUV) radiation can be from about 4 nanometers to less than 124 nanometers.

In those embodiments where each active area AA is covered by SAM 206, a capacitor contact CC disposed on the active area AA may penetrate SAM 206 to establish electrical contact with the active area AA. Similarly, other contacts (e.g., bit line contacts (not shown)) may also pass through SAM 206 to reach the active area AA. In addition, in some embodiments, a capacitor contact CC extending to a lower active area AA may be higher than a capacitor contact CC extending to a higher active area AA. As illustrated in FIG. 2B , a capacitor contact CC extending to active area AA1 (also referred to as capacitor contact CC1) may be higher than a capacitor contact CC extending to active area AA2 (also referred to as capacitor contact CC2).

As described above, the active area AA of the memory cell 100 in the memory array 10 has additional portions (i.e., contact enhancement caps 204) at its top corners. By having more of these additional portions, the active area AA can provide a larger landing area for the capacitor contacts CC standing on the active area AA. Therefore, the electrical contact between the capacitor contacts CC and the active area AA can be less affected by process variations (such as lithography coverage issues) for setting the capacitor contacts CC. In other words, the electrical contact between the capacitor contacts CC and the active area AA can be improved. In addition, adjacent active areas AA are designed to have different heights, and the top surface of one active area AA can be recessed relative to the top surface of an adjacent active area AA. Therefore, the additional portion of the adjacent active area AA, that is, the portion formed at the top corner of the active area AA, can be further spaced apart in the vertical direction. Therefore, the adjacent active areas AA can be prevented from merging together, thereby avoiding interference between the memory cells 100 formed on the adjacent active areas AA.

FIG3 is a flow chart illustrating a method for preparing the structure shown in FIG2B of some embodiments of the present disclosure. FIG4A to FIG4K are plan views illustrating a structure at an intermediate stage of the preparation method shown in FIG3 of some embodiments of the present disclosure. FIG5A to FIG5K are cross-sectional views illustrating a structure at an intermediate stage of the preparation method shown in FIG3 of some embodiments of the present disclosure. In particular, FIG5B is a cross-sectional view illustrating a structure taken along the A-A' line shown in FIG4B, and FIG5C to FIG5K are cross-sectional views illustrating a structure taken along the BB' line shown in FIG4C to FIG4K.

3, 4A and 5A, step S11 is performed, and a first insulating layer 300, a second insulating layer 302 and a mask layer 304 are sequentially formed on the semiconductor substrate 200. According to some embodiments, the manufacturing technology of the first insulating layer 300 is silicon oxide, and the manufacturing technology of the second insulating layer 302 is silicon nitride. In these embodiments, the manufacturing technology of the first insulating layer 300 can be through a thermal oxidation process or a deposition process (e.g., a chemical vapor deposition (CVD) process), and the manufacturing technology of the second insulating layer 302 can be through a deposition process (e.g., a CVD process). In addition, in some embodiments, the mask layer 304 is a photoresist layer and can be coated on the semiconductor substrate 200. In another embodiment, the mask layer 304 is a hard mask layer, and its manufacturing technology can be through a deposition process (such as a CVD process).

Referring to FIG. 3 , FIG. 4B and FIG. 5B , step S13 is performed, and the mask layer 304 is patterned to form a stripe pattern 304a. The stripe pattern 304a may extend along a direction D1, and the direction D1 may be consistent with the direction in which each row of active areas AA shown in FIG. 2A extends. By partially removing the mask layer 304 to form the stripe pattern 304a, a portion of the second insulating layer 302 between the stripes 304a may now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method of forming the mask layer 304 into the stripe pattern 304a may include a lithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method of forming the mask layer 304 into the stripe pattern 304a may include a lithography process and an etching process.

Referring to FIG. 3 , FIG. 4C and FIG. 5C , step S15 is performed, and the stripe pattern 304a is further patterned to form an array of island patterns 304b. The island patterns 304b of each row can be arranged along a direction D1, and the island patterns 304b of each row can be arranged along a direction D2 intersecting the direction D1. The island patterns 304b will serve as a shadow mask when forming the initial trench TR' in a subsequent step. The island patterns 304b of each row are part of the same stripe pattern 304a and can be laterally separated from each other along the direction D1. By partially removing the stripe pattern 304a to form the island pattern 304b, the portion of the second insulating layer 302 between the island patterns 304b can now be exposed. In some embodiments, the mask layer 304 is a photoresist layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a lithography process. In another embodiment, the mask layer 304 is a hard mask layer, and the patterning method for forming the stripe pattern 304a into the island pattern 304b includes a lithography process and an etching process.

As described above, in some embodiments, two patterning steps are used to form the island pattern 304b. In another embodiment, a single patterning process can be used to pattern the mask layer 304 shown in Figures 4A and 5A into the island pattern 304b shown in Figures 4C and 5C.

3 , 4D and 5D , step S17 is performed and an initial trench TR' is formed in the semiconductor substrate 200. The initial trench TR' may penetrate a portion of the first and second insulating layers 300, 302, span between the island pattern 304b, and extend further into the semiconductor substrate 200. By forming the initial trench TR', surface portions of the semiconductor substrate 200 are separated from each other in the lateral direction and are referred to as initial active areas AA'. The top surfaces of the initial active areas AA' may be substantially coplanar with each other. According to some embodiments, an etching process is used to form the initial trench TR'. In the etching process, the island pattern 304b may serve as a shadow mask. In addition, after the etching process, the island pattern 304b may be removed and the second insulating layer 302 thereunder may be exposed.

3, 4E and 5E, step S19 is performed to remove the first and second insulating layers 300, 302. Therefore, the top surface of the initial active area AA' can be exposed. In some embodiments, the method of removing the first and second insulating layers 300, 302 includes an etching process.

Referring to FIG. 3 , FIG. 4F , and FIG. 5F , step S21 is performed to form an isolation structure 202 in the initial trench TR′. In some embodiments, the method for preparing the isolation structure 202 includes providing an insulating material on the structure shown in FIG. 4E and FIG. 5E . The insulating material can fill the initial trench TR′ and cover the top surface of the initial active area AA′. Subsequently, the portion of the insulating material that crosses the top surface of the active area AA can be removed by a planarization process, such as a polishing process and an etching process, or a combination thereof. In addition, a portion of the insulating material filled in the preliminary trench TR' may be recessed relative to the top surface of the initial active area AA', and the remaining insulating material may form the isolation structure 202. For example, the recessing method of the portion of the insulating material in the preliminary trench TR' may include an etching process.

3 , 4G and 5G , step S23 is performed to selectively form a mask layer 306 on some of the initial active areas AA'. Therefore, as shown in FIG5G , one of the adjacent initial active areas AA' is covered by the mask layer 306, while the other may remain exposed. According to some embodiments, the initial active areas AA' of each column are alternately covered along the column direction (e.g., direction D1). In these embodiments, the mask layer 306 is periodically arranged along the column direction (e.g., direction D1). For example, the preparation method of the mask layer 306 may include forming a material layer that spans the entire domain, and patterning the material layer by a lithography process and an etching process to form the mask layer 306. The mask layer 306 is made of a material having sufficient etching selectivity with respect to the semiconductor substrate 200.

3, 4H and 5H, step S25 is performed, and the uncovered initial active area AA' is recessed relative to the initial active area AA' covered by the mask layer 306. Therefore, the initial active area AA' is selectively recessed, and the active area AA as described with reference to FIG2B is formed. As shown in FIG5H, the active area AA1 is one of the recessed active areas AA, and the active area AA2 is one of the non-recessed active areas AA. In addition, in the recessing step, the initial trench TR' is formed to have a trench TR with a side wall higher than another side wall, as shown in FIG2B. In some embodiments, the selective recessing method of the initial active area AA' includes an etching process. In these embodiments, the mask layer 306 and the isolation structure 202 have sufficient etching selectivity with respect to the semiconductor substrate 200, so that the mask layer 306 and the isolation structure 202 may be almost not consumed in the etching process for the semiconductor substrate 200.

3, 4I and 5I, step S27 is performed to remove the mask layer 306. With the removal of the mask layer 306, the previously covered active area AA can now be exposed. For example, as shown in FIG5I, the active areas AA1 and AA2 can be exposed simultaneously in the current step. According to some embodiments, the preparation method of the mask layer 306 includes an etching process. Since the mask layer 306 has sufficient etching selectivity with respect to the isolation structure 202 and the semiconductor substrate 200, the isolation structure 202 and the active area AA can be almost not recessed during the etching process.

3, 4J and 5J, step S29 is performed to form SAMs 206 on the top surface of the active area AA. According to some embodiments, the SAMs 206 are selectively adsorbed on the top surface of the active area AA, while the top of the sidewall of the trench TR' may remain uncovered.

In some embodiments, the SAM-forming compound may be dissolved or dispersed in a solvent. The composition of the solvent is suitable for forming a SAM layer (including the SAM-forming compound). The solvent includes, but is not limited to, toluene, xylene, dichloromethane (DCM), chloroform, carbon tetrachloride, ethyl acetate, butyl acetate, amyl acetate, propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monomethyl ether (PGME), ethoxy ethyl propionate, anisole, ethyl lactate, diethyl ether, dioxane, tetrahydrofuran (THF), acetonitrile, acetic acid, amyl acetate, n-butyl acetate, γ-butyrolactone (GBL), acetone, methyl isobutyl ketone (methyl isobutyl ketone), and the like. ketone), 2-heptanone, cyclohexanone, methanol, ethanol, 2-ethoxyethanol, 2-butoxyethanol, isopropanol, n-butanol, DMF, N,N-dimethylacetamide, pyridine, and DMSO. These solvents can be used alone or in combination.

In some embodiments, the solution can be applied to the top surface of the substrate using any appropriate coating technique (e.g., dip coating, spin coating), and then the solvent is removed to form an initial SAM layer. The initial SAM layer has a top surface in contact with the atmosphere and a bottom surface in contact with a selected surface of the substrate (a surface to which the compound forming the SAM has a preferential affinity). Generally, the thickness of the SAM is about 0.5 to about 20 nanometers, particularly about 0.5 nanometers to about 10 nanometers, or even about 0.5 nanometers to 2 nanometers.

3, 4K and 5K, step S31 is performed to form a contact enhancement top cap 204. According to some embodiments, the manufacturing technology of the contact enhancement top cap 204 is through an epitaxial process. In the epitaxial process, the material of the contact enhancement top cap 204 can grow from the exposed portion of the active area AA, which is the top of the side wall of the active area AA, extending between the SAM 206 and the isolation structure 202. In some cases, the contact enhancement top cap 204 can further extend to the side wall of the SAM 206. By forming the contact enhancement top cap 204, the top of the active area AA is laterally surrounded, as described with reference to FIG. 2A, with an additional portion.

Referring to FIG. 3 and FIG. 2B , step S33 is performed to form a capacitor contact CC on the active area AA. Although not shown, several process steps may be performed before forming the capacitor contact CC. For example, before forming the capacitor contact CC, a dielectric layer (not shown) may be formed entirely on the active area AA and the isolation structure 202. In addition, a through hole may be formed in the dielectric layer by a lithography process and an etching process to define the location of the capacitor contact CC. Subsequently, a conductive material may be filled into the through hole by a deposition process, a plating process, or a combination thereof, and excess conductive material on the dielectric layer may be partially removed by a planarization process. The remaining portion of the conductive material in the via may form a capacitor contact CC.

At this point, the structure shown in FIG. 2B has been formed. Although not shown, additional process steps may be performed to form other elements of the memory array 10 (as described with reference to FIG. 1B and FIG. 2A ), including word lines WL, bit lines BL, and storage capacitors SC. These additional process steps may be performed during and after the process steps described with reference to FIG. 3 , FIG. 4A to FIG. 4K , FIG. 5A to FIG. 5K , and FIG. 2B .

FIG. 6 is a cross-sectional view illustrating edge portions of two adjacent active areas AA and a portion of an isolation structure 202 extending between the adjacent active areas AA according to some other embodiments of the present disclosure.

6, in some embodiments, the SAMs 206 described with reference to FIG. 2B are omitted. In these embodiments, the top of each active area AA is covered by a contact enhancement capping layer 604. The contact enhancement capping layer 604 is similar to the contact enhancement top cap 204 (as described with reference to FIG. 2B) in terms of material selection and function. In other words, the contact enhancement capping layer 604 is semi-conductive or conductive and can be used as an additional portion of the active area AA to improve the electrical contact between the active area AA and the capacitor contact CC standing on the active area AA. In some embodiments, the contact enhancement cap layer 604 includes a contact enhancement layer 604a located on the top surface of the active area AA, and includes a contact enhancement top cap 604b laterally surrounding the top of the active area AA. The contact enhancement top cap 604b can extend from the contact enhancement layer 604a along the side wall of the active area AA to the top surface of the isolation structure 202, and provide an additional landing area for the capacitor contact CC provided on the active area AA. In some embodiments, the capacitor contact CC penetrates the contact enhancement layer 604a to establish electrical contact with the active area AA.

As described above, some active areas AA (e.g., active area AA1) protrude less than other active areas AA (e.g., active area AA2) relative to the isolation structure 202. Therefore, the contact enhancement capping layer 604 (referred to as the contact enhancement capping layer 604-1) covering the less protruding active areas AA is lower than the contact enhancement capping layer 604 (referred to as the contact enhancement capping layer 604-2) covering the more protruding active areas AA. In other words, the contact enhancement layer 604a of the contact enhancement capping layer 604-1 may extend on a plane lower than the plane on which the contact enhancement layer 604a of the contact enhancement capping layer 604-2 extends. In addition, the contact enhancement top cap 604b of the contact enhancement cap layer 604-1 can have a height _H604-1 that is shorter than the height _H604-2 of the contact enhancement top cap 604b of the contact enhancement cap layer 604-2. The height _H604-1 is measured from the bottom end of the contact enhancement top cap 604b of the contact enhancement cap layer 604-1 (which can be flush with the top surface _TS202 of the isolation structure 202) to the top end of the contact enhancement top cap 604b. Similarly, height H _604-2 is measured from the bottom end of the contact enhancement top cap 604b of the contact enhancement cap 604-2 (which can be flush with the top surface TS ₂₀₂ of the isolation structure 202) to the top end of the contact enhancement top cap 604b. Since the contact enhancement cap 604-1 is lower than the contact enhancement cap 604-2, the top corners of the contact enhancement caps 604-1 and 604-2 can be more spaced apart in the vertical direction, so when the width of the trench TR between adjacent active areas AA is greatly reduced, the contact enhancement caps 604-1 and 604-2 can be prevented from merging. Therefore, interference between the memory cells 100 formed on the adjacent active areas AA can be avoided.

In the preparation of the structure shown in FIG6 , the step of forming the SAM 206 (as described with reference to FIG4J and FIG5J ) can be omitted. In addition, after the active area AA1 is recessed and the mask layer 306 is removed (as described with reference to FIG4H-4I and FIG5H-5I ), the contact enhancement capping layer 604 is formed on the active area AA by, for example, an epitaxial process. In addition, the capacitor contact CC can be formed on the active area AA.

As described above, the active regions of the memory cells in the memory array have additional portions (i.e., contact enhancement caps) at their top corners. By having more of these additional portions, the active region can provide a larger landing area for the capacitor contacts standing on the active region. Therefore, the electrical contact between the capacitor contacts and the active region can be less affected by process variations in setting the capacitor contacts. In other words, the electrical contact between the capacitor contacts and the active region can be improved. In addition, adjacent active regions are designed to have different heights, and the top surface of one active region can be recessed relative to the top surface of an adjacent active region. Therefore, the additional portions of adjacent active regions can be more spaced apart in the vertical direction. Therefore, it is possible to prevent adjacent active regions from merging together, thereby avoiding interference between memory cells formed on adjacent active regions.

In one embodiment of the present disclosure, a method for preparing a memory array is provided, comprising: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface area of the semiconductor substrate; filling an isolation structure in the trench, wherein the isolation structure is filled to a height lower than a top surface of one of the active regions; A first group of active areas of the active areas is recessed from a top surface, and a second group of active areas of the plurality of active areas is covered at the same time; and a plurality of contact-enhanced side wall spacers and a plurality of contact-enhanced top covers are integrally formed, wherein the contact-enhanced side wall spacers laterally surround the tops of the active areas, and the contact-enhanced top covers cover the upper surfaces of the active areas.

Although the present disclosure and its advantages have been described in detail, it should be understood that some changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the scope of the disclosed patent. For example, many of the above processes may be implemented in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present disclosure is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the disclosed patents of the present disclosure.

10: Memory array 100: Memory cell 200: Semiconductor substrate 202: Isolation structure 204: Contact enhancement cap 204-1: Contact enhancement cap 204-2: Contact enhancement cap 206: Self-assembled monolayer (SAM) 206-1: Self-assembled monolayer 206-2: Self-assembled monolayer 300: First insulating layer 302: Second insulating layer 304: Mask layer 304a: Stripe pattern 304b: Island pattern 306: Mask layer 604: contact enhancement cap 604-1: contact enhancement cap 604-2: contact enhancement cap 604a: contact enhancement layer 604b: contact enhancement top cap AA: active area AA': initial active area A-A': line AA1: active area AA2: active area AT: access transistor B-B': line BL: bit line CC: capacitor contact CC1: capacitor contact CC2: capacitor contact D1: direction D2: direction H1: height H2: height H202: height H204-1: height H204-2: height H604-1: height H604-2: height S11: step S13: step S15: step S17: step S19: step S21: step S23: step S25: step S27: step S29: step S31: step S33: step SC: storage capacitor SW1: side wall SW2: side wall TR: trench TR': initial trench TS1: top surface TS2: top surface TS202: top surface WL: word line

When referring to the embodiments and the disclosed patent scope together with the drawings, a more comprehensive understanding of the disclosure of the present disclosure can be obtained. The same component symbols in the drawings refer to the same components. FIG. 1A is a circuit diagram illustrating a memory cell in a memory array of some embodiments of the present disclosure. FIG. 1B is a structural diagram illustrating a memory array including a plurality of memory cells of some embodiments of the present disclosure. FIG. 2A is a plan view illustrating a local layout of a memory array of some embodiments of the present disclosure. FIG. 2B is a cross-sectional view illustrating the edge portion of two adjacent active areas of some embodiments of the present disclosure and a portion of an isolation structure extending between these adjacent active areas. FIG. 3 is a flow chart illustrating a method for preparing the structure shown in FIG. 2B of some embodiments of the present disclosure. FIG. 4A to FIG. 4K are plan views illustrating a structure at an intermediate stage of the preparation method shown in FIG. 3 of some embodiments of the present disclosure. FIG. 5A to FIG. 5K are cross-sectional views illustrating a structure at an intermediate stage of the preparation method shown in FIG. 3 of some embodiments of the present disclosure. FIG. 6 is a cross-sectional view illustrating an edge portion of two adjacent active regions and a portion of an isolation structure extending between these adjacent active regions of some other embodiments of the present disclosure.

200:Semiconductor substrate

202: Isolation structure

204:Contact enhanced top cover

204-1: Contact Enhanced Top Cover

204-2: Contact Enhanced Top Cover

206: Self-assembled monolayer (SAM)

206-1: Self-assembled single layer

206-2: Self-assembled single layer

AA: Active Area

AA1: Active area

AA2: Active area

CC: capacitor contact

CC1: capacitor contact

CC2: capacitor contact

H1: Height

H2: Height

H202: Height

H204-1: Height

H204-2: Height

SW1: Side wall

SW2: Side wall

TR: Groove

TS1: Top

TS2: Top

TS202: Top

Claims (8)

A method for preparing a memory array includes: forming a trench on a front surface of a semiconductor substrate, wherein the trench defines a plurality of laterally separated active regions formed by a surface area of the semiconductor substrate; filling the trench with an isolation structure, wherein the isolation structure is filled to a height lower than a top surface of one of the active regions; recessing a first group of active regions of the active regions from a top surface, and simultaneously recessing the plurality of active regions. A second set of active regions is covered with a top surface; a plurality of contact enhancement side wall spacers and a plurality of contact enhancement top caps are integrally formed, the contact enhancement side wall spacers laterally surround the tops of the active regions, and the contact enhancement top caps cover the upper surfaces of the active regions; and before forming the contact enhancement top caps, a plurality of self-assembly monolayers (SAMs) are formed on the top surfaces of the active regions. The method for preparing a memory array as described in claim 1, wherein the formation of the trench comprises: forming at least one insulating layer on the front surface of the semiconductor substrate; forming a plurality of mask patterns on the at least one insulating layer; performing an etching process on the at least one insulating layer and the semiconductor substrate using the mask patterns as a shadow mask to form the trench; and removing the mask patterns and the at least one insulating layer. A method for preparing a memory array as described in claim 2, wherein the at least one insulating layer includes a first insulating layer and a second insulating layer stacked on the first insulating layer. A method for preparing a memory array as described in claim 1, wherein the formation of the isolation structure includes: providing an insulating material in the trench; and recessing the insulating material, thereby recessing the insulating material relative to the top surface of the active region and forming the isolation structure. A method for preparing a memory array as described in claim 1, wherein the second set of active areas is covered by a plurality of mask layers, and the first set of active areas is recessed, and the mask layers are removed before forming a plurality of contact enhancement sidewall spacers. A method for preparing a memory array as described in claim 1, wherein the side walls of the top of the active regions remain uncovered by the SAMs before forming the contact enhancement caps. A method for preparing a memory array as described in claim 1, wherein the method for preparing the contact enhancement caps includes an epitaxial process. A method for preparing a memory array as described in claim 1, wherein the contact enhancement top caps and the contact enhancement side wall spacers cover the tops of the active regions.