TWI862731B - Electronic fuse cell array - Google Patents

Abstract

An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.

Description

Electronic fuse unit array

This description relates to an electronic fuse (eFuse) cell array structure.

In very large scale integrated circuits, fuses (such as eFuse) that can be programmed for one-time programmable (OTP) memory are often present. A semiconductor chip may include one or more eFuses as an eFuse cell array. An eFuse memory may store data having different logic levels depending on a program state of a fuse. eFuse memory may be used in a variety of devices. For example, when a defective memory cell is detected in a power management IC (PMIC) device, the semiconductor memory device may perform a repair operation by replacing the defective memory cell with a redundant memory cell. An eFuse is a non-volatile storage element, which includes: an anti-fuse, which is a programmable element that provides an initial high resistance and a selective low resistance or a short circuit when it is blown; or a fuse element, which is a programmable element that provides an initial low resistance and a selective high resistance or an open circuit when it is blown.

As a one-time programmable (OTP) memory, if a relatively large current of about 10mA to 30mA passes through the eFuse memory element, the eFuse can be programmed. If the eFuse is programmed or is an open circuit, the resistance through the eFuse is greater than tens of KΩ. In order to make the memory element eFuse an open circuit, a larger programming current may be required, and a metal oxide semiconductor (MOS) transistor with a large channel width may be required to program the OTP memory element, resulting in an increase in the chip area of the semiconductor non-volatile memory device. It is expected to reduce the size of the OTP memory to have a compact design of a non-volatile memory (NVM) semiconductor device.

This [Content of the Invention] is provided to introduce in a simplified form a selection of concepts that are further described below in the [Implementation Method]. This [Content of the Invention] is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to assist in determining the scope of the claimed subject matter.

In a general aspect, an eFuse cell array includes a first unit cell and a second unit cell, each of which includes a PN diode, a unit read transistor, and a fuse element. A first placement order of the PN diode, the unit read transistor, and the fuse element in the first unit cell is opposite to a second placement order of the PN diode, the unit read transistor, and the fuse element in the second unit cell.

Each of the first unit cell and the second unit cell may further include a write word line coupled to a cathode of the PN diode, a read word line coupled to a gate of the unit read transistor, and a bit line coupled to an anode of the fuse element.

In each of the first unit cell and the second unit cell, a source region of the unit read transistor, an anode of the PN diode, and a cathode of the fuse element may be coupled to each other via a common node.

A position of the PN diode in the first unit cell may be opposite to a position of the PN diode in the second unit cell.

A position of the fuse element in the first unit cell may be opposite to a position of the fuse element in the second unit cell.

The eFuse cell array may further include a shared read transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell. The unit read transistor and the shared read transistor may be NMOS transistors.

The eFuse cell array may further include a common programming transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell. The common programming transistor may be a PMOS transistor.

Each of the fuse elements in the first unit cell and the second unit cell may be further electrically coupled to the common read transistor.

The PN diode may include an N-type doped region in an N-type well region, a P-type doped region in the N-type well region, a trench isolation region surrounding the N-type doped region, and a P-type guard ring structure surrounding the trench isolation region.

The cell read transistor may include a source region and a drain region in a well region, a gate insulating layer disposed between the source region and the drain region, and a gate electrode. The source region may be electrically coupled to the P-type doped region of the PN diode.

The fuse element may include a polysilicon layer formed on an isolation region and a silicide layer formed on the polysilicon layer. A cathode of the fuse element may be electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor.

In another general aspect, an eFuse cell array includes a write word line configured for a write operation, a read word line configured for a read operation, a bit line disposed orthogonal to the write word line and the read word line, a PN diode coupled to the read word line, a cell read transistor coupled to the read word line, and a fuse element coupled to the bit line.

The write word line may be coupled to a cathode of the PN diode. The read word line may be coupled to a gate of the cell read transistor. The bit line may be coupled to an anode of the fuse element.

A source region of the cell read transistor, an anode of the PN diode, and a cathode of the fuse element can be coupled to each other via a common node.

The eFuse cell array may further include a shared read transistor coupled to the fuse element for a read operation. A read current may flow through the cell read transistor, the fuse element, and the shared read transistor.

The eFuse cell array may further include a common programming transistor coupled to the fuse element to provide a programming current to the fuse element. The programming current may flow through the common programming transistor, the fuse element, and the PN diode, such that the programming current has a current path opposite to the current path of the read current on the fuse.

The eFuse cell array may further include a sense amplifier configured to determine whether the fuse element is programmed.

The eFuse cell array may further include a read current supply configured to provide a read current. The read current supply may include a read current transistor and a read current resistor coupled to the read current transistor.

The eFuse cell array may further include a reference voltage supply configured to supply a reference voltage. The reference voltage supply may include a first reference transistor corresponding to the read current transistor and a first reference resistor corresponding to the read current resistor.

The reference voltage supply may further include a second reference transistor corresponding to the cell read transistor, a second reference resistor corresponding to the fuse, and a third reference transistor corresponding to the common read transistor.

The PN diode may include an N-type doped region in an N-type well region, a P-type doped region in the N-type well region, a trench isolation region surrounding the N-type well region, and a P-type guard ring structure surrounding the trench isolation region.

The cell read transistor may include a source region and a drain region in a well region, a gate insulating layer disposed between the source region and the drain region, and a gate electrode. The source region may be electrically coupled to the P-type doped region of the PN diode.

The fuse element may include a polysilicon layer formed on an isolation region and a silicide layer formed on the polysilicon layer. A cathode of the fuse element may be electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor.

The eFuse cell array may further include a word line driver configured to select one of the word lines in the cell array, a program driver configured to provide a programming current to the fuse, and a control logic configured to control the word line driver and the program driver.

In another general aspect, an eFuse cell array includes a memory element coupled to a bit line, a diode configured to couple the memory element to a write word line, a cell read transistor coupled to the memory element and a gate of the cell read transistor coupled to a read word line, a common read transistor configured to couple the memory element to a ground via the bit line, and a common program transistor coupled to the memory element via the bit line.

The eFuse cell array may further include a source region of the cell read transistor, an anode of the PN diode, and a cathode of the memory element coupled to a common node thereof.

The write word line may be coupled to a cathode of the PN diode, and the bit line is coupled to an anode of the fuse.

The memory element may be a one-time programmable (OTP) memory element, and may be one of a fuse or an anti-fuse.

In another general aspect, an eFuse cell array includes: a plurality of unit cells, each of which includes a memory element coupled to a bit line, a diode configured to couple the memory element to a write word line and a unit read transistor coupled to the memory element and a read word line; a common read transistor configured to couple the memory element to a ground through the bit line; and a common program transistor coupled to the memory element through the bit line. A first placement order of the memory element, the cell read transistor and the diode in the odd-numbered unit cells of the plurality of unit cells is opposite to a second placement order of the memory element, the cell read transistor and the diode in the even-numbered unit cells of the plurality of unit cells.

The write word line may be coupled to a cathode of the diode, the read word line may be coupled to a gate of the cell read transistor, and the bit line may be coupled to an anode of the memory element.

In each of the plurality of unit cells, a source region of the cell read transistor, an anode of the diode, and a cathode of the memory element may be coupled to each other via a common node.

Other features and aspects will be apparent from the following detailed description, drawings and scope of the invention application.

10: Semiconductor devices

20: Control Logic

30: Frame

40: Word line (WL) driver

50:Programmable driver

60: Cell array

65: First bit line BL

70: Sense amplifier

75: Second bit line/read bit line RBL

100:Unit Unit

100':Unit Unit

100a:Unit unit

100b:Unit unit

100c:Unit unit

100d:Unit unit

100i:Unit Unit

100n: nth unit unit

110: PN diode

110': Second PN diode

110a: first PN diode

110b: Second PN diode

110b': Second PN diode

110c: The third PN diode

110d: Fourth PN diode

110n: nth PN diode

110n': nth PN diode

111: P-type well area

112: N-type well area

112a: First NW

112b: Second NW

113: cathode

114: Yang pole

120: Cell read transistor

120a: First unit read transistor

120b: Second unit read transistor

120b': Second unit read transistor

120c: Read transistors

120d: Read transistors

120n: nth unit read transistor

120n': nth unit read transistor

121: P-type well area

122: Gate insulation film

123: Gate electrode

134: Spacer

125:n+ drain region

126:n+ source region

130: Electronic fuse (eFuse)

130': Second memory element

130a: first memory element/first fuse

130a': First fuse

130b: Second memory element/second fuse

130b': Second fuse

130c: memory element/third fuse

130d: memory element/fourth fuse

130n: nth fuse

130n': nth fuse

140: First shared read transistor

140': Second shared read transistor

142: Polysilicon material

144: Silicide layer

145: N+ drain region

150:p+protective ring

152: Silicide layer

155: Source

160: Trench isolation area

170: Trench type fuse isolation area

175:Metal wiring

200:Programmable current controller

205: Anti-gate

210: shared program transistor

210': shared program transistor

215: Source region

225: P+ drain region

230: Gate electrode

300: Read current supply

310: Reading current transistors

320: Reading current resistor

400: Reference voltage supply

410: first reference transistor

420: Second reference transistor

430: Third reference transistor

440: First reference resistor

450: Second reference resistor

A: Anode

BL: Program bit line

1BL: bit line

2BL: bit line

C: cathode

CN: Common nodes

D: Drain

DOUT: output pin

G: Gate

N1: First node

N2: Second node

N3: The third node

N4: The fourth node

N5: Fifth node/reading node

RWL: Read Word Line

1RWL: read word line

2RWL: Read word line

nRWL: Read word line

S: Source

VDD: Programming voltage

VSS: reference voltage

WWL: Write Word Line

1WWL: Write word line

2WWL: Write word line

nWWL: Write word line

FIG. 1A shows a block diagram of a semiconductor device having an eFuse cell array according to an embodiment.

FIG. 1B illustrates a chip layout of a semiconductor device having an eFuse cell array according to an example.

FIG. 1C shows a cell layout of an eFuse cell array according to an example.

FIG. 1D shows a cross-sectional view of one of two eFuse units according to an example.

FIG2 shows a block diagram of an eFuse cell array according to an example.

FIG3A shows a circuit diagram of an eFuse unit according to an example.

FIG. 3B shows a circuit diagram of an eFuse unit with a read/write current path according to an example.

FIG4 shows a circuit diagram of an eFuse cell array for a write operation according to an example.

FIG5 shows a circuit diagram of an eFuse cell array for a read operation according to an example.

FIG6 shows a cross-sectional view of a PN diode in an eFuse unit according to an example.

FIG. 7 shows a cross-sectional view of a cell read transistor in an eFuse cell according to an example.

FIG8 shows a cross-sectional view of an eFuse element in an eFuse unit according to an example.

FIG. 9 shows a cross-sectional view of an eFuse cell having a read/write current path according to an embodiment.

FIG. 10 shows a cross-sectional view of an eFuse cell array according to an example.

In the drawings and detailed descriptions, the same element symbols refer to the same elements. The drawings are not drawn to scale, and the relative size, proportion and depiction of the elements in the drawings may be exaggerated for illustration, description and convenience.

The following detailed description is provided to help the reader gain a comprehensive understanding of the methods, devices and/or systems described herein. However, various changes, modifications and equivalents of the methods, devices and/or systems described herein will become apparent after understanding the disclosure of this application. For example, the order of operations described herein is merely an example and is not limited to the order described herein but may be changed, as is apparent after understanding the disclosure of this application, except for operations that must occur in a specific order. In addition, descriptions of features known in the art may be omitted for clarity and brevity.

The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate the many possible ways to implement the methods, devices, and/or systems described above that will become apparent after understanding the disclosure of this application.

In the specification, when an element (such as a layer, region or substrate) is described as being "located on", "connected to" or "coupled to" another element, it may be directly "located on", "connected to" or "coupled to" another element, or one or more other elements may exist in between. In contrast, when an element is described as being "directly located on", "directly connected to" or "directly coupled to" another element, one or more other elements may not exist in between.

As used herein, the term "and/or" includes any one and any combination of any two or more of the associated listed items.

Although terms such as "first", "second", and "third" may be used herein to describe various components, assemblies, regions, layers, or sections, these components, components, regions, layers, or sections should not be limited by these terms. Rather, these terms are only used to distinguish one component, component, region, layer, or section from another component, component, region, layer, or section. Therefore, without departing from the teachings of the examples described herein, a first component, component, region, layer, or section referred to may also refer to a second component, component, region, layer, or section.

Spatially relative terms such as "above", "upper", "below", and "lower" may be used herein for ease of description to describe the relationship of one element to another element as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figure is flipped, an element described as being "above" or "upper" relative to another element would be "below" or "lower" relative to the other element. Thus, depending on the spatial orientation of the device, the term "above" encompasses both above and below orientations. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein should be interpreted accordingly.

The terms used herein are only used to describe various examples and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural forms as well. The terms "include", "comprise" and "have" specify the presence of the stated features, numbers, operations, components, elements and/or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and/or combinations thereof.

Features of the examples described herein may be combined in various ways, as will become apparent upon understanding the disclosure of this application. Furthermore, although the examples described herein have multiple configurations, other configurations are possible, as will become apparent upon understanding the disclosure of this application.

The present invention provides a semiconductor device having an eFuse cell array capable of reducing the occupied area of an eFuse cell.

The present invention discloses a semiconductor device by designing eFuse cells as staggered stacks, thereby improving design rule satisfaction and preventing the fuses of adjacent cells from being damaged due to leakage current generated in a programming mode.

The present invention is described in more detail below based on the examples shown in the drawings.

FIG. 1A shows a block diagram of a semiconductor device having an eFuse cell array according to an example.

As shown in the figure, the semiconductor device 10 may include a control logic 20, a word line WL driver 40, a programmable driver 50, a cell array 60, a sense amplifier 70 and the like. However, it is obvious that the present invention is not limited to such configurations, and other configurations may be substituted or added. In this article, it should be noted that the use of the term "may" relative to an example or embodiment (for example, regarding what an example or embodiment may include or implement) means that there is at least one example or embodiment that includes or implements such a feature and all examples and embodiments are not limited thereto.

The control logic 20 may be configured to supply an internal control signal suitable for a programming mode or a read mode based on a control signal. In addition, the control logic 20 may be configured to supply a respective control signal to the word line (WL) driver 40, the programming driver 50, and the sense amplifier 70. The word line driver 40 may include a word line selector and may be configured to activate a write word line (WWL) or a read word line (RWL). The program driver (PD driver) 50 may include a bit line selector and may be configured to supply a programming current controlled by the WSEL pin. eFuse The cell array 60 may include a plurality of unit cells or bit cells, which are also referred to as an eFuse cell array or a fuse cell array. The sense amplifier 70 may be configured to sense a current difference between a reference current and a sense current passing through the eFuse to generate an output as a digital data. The generated digital data is provided to an output pin DOUT. The sense amplifier is configured to detect whether the eFuse is blown.

In FIG. 1A , the RE pin can be configured to activate a read input by providing a read enable signal for a read operation. The PEB pin can also be configured to activate the program input by providing a program enable signal for a write operation. The ADD pin can be configured to provide an address select to the word line (WL) driver 40. The WSEL pin can be configured to provide a programming current in the program mode. The VDD and VSS pins can be configured to supply an external supply power and ground power, respectively.

The eFuse cell array 60 includes a plurality of unit cells including an OTP memory element. For example, an electronic fuse (eFuse) type element or an anti-fuse type element may be used for the OTP memory element. In one embodiment, the eFuse type element is an OTP memory element. The eFuse type element may be programmed by applying a high voltage or a high current to the eFuse element.

According to one example, the eFuse cell array 60 includes 128 columns*16 rows. That is, the eFuse cell array 60 may include 128 word lines and 16 bit lines. Therefore, a total of 2048 bit cells or unit cells are configured in the eFuse cell array 60. Each cell lattice has an eFuse, which may include an OTP element, a diode, and a read transistor, which is further described in detail in FIG. 1C and FIG. 1D.

In this example, one row includes a write word line WWL and a read word line RWL. Therefore, there are 128 WWLs and 128 RWLs. And WWLs and RWLs are arranged in a one-to-one staggered manner. In this example, a word line selector and a bit line selector are required to perform programming of the unit cell. One of the 128 word lines and one of the 16 bit lines are selected sequentially through row decoding and column decoding. Therefore, when selected sequentially, the unit cell structure is operated.

FIG. 1B illustrates a chip layout of a semiconductor device having an eFuse cell array according to an example.

As shown in FIG. 1B , the eFuse cell array 60 occupies an area relatively larger than the area of other devices. A WL driver 40 for selecting each cell of the eFuse cell array is placed on the right side of the eFuse cell array. In addition, for programming or blowing fuse elements, a PD driver 50 is placed directly below the eFuse cell array. A sense amplifier (BL S/A) 70 associated with a read operation is placed below the PD driver 50. And a control logic block 20 for controlling both the WL driver 40 and the PD driver 50 is located in the lower right corner. Therefore, a semiconductor memory device 10 having a relatively compact chip size is formed. When compared to a typical cell array size, the cell array size can be reduced, thereby reducing the overall chip size.

FIG. 1C shows a cell layout of an eFuse cell array according to an example.

As described above, for example, the eFuse cell array 60 includes a total of 2048 unit cells, and many of the unit cells are arranged in a frame 30. For example, FIG. 1C is an enlarged view of a frame 30 in which many unit cells are arranged. Unit cells 100a, 100b, 100c, 100d are arranged in parallel. Each unit cell includes at least three components or three devices: a PN diode, a switching transistor (read transistor) and a fuse.

For example, as shown in FIG. 1C , the first unit cell 100a includes a first PN diode 110a, a first unit read transistor 120a, and a first memory element 130a. In the same manner, the second unit cell 100b includes a second PN diode 110b, a second unit read transistor 120b, and a second memory element 130b. As for the third and fourth unit cells, they have PN diodes 110c and 110d, read transistors 120c, 120d, and memory elements 130c, 130d. Each of the memory elements 130a, 130b, 130c, 130d may be, for example, a fuse or an anti-fuse. According to one embodiment, the memory elements 130a, 130b, 130c, 130d are write-once devices, each unit cell of which is written at most once.

As shown in FIG. 1C , in one example, each of the cell read transistors 120a, 120b, 120c, and 120d in the unit cell is fixed at the center. However, the positions of the PN diodes 110a, 110b, 110c, and 110d are changed from left to right or from right to left, so that the positions of the PN diodes are staggered to form a sawtooth shape. The positions of the fuses 130a, 130b, 130c, and 130d are staggered in a manner similar to the PN diodes.

In one example, the order of the PN diode, the read operation diode, and the fuse element in the first unit cell 100a is opposite to the order of the PN diode, the read operation diode, and the fuse element in the second unit cell 100b in the same direction (e.g., X-axis). The second unit cell 100b has an order opposite to the first unit cell 100a. In this example, the first unit cell 100a has a first placement order: from left to right direction is the first PN diode 110a, the first unit read transistor 120a, and the first memory element 130a. However, the second unit cell 100b has a second placement order: from left to right, the second memory element 130b, the second unit read transistor 120b, and the second PN diode 110b. The placement order of the third unit cell 100c is the same as that of the first unit cell. The placement order of the fourth unit cell 100d is the same as that of the second unit cell 100b.

It is desirable that the first PN diode 110a and the second PN diode 110b are disposed diagonally to each other in adjacent unit cells. Therefore, the first PN diode 110a and the second PN diode 110b are disposed as far apart from each other as possible. In order to have a longest distance between the first PN diode and the second PN diode, it is desirable that the first PN diode 110a is located at a diagonal position relative to the second PN diode 110b.

If the first PN diode 110a and the second PN diode 110b are arranged to be as far apart from each other as possible, it may help to reduce the NW to NW leakage current. For example, the first PN diode 110a is formed in a first NW, and the second PN diode 110b is formed in a second NW. When the first NW and the second NW are close to each other, the leakage current can easily flow to each other. If the leakage current flows from the first PN diode to the second PN diode, the second fuse electrically coupled to the second PN diode may be damaged due to an unprogrammed second fuse that is inadvertently programmed by the leakage current. Therefore, the second fuse may fail. Therefore, it is desirable to minimize the leakage current between the two N-type wells. If the leakage current is reduced, the failure of the fuse element can be reduced.

The PN diodes in the remaining unit cells 100c and 100d may be configured in the same manner as the unit cells 100a and 100b. In one example, the third PN diode 110c and the fourth PN diode 110d of the unit cells adjacent to each other are configured to be separated from each other. In addition, the third fuse 130c and the fourth fuse 130d are also arranged to be separated to be diagonal to each other. That is, the fuses of the unit cells adjacent to each other may be configured to be separated from each other.

Therefore, as shown in the example of FIG. 1C , odd-numbered row unit cells 100a and 100c have the same configuration structure. Even-numbered row unit cells 100b and 100d have the same configuration structure. Correspondingly, odd-numbered rows (row 1, row 3, row 5, etc.) have the same structure as each other, and even-numbered rows (row 2, row 4, row 6, etc.) also have the same structure as each other.

The semiconductor memory device may include a plurality of unit cells to form a cell array, wherein each of the unit cells includes at least three components including: a PN diode, a cell read transistor; and a fuse element, and wherein the unit cells include at least a first unit cell and a second unit cell and the first unit cell and the second unit cell are alternately arranged to form a cell array, wherein the placement order of one of the three components in the first unit cell is opposite to the placement order of the three components in the second unit cell in the same direction.

FIG. 1D shows a cross-sectional view of one of two eFuse units according to an example.

FIG. 1D is a cross-sectional view taken along lines A-A' and BB' of the unit cells 100a and 100b in FIG. 1C. As shown in the figure, in the present invention, the first PN diode 110a and the second PN diode 110b are formed in the first NW 112a and the second NW 112b, respectively. The first NW 112a and the second NW 112b are placed farthest from each other. By configuring the two PN diodes to be spaced far apart from each other, the leakage current between NW to NW (dotted line) can be reduced.

Since each of the unit cells includes only three devices: a PN diode, a read transistor, and a memory element (fuse), the cell array has a relatively compact area. If the unit cell includes four devices, the total area of the cell array will be larger than the embodiment of the present invention.

In addition, as shown in FIG. 1D , the first type unit cell 100 is arranged in the order of the memory element 130, the unit read transistor 120, and the PN diode 110 from the left side of the figure. The second type unit cell 100b is arranged in the order of the PN diode 110, the unit read transistor 120, and the memory element 130.

In addition, a cathode (N-type doped region) 113 of the PN diode 110 is coupled to a control logic 20. An anode (P-type doped region) 114 of the PN diode 110 is coupled to an N-type highly doped source region 126 of the cell read transistor 120 and a cathode of the memory element 130 through a metal line 175. An N-type highly doped drain region 125 of the cell read transistor 120 is coupled to an input line of a sense amplifier 70 for a read operation (see, for example, FIG. 5 ). In addition, the N-type highly doped source region 126 is coupled to the PN diode 110 and the memory element 130. In addition, the cathode of the memory element 130 is coupled to the P+ anode 114 of the PN diode 110 and the N-type highly doped source region 126 of the cell read transistor 120 using a metal wire 175 through a common node CN. In addition, the three components in the unit cell 100a are surrounded by a P+ guard ring structure 150.

The second type unit cell 100b has a structure similar to that of the first type unit cell 100a. However, the arrangement order of the three components in the second type unit cell 100b is opposite to that of the first type unit cell 100a.

FIG2 shows a block diagram of an eFuse cell array according to an example.

As previously described, the eFuse cell array 60 may include a plurality of unit cells 100. Each unit cell 100 may include a PN diode 110, a unit read transistor (or a first read transistor) 120, and a memory element 130. The eFuse cell array 60 may further include a common read transistor (or a second read transistor) 140 and a common program transistor or a program operation transistor or a third switch transistor 210 coupled to the memory element 130.

Although the unit read transistor 120 is located in the unit cell 100, the shared read transistor 140 is located outside the unit cell 100, resulting in a reduction in the area occupied by the eFuse unit array 60. The shared read transistor 140 is coupled to each eFuse 130 in the unit cell in the same row. That is, the shared read transistor 140 is coupled to a plurality of unit cells 100 through the bit line BL. A plurality of read transistors and a shared read transistor 140 are coupled to the bit line BL.

Generally, the shared read transistor 140 may be included in a unit cell 100. However, according to the present invention, in order to reduce the size of the unit cell 100, it is designed to exclude the shared read transistor 140 from the unit cell 100. Therefore, the size of the unit cell 100 and the size of the eFuse cell array 60 including the unit cell can be reduced. It effectively reduces the size of the eFuse cell array 60 that occupies the largest area in the chip area.

In FIG. 2 , a P-type guard ring 150 is formed to surround the PN diode 110, the cell read transistor 120 and the memory element 130. In addition, the cell read transistor (or the first read transistor) 120 and the shared read transistor (or the second read transistor) 140 can be an n-type metal oxide semiconductor (NMOS) transistor or an NMOS metal oxide semiconductor field transistor (NMOSFET). The shared program transistor (or the third switch transistor) 210 can be a p-type metal oxide semiconductor (PMOS) transistor or a PMOS metal oxide semiconductor field transistor (PMOSFET).

As shown in FIG. 2 , the diode 110, the cell read transistor 120 and the memory element 130 included in the unit cell 100 are electrically coupled to each other through a common node CN via a metal wire 175. In addition, the common read transistor 140 and the common program transistor 210 are electrically coupled to the fuse element via a third node N3 of the bit line BL.

FIG3A shows a circuit diagram of an eFuse unit according to an example.

According to FIG. 3A , as described above, a unit cell 100 includes three devices, including a PN diode 110, a unit read transistor 120, and a memory element 130. In addition, it further includes a write word line WRL, a read word line RWL, and a program bit line BL.

A cathode C of the diode 110 of the unit cell 100 can be configured to receive the write word line WWL. A gate G of the read transistor 120 of the unit cell 100 can be configured to receive the read word line RWL.

Program PMOS transistor 210 can be used to program unit cell 100. Program PMOS transistor 210 can be shared by other unit cells in a programming operation. A source S of shared program transistor 210 is called a program node of eFuse array 60 and can be configured to receive program voltage VDD. A drain D of transistor 210 is coupled to node N3 of eFuse 130 of unit cell 100. A gate G of program transistor 210 can be configured to be self-reflective and NAND gate 205 receives a program signal.

The read NMOS transistor 140 can serve as a current path for the unit cell 100 to be read. In other words, the read transistor 140 can be shared by other unit cells for the read operation. The source S of the shared read transistor 140 can be configured to receive the reference voltage VSS or ground. The drain D of the shared read transistor 140 is coupled to the node N3 of the eFuse 130 of the unit cell 100. The gate G of the transistor 140 can be configured to receive a read enable signal.

The write word line WWL and a cathode C of the PN diode 110 are coupled together at a first node N1. The read word line RWL and a gate of the cell read transistor 120 are coupled together at a second node N2. The program bit line BL and an anode A of the fuse element are coupled together at a third node N3. In addition, the unit cell 100 further includes a common node CN. An anode A of the PN diode 110, a source terminal of the cell read transistor 120, and a cathode C of the memory element 130 are coupled together through a common node CN.

In this embodiment, the bit line is formed in a direction orthogonal to the write word line and the read word line. Therefore, the write word line WWL, the read word line RWL and the program bit line BL are coupled to the PN diode 110, the cell read transistor 120 and the memory element 130, respectively.

According to an embodiment, the eFuse cell array further includes a common read transistor 140 and a common program transistor 210 formed outside the unit cell 100 area. The common read transistor 140 is used for a read operation. A read enable signal is applied to the gate terminal of the common read transistor 140, which operates in an on/off state according to the read enable signal. In this example, the common read transistor 140 can be an NMOS transistor. A drain terminal of the common read transistor 140 is coupled to the anode of the memory element 130 through the program bit line BL. A source terminal of the common read transistor 140 can be configured to receive a reference voltage or ground.

The shared programming transistor 210 can be configured to provide a programming current in the programming mode and can be located in a programming current controller 200. A NAND gate 205 can be configured to turn on the shared programming transistor 210 in the programming mode. The shared programming transistor 210 can be in an off state in the read mode. The shared programming transistor 210 can be a PMOS transistor. In the case of a PMOS shared programming transistor 210, the gate-source voltage (V _GS ) is constant even if the fuse is blown, and a constant current flows in the programming mode. If the shared programming transistor 210 uses NMOS, the programming current changes in the programming mode because V _GS changes when the fuse element is blown.

The shared read transistor 140 and the shared program transistor 210 are coupled to opposite ends of the bit line 1BL. Here, the memory element 130, the shared read transistor 140 and the shared program transistor 210 in the unit cell 100 are all coupled to each other through the third node N3 of the bit line BL.

FIG. 3B shows a circuit diagram of an eFuse unit having a read/write current path according to an example.

Arrow line 1 shows the flow of a programming current when the unit cell 100 is programmed. When the unit cell 100 is programmed, a programming current flows. For example, when the unit cell 100 is programmed, the read word line RWL of the unit cell 100 is turned off to electrically disconnect the read transistor 120 from the eFuse 130. The write word line WWL is activated to turn on the diode 110. The activation signal turns on the common programming transistor 210. Therefore, the current flows from the source S of the programming transistor 210 through the drain D of the transistor 210, the eFuse 130, the anode A of the diode 110, and the cathode of the diode 110, as shown by arrow line 1. The current causes the fuse eFuse 130 to burn out or causes the unit cell 100 to be programmed. Alternatively, when the programming transistor 210 and the diode 110 are turned on, the programming voltage VDD at the source S of the programming transistor 210 is transferred to the drain D of the transistor 210 to program the eFuse 130.

The memory element 130 is programmed or blown by a programming current. Programming or blowing refers to the task of increasing the resistance of the fuse. In the present invention, silicided polysilicon is used as an electronic fuse (eFuse), and the resistance can be increased by migration in a silicide layer formed on the polysilicon layer. Here, the programming current flows from the anode to the cathode of the memory element (eFuse) 130. The silicided polysilicon structure is programmed using electromigration (EM) from the cathode to the anode of the silicide layer. The programming current then exits through a PN diode and a write word line WWL. Here, the write word line is previously selected.

In FIG. 3B , arrow line 2 shows the flow of the read current when the unit cell 100 is read. For example, when reading the unit cell 100, the write word line WWL of the unit cell 100 is turned off to electrically disconnect the PN diode 110 from the eFuse 130. The read word line RWL is activated to turn on the unit of the read transistor 120. The activation signal turns on the shared read transistor 140. In a read operation, the program transistor 210 is turned off, thereby electrically disconnecting from the eFuse 130. The read transistor 120 is turned on. A read current is forced to the drain D of the NMOS transistor 120. The current flows through transistor 120, eFuse 130 and node N3. Therefore, the current flows from the drain D of transistor 120, the source S of transistor 120, eFuse 130, the drain D of transistor 140 and the source S of transistor 140 or the ground, as shown by arrow line 2.

A read word line RWL for a read operation is preselected, and a current for a read operation is supplied to the drain terminal of the cell read transistor 120. The read current passes through the memory element 130. The read current varies depending on the resistance of the memory element 130. When the fuse element is blown and the resistance is high, the read current value is small. Later, it can be converted into a resistance or voltage to see whether the fuse element is programmed. And the current through the memory element 130 flows through the bit line BL to the common read transistor 140. Here, the read current flows from the cathode to the anode direction of the memory element 130, and it can be seen that the read current flows in the opposite direction of the programming current. In addition, because the read current does not pass through the PN diode 110, a read operation may not require a high drive voltage. Therefore, a low drive current can be used as a read current. The read current can check whether the memory element 130 has been programmed. If the resistance in the current path is high, it is assumed that the selected fuse has been programmed. If it is not high, it is assumed that the selected fuse has not been programmed.

FIG4 shows a circuit diagram of an eFuse cell array for a write operation according to an example.

As shown in the figure, the programmable cell array 60 includes a plurality of cell units 100a, 100b, 100n, write word lines 1WWL, 2WWL, nWWL and read word lines 1RWL, 2RWL, nRWL and bit lines 1BL, 2BL. In this example, there are 128 read/write word lines and 16 bit lines.

For example, in the selected row, the first PN diode 110a is coupled to the first write word line 1WWL, and the second PN diode 110b is coupled to the second write word line 2WWL. In the same manner, the nth PN diode 110n in the nth unit cell 100n is coupled to the nth write word line nWWL.

In the selected row, the first unit read transistor 120a is coupled to the first read word line 1RWL, and the second unit read transistor 120b is coupled to the second read word line 2RWL. In the same manner, the nth unit read transistor 120n is coupled to the nth read word line nRWL.

In the selected row, the first, second and nth fuses 130a, 130b and 130n are all coupled to only one first bit line 1BL. That is, each of the fuses 130a, 130b, 130n includes a cathode terminal and an anode terminal, and the anode terminals of the first, second and nth fuses 130a, 130b and 130n are commonly coupled to the same first bit line 1BL.

The PN diodes, read transistors, and fuses in the unselected rows are electrically coupled in the same manner as in the selected rows.

For example, in an unselected row, the first PN diode 110a' is coupled to the first write word line 1WWL. The second PN diode 110b' is coupled to the second write word line 2WWL. Therefore, the nth PN diode 110n' in the nth unit cell 100n is coupled to the nth write word line nWWL.

In addition, in the unselected row, the first unit read transistor 120a' is coupled to the first read word line 1RWL, the second unit read transistor 120b' is coupled to the second read word line 2RWL, and the nth unit read transistor 120n' is coupled to the nth read word line nRWL.

Also in the unselected row, the first, second and nth fuses 130a', 130b' and 130n' are coupled only to a second bit line 2BL. That is, fuses 130a', 130b' and 130n' include a cathode terminal and an anode terminal. All anode terminals of the first memory element 130a', the anode terminal of the second memory element 130b' and the anode terminal of the nth memory element 130n' are coupled together to the same second bit line 2BL.

One of the word lines is selectively activated by the word line selector in the WL driver 40. In addition, one of the bit lines is selectively activated by the bit line selector in the PD driver 50.

As shown in FIG. 4 , a first common read transistor 140 coupled to the first bit line 1BL is included in the selected row. In addition, similarly, the unselected row includes a second common read transistor 140' coupled to the second bit line 2BL.

Each of the shared read transistors 140 and 140' includes a second source terminal, a second drain terminal and a second gate terminal. The second drain terminal of the first shared read transistor 140 is coupled to the first bit line 1BL and its second source terminal is grounded. The second shared read transistor 140' has a structure similar to that of the first shared read transistor 140. In the shared read transistors 140 and 140', a read enable signal is applied to the second gate terminal to control a read operation of the unit cell 100. The read operation is performed by the read enable signal for sensing a read current.

In addition, the eFuse cell array 60 further includes a programming current controller 200 having shared programming transistors 210 and 210'. The programming current controller 200 controls the programming current for programming fuses. A programming PMOS transistor can be used as the shared programming transistor 210. The shared programming transistor 210 includes a third source terminal, a third drain terminal, and a third gate terminal. The third drain terminal of the shared programming transistor 210 is coupled to the first bit line 1BL. The programming PMOS transistor 210 is shared by the unit cells 100, 100b, and 100n in a programming operation. The source region 215 of the common program transistor 210 is referred to as a program node of the eFuse array 60 and can be configured to receive a program voltage VDD (see FIG. 10 ).

As shown in FIG. 4 , each unit cell 100 is electrically insulated from other adjacent unit cells by a trench isolation region or another field oxide. Therefore, leakage current generated between unit cells can be reduced.

In one example, the memory element 130 may be a silicided polysilicon (Poly-Si) layer. The silicide layer is formed on the polysilicon layer. The silicide layer may be one of cobalt silicide (CoSi2), nickel silicide (NiSi), tungsten silicide (WSi) or titanium silicide (TiSi2), but is not limited thereto.

The resistance of the fuse element may change before or after a write or programming operation. For example, before a write or programming operation, the resistance of the fuse element may have a resistance value of about 300Ω or less. After a write or programming operation, the eFuse may have a resistance value of about 3kΩ or greater.

In an embodiment of the present invention, a program operation of a semiconductor device having a complete array of eFuse cells is described.

In this example, the first unit cell 100 is selected for programming operation by a selection signal provided by the self-control logic 20. Then, the unit read transistor 120 and the common read transistor 140 are turned off, and the common programming transistor 210 is turned on. According to a turn-on operation, a programming voltage of about 3V to about 8V is applied to a source terminal of the common programming transistor 210, and a programming current flows through the first bit line 1BL. A WWL can be selected from 128 WWLs by the WL driver. The PN diode 110 and the first bit line 1BL are turned on, so that a programming current flows to the fuse element, and then the fuse element is finally blown (programmed). The programming current flows sequentially through the shared programming transistor 210, the first bit line 1BL, the first memory element 130, and the first PN diode 110. The programmed fuse may have a high resistance of about 3,000Ω or more.

If the unit cell 100' is not selected during the programming operation, the second PN diode 110' is used to protect the second memory element 130'. The second PN diode 110' blocks the current flowing to the second memory element 130' in the second unit cell 100' because the second unit cell 100' is not selected. Therefore, the second memory element 130' in the second unit cell 100' can be protected from the programming operation performed in the first unit cell 100.

FIG5 shows a circuit diagram of an eFuse cell array for a read operation according to an example.

In FIG. 5 , the PN diode 110 is omitted because the PN diode 110 is not used during the read operation. For example, when reading the unit cell 100, the read word line RWL is activated to turn on the unit read transistor 120. The signal is activated to turn on the common read transistor 140. The sense amplifier 70 is turned on. Therefore, the current flows from the sense amplifier 70 through the second bit line RBL 75, the drain D of the transistor 120, the source S of the transistor 120, the eFuse 130, the drain D of the transistor 140, through the first bit line BL 65 and the source S of the transistor 140 or ground.

The sense amplifier 70 may be able to compare a reference resistor to the eFuse resistance when determining the state of the eFuse. The amount of current passing through the memory element (eFuse) 130 or the amount of voltage across the eFuse may be measured through a read operation. From the measured current or voltage, the eFuse resistance may be obtained and compared to the reference resistance in the sense amplifier 70. For example, if the eFuse resistance is less than the reference resistance, it is determined that the selected memory element 130 has not been programmed. Conversely, if the eFuse resistance is greater than the reference resistance, it is determined that the fuse element has been programmed. The reference voltage supply 400 provides an equivalent circuit for a read operation in the eFuse cell array 60.

During a read operation in a semiconductor memory device, one of the 128 RWLs is selected by the word line driver 40. The eFuse information of 16 cells in the selected RWL is output. To further describe the read operation in detail, the control logic 20 selects the first unit cell 100 to perform the read operation and provides a selection signal to the first unit cell 100. Then, the cell read transistor 120 and the read current transistor 310 in the read current supply 300 are turned on. All the switch transistors 410, 420 and 430 provided in the reference voltage supply 400 are also turned on.

In FIG. 5 , a read current supply 300 is used to provide a read current to a unit cell 100 selected for a read operation. That is, during a read operation of the semiconductor device 10 , a read current is provided to the selected unit cell 100 . This read current supply 300 includes a read current transistor 310 and a read current resistor 320 , wherein the read current resistor is formed of a non-silicide polysilicon film on an insulating layer. Materials other than non-silicide polysilicon films may be used. To supply the read current, in a non-limiting example, a read voltage according to this configuration may be in the range of about 1 to about 6V.

When the read current transistor 310 is turned on, the read current flows through the read current transistor 310, the read current resistor 320, the cell read transistor 120 and the memory element 130, and then flows through the common read transistor 140. The cell read transistor 120 and the read current resistor 320 are electrically coupled to each other by a metal wire 75 or a conductor. The metal wire may belong to the second bit line 75 used for the read operation. Therefore, the second bit line 75 is also referred to as the read bit line RBL. In this example, the read bit line RBL 75 is only used for the read operation and not the program operation, however, the first bit line 65 (BL) is used for both the program operation and the read operation. Therefore, the first bit line 65 is called a program bit line (PRL) or a read bit line (RBL). The read current is supplied to the drain terminal of the cell read transistor 120. In addition, the selected cell read transistor 120 is turned on and the read current is transferred to the memory element 130 as it is. Since the fuse element 140 is coupled to the drain terminal D of the common read transistor 140 through the bit line BL, the read current is discharged to ground at the source terminal S of the common read transistor 140. Here, the voltage across the eFuse element 140 can be measured during the read operation, which depends on the resistance of the eFuse element 140. The sense amplifier 70 compares the measured voltage across the fuse element 140 with a reference voltage to determine whether the fuse element 140 is programmed (or blown). Here, the read current resistor 320 and the drain terminal of the cell read transistor 120 are coupled together at the fourth node N4. The drain terminal D of the cell read transistor 120 and the sense amplifier 70 are coupled together at the fifth node or read node N5. One of the drains D of the cell read transistor 120 is coupled and forms a read node N5 for the eFuse cell array 60. The read node N5 is coupled to the sense amplifier 70 via the read bit line 75.

In addition, the same read current is also supplied to a reference voltage supply 400, which is configured to supply a reference voltage to the sense amplifier 70. The reference voltage supply 400 includes a first reference transistor 410, a first reference resistor 440, a second reference transistor 420, a second reference resistor 450, and a third reference transistor 430. The reference voltage supply 400 provides an equivalent circuit to a current path for a read operation in the eFuse cell array 60.

The following [Table 1] suggests reference transistors and reference resistors in a reference voltage supply 400 for a transistor or resistor for a read operation.

Table 1 shows that the first to third reference transistors 410, 420 and 430 represent the read current transistor 310, the unit read transistor 120 and the shared read transistor 140, respectively. The first reference resistor 440 represents the read current resistor 320, and the second reference resistor 450 represents the memory element (eFuse) 130.

The first reference transistor 410 and the corresponding read current transistor 310 may be PMOS devices (such as) to minimize the mismatch characteristics that originally occur during the read operation. The second and third reference transistors 420 and 430 and the corresponding shared read transistors 120 and 140 may be NMOS transistors to minimize the mismatch characteristics that originally occur during the read operation. Since these methods are used in the example, the mismatch characteristics during the read operation can be minimized.

According to the example of FIG. 5 , the read current transistor 310 may be a P-channel MOS transistor. The read current resistor 320 may have a predetermined first resistance value. In addition, one end of the read current resistor 320 may be coupled to a fourth drain terminal of the read current transistor 310. The other end of the read current resistor 320 is typically coupled to each of the drain terminals of the cell read transistor 120 in the eFuse cell structure 100 through the bit line 220A. The other end of the read current resistor 320 may also be coupled to the bit line sense amplifier 70. In a non-limiting example, the first resistance value of the read current resistor 320 may have an intermediate value of about 1600Ω between the unprogrammed resistance value (i.e., 300Ω or less) and the minimum resistance value (i.e., 3000Ω when programmed).

According to the example of FIG. 5 , the reference voltage supplier 400 can provide a reference voltage to the bit line sense amplifier 70. The reference voltage supplier 400 can include three switching transistors 410, 420, and 430 and two reference resistors 440 and 450 formed using a non-silicided polysilicon layer. The reference voltage supplier 400 can divide the read voltage using a plurality of resistors coupled in series, and can generate the divided voltage as a reference voltage. The three switching transistors 410, 420, and 430 can be coupled in series. The second reference resistor 440 may be coupled between the first reference transistor 410 and the second reference transistor 420, and the second reference resistor 450 may be coupled between the second reference transistor 420 and the third reference transistor 430.

According to the example of FIG. 5 , the first reference transistor 410 may be a PMOS device. With respect to the first reference transistor 410, its source terminal may receive a read voltage, its gate terminal may receive a reverse read control signal, and its drain terminal may be coupled to one end of the first reference resistor 440 to selectively provide a read voltage to the first reference resistor 440. The second reference transistor 420 may selectively couple the first reference resistor 440 and the second reference resistor 450. That is, the second reference transistor 420 may be an NMOS having a drain terminal commonly coupled to the first reference resistor 440 and the sense amplifier 70, a gate terminal to which the read control signal is input, and a source terminal coupled to the second reference resistor 450. The third reference transistor 430 may be an NMOS having a drain terminal coupled to the second reference resistor 450, a gate terminal receiving a read control signal, and a source terminal grounded so that current flows through the first reference resistor 440 and the second reference resistor 450 due to the read voltage.

According to the example of FIG. 5 , the two resistors provided in the reference voltage supply 400 (i.e., the first reference resistor 440 and the second reference resistor 450) may each have a predetermined resistance value. The predetermined resistance value may be between a resistance value in an unprogrammed state and a resistance value in a programmed state. In a non-limiting example, each resistance value may have a middle value of 1500Ω to 5000Ω between a resistance value of about 50Ω to about 200Ω in an unprogrammed state of the eFuse 140 and a minimum resistance value of about 3000Ω to about 10000Ω in a programmed state.

Next, a cross-sectional view of each device is described.

FIG6 shows a cross-sectional view of a PN diode in an eFuse unit according to an example.

As shown in the figure, a P-type well region 111 is formed on a semiconductor substrate, and an N-type well region 112 is formed in the P-type well region 111. An N+ cathode 113 and a P+ anode 114 are formed to be spaced apart from each other in the N-type well region 112, and each has a predetermined depth. A trench isolation region 160 is formed to surround the N+ cathode 113 and the P+ anode 114 formed in the N-type well region 112. In addition, a P-type protection ring 150 having a silicide layer 152 is formed in the P-type well region 111 to surround the PN diode structure 110 and is disposed adjacent to the trench isolation region 160. In addition, a silicide layer 152 is formed on the N+ cathode 113 and the P+ anode 124 in the PN diode. A contact plug and a metal portion may be formed on each silicide layer 152.

FIG. 7 shows a cross-sectional view of a cell read transistor in an eFuse cell according to an example.

A P-type well region 121 is formed in the semiconductor substrate. In addition, a gate insulating film 122 and a gate electrode 123 are formed on the P-type well region 121. A spacer 124 is formed on a side wall of the gate electrode 123. An n+ drain region 125 and an n+ source region 126 are formed on the two gate electrodes 123 in the P-type well region 121. A silicide layer 152 is formed on the gate electrode 123, the n+ drain region 125, and the n+ source region 126. In addition, a p+ guard ring 150 is also formed in the P-type well region 121, and a trench isolation region 160 is formed to surround the cell read transistor 120.

FIG8 shows a cross-sectional view of an eFuse element in an eFuse unit according to an example.

The memory element 130 may be a polysilicon fuse, which includes a silicide layer 144 formed on a polysilicon material 142. The silicide layer 144 may use one of cobalt silicide, nickel silicide, and titanium silicide, but is not limited thereto. A contact plug for an anode and a contact plug for a cathode may be formed in the memory element 130, and a metal portion is formed thereon. The memory element 130 has an anode and a cathode. The anode and the cathode are formed to be insulated from the semiconductor substrate by an insulating film. A trench type fuse isolation region 170 having a predetermined depth is formed in the P-type well region 121 located in a lower portion of the memory element 130. The lateral length of the trench type fuse isolation region 170 is longer than the lateral length of the memory element 130. In addition, a protection ring 150 having a silicide layer 152 is also formed adjacent to the trench isolation region 160.

FIG9 shows a cross-sectional view of an eFuse cell having a read/write current path according to an embodiment.

Although FIG. 9 shows each device arranged in a vertical direction for ease of description, as shown in FIG. 1D , they are arranged on a semiconductor substrate.

As shown in FIG9 , the PN diode 110, the cell read transistor 120, and the memory element 130 are coupled to each other. The N+ cathode 113 of the PN diode 110 is coupled to the control logic 20, and the P+ anode 114 is coupled to the n+ source region 126 of the cell read transistor 120 and the cathode of the memory element 130. The n+ drain region 125 of the cell read transistor 120 is coupled to the input line of the sense amplifier 70. In addition, the n+ source region 126 of the cell read transistor 120 is coupled to the PN diode 110 and the memory element 130. In addition, a metal wiring 175 is used in the common node CN to couple the cathode of the memory element 130 to the P+ anode 114 of the PN diode 110 and the n+ source region 126 of the cell read transistor 120.

In this configuration, the cell read transistor 120 and the shared read transistor 140 are turned off during the programming operation. To program the memory element 130, a programming current flows to the memory element 130. Arrow line 1 shows the programming current path, which indicates that the current flows from the memory element 130 to the PN diode 110. Therefore, the resistance value of the memory element 130 increases.

On the other hand, during a read operation, the cell read transistor 120 and the shared read transistor 140 are turned on. Then, a read current is output from the cell read transistor 120 and flows through the memory element 130 and transferred to the shared read transistor 140 coupled to the bit line. Arrow line 2 indicates the read current path.

As described above, the program operation of the semiconductor device 10 of the present invention passes through the PN diode 120, while the read operation does not pass through the PN diode 120, thereby providing different currents. There is an added advantage of being able to operate at a low voltage because the current directions in the read and write operations are opposite to each other and it is not expected to pass through the PN diode in the read operation.

FIG. 10 shows a cross-sectional view of an eFuse cell array according to an example.

As shown in the figure, a plurality of unit cells 100 are arranged in a row direction, and in an example, a total of 128 unit cells are provided. Each unit cell 100a, 100b, 100i and 100n has a memory element 130, a unit read transistor 120 and a PN diode 110. When arranged in a row direction, the unit cells 100a, 100b, 100i and 100n are arranged alternately with each other. That is, from the left side of the figure, the first unit cell 100a having a first type structure has a PN diode 110, a unit read transistor 120 and a memory element 130 in sequence in a first direction. The second unit cell 100b has a configuration of three components opposite to the first unit cell 100a in a second direction opposite to the first direction, as previously described in FIG. 1C. The second unit cell 100b as a second type structure has a memory element 130, a cell read transistor 120, and a PN diode 110 in sequence.

Therefore, as shown in FIG. 10 , for example, the unit cell 100a disposed in the first row and the 127th unit cell 100i disposed in the 127th row have the same structure. The configuration sequence of the three devices disposed in the unit cell 100a of the first row and the unit cell 100i disposed in the 127th row is the same. Similarly, the unit cell 100b disposed in the second row and the last unit cell 100n disposed in the 128th row have the same structure. The configuration sequence of the three devices disposed in the unit cell 100b of the second row is the same as the configuration sequence of the last unit cell 100n disposed in the 128th row. In other words, the configuration sequence is structured symmetrically. Therefore, odd-numbered rows (row 1, row 3, ..., row 127, etc.) have the same structure as each other, and even-numbered rows (row 2, row 4, ..., row 128, etc.) have the same structure as each other. In this example, the unit cell set arranged in the odd-numbered rows (row 1, row 3, ..., row 127, etc.) can be referred to as a first type of unit cell set, and the unit cell set arranged in the even-numbered rows (row 2, row 4, ..., row 128, etc.) can be referred to as a second type of unit cell set.

As shown in FIG. 10 , the PN diode 110 and the memory element 130 are disposed on the left and right sides, respectively, with respect to the cell read transistor 120 in the first type unit cell 100a. However, the positions of the PN diode 110 and the memory element 130 in the second type unit cell 100b are opposite to those in the first type unit cell 100a. This is because it is easy to ensure a space between two N-type well regions in which two PN diodes are formed, as previously mentioned in FIG. 1C , to reduce leakage current between the two N-type well regions.

In detail, the N+ cathode 113 of the PN diode 110 is coupled to the control logic 20, and the P+ anode 114 of the PN diode 110 is coupled to the n+ source region 126 of the cell read transistor 120. The n+ drain region 125 of the cell read transistor 120 is coupled to the input line of the sense amplifier 70. The n+ source region 126 of the cell read transistor 120 is coupled to the PN diode 110 and the memory element 130. The cathode constituting the memory element 130 is coupled to the P+ anode 114 of the PN diode 110 and the n+ source region 126 of the cell read transistor 120.

In FIG. 10 , the shared read transistor 140 is coupled to the anode of the memory element 130 via the bit line BL, and the shared program transistor 210 of the programmable current controller 200 is also coupled to the anode of the memory element 130 via the bit line BL. A source 155 of the shared read transistor 140 can be configured to receive a reference voltage VSS or ground. An NMOS device can be used for the shared read transistor 140.

A PMOS device can be used as the shared program transistor 210. The source region 215 of the shared program transistor 210 is referred to as the program node of the eFuse array 60 and can be configured to receive the program voltage VDD. A gate electrode 230 of the shared program transistor 210 can be configured to be self-reflective and the gate 205 receives a program signal. In addition, a P+ drain region 225 of the shared program transistor 210 is coupled to an N+ drain region 145 of the shared read transistor 140 via the bit line BL.

According to the present example, the unit cell 100 is formed by sequentially coupling a PN diode 110, a unit read transistor 120, and a memory element 130. The unit cell 100 may have two switching transistors 120 and 140 for a read operation, but in the present example, a single switching transistor (read transistor) 120 is formed in the unit cell 100. Another switching transistor (common read transistor) 140 is provided outside the unit cell to have a compact size of the unit cell 100.

Therefore, the present invention can provide a design for making the semiconductor device 10 have a smaller area. That is, a typical unit cell includes two switching transistors, a PN diode and a fuse element, and has a unit area of about ^60μm2 to about ^200μm2 . On the other hand, the unit area of a unit cell in the present invention includes a switching transistor, a PN diode and a fuse element that can be designed to be about ^20μm2 to about ^50μm2 . Therefore, the area of the semiconductor device 10 can be designed to be smaller.

According to a semiconductor device having an eFuse cell array of the present invention as described above, a unit cell is formed by sequentially coupling a PN diode, a unit read transistor, and a fuse. When located outside the unit cell, the common read transistor involved in the read operation of the fuse element is coupled through the bit line. Therefore, when a typical unit cell is compared with, the cell area can be reduced, thereby meeting a more stringent semiconductor device design rule.

According to the present invention, when stacking unit cells to form a cell array, each unit cell is stacked by being positioned in directions opposite to each other. Since each fuse of the unit cell is positioned to be separated from each other according to the stacking direction, it is possible to prevent the fuse of the adjacent cell from being damaged by the leakage current in the programming mode, thereby improving the reliability of the semiconductor memory device.

Although the present invention includes specific examples, it will be understood after understanding the disclosure of this application that various changes in form and details can be made in these examples without departing from the spirit and scope of the scope of the application and its equivalents. The examples described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each example should be considered to be applicable to similar features or aspects in other examples. Appropriate results can be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the present invention is not defined by the detailed description but by the scope of the patent application and its equivalents, and all changes within the scope of the patent application and its equivalents should be deemed to be included in the present invention.

60: Cell array

100:Unit Unit

110: PN diode

120: Cell read transistor

130: Electronic fuse (eFuse)

140: Shared read transistor

200:Programmable current controller

205: Anti-gate

210: shared program transistor

A: Anode

BL: Program bit line

C: cathode

CN: Common nodes

D: Drain

G: Gate

N1: First node

N2: Second node

N3: The third node

N5: Fifth node/reading node

RWL: Read Word Line

S: Source

WWL: Write Word Line

Claims (31)

An eFuse cell array includes: a first unit cell and a second unit cell, each of which includes: a PN diode; a unit read transistor; and a fuse element, wherein a first placement order of the PN diode, the unit read transistor, and the fuse element in the first unit cell is opposite to a second placement order of the PN diode, the unit read transistor, and the fuse element in the second unit cell. The eFuse cell array of claim 1, wherein each of the first unit cell and the second unit cell further comprises: a write word line coupled to a cathode of the PN diode; a read word line coupled to a gate of the cell read transistor; and a bit line coupled to an anode of the fuse element. An eFuse cell array as claimed in claim 1, wherein in each of the first unit cell and the second unit cell, a source region of the cell read transistor, an anode of the PN diode and a cathode of the fuse element are coupled to each other via a common node. As in the eFuse cell array of claim 1, a position of the PN diode in the first unit cell may be opposite to a position of the PN diode in the second unit cell. As in the eFuse cell array of claim 1, a position of the fuse element in the first unit cell may be opposite to a position of the fuse element in the second unit cell. The eFuse cell array of claim 1 further comprises: a common read transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell, wherein the unit read transistor and the common read transistor are NMOS transistors. The eFuse cell array of claim 6 further comprises: a shared programming transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell, wherein the shared programming transistor is a PMOS transistor. An eFuse cell array as claimed in claim 7, wherein each of the fuse elements in the first unit cell and the second unit cell is further electrically coupled to the common read transistor. The eFuse cell array of claim 1, wherein the PN diode includes: an N-type doped region in an N-type well region; a P-type doped region in the N-type well region; a trench isolation region surrounding the N-type well region; and a P-type guard ring structure surrounding the trench isolation region. An eFuse cell array as claimed in claim 9, wherein the cell read transistor comprises: a source region and a drain region in a well region; a gate insulating layer and a gate electrode disposed between the source region and the drain region, wherein the source region is electrically coupled to the P-type doped region of the PN diode. The eFuse cell array of claim 10, wherein the fuse element comprises: a polysilicon layer formed on an isolation region; and a silicide layer formed on the polysilicon layer, wherein a cathode of the fuse element is electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor. An eFuse cell array includes: a write word line configured for a write operation; a read word line configured for a read operation; a bit line disposed orthogonally to the write word line and the read word line; a PN diode coupled to the write word line; a cell read transistor coupled to the read word line; and a fuse element coupled to the bit line, wherein the write word line is coupled only to a cathode of the PN diode. An eFuse cell array as claimed in claim 12, wherein the read word line is coupled to a gate of the cell read transistor, and the bit line is coupled to an anode of the fuse element. An eFuse cell array as claimed in claim 12, wherein a source region of the cell read transistor, an anode of the PN diode and a cathode of the fuse element are coupled to each other via a common node. The eFuse cell array of claim 12 further comprises: a common read transistor coupled to the fuse element for a read operation, wherein a read current flows through the cell read transistor, the fuse element and the common read transistor. The eFuse cell array of claim 15 further comprises: a common programming transistor coupled to the fuse element to provide a programming current to the fuse element, wherein the programming current flows through the common programming transistor, the fuse element and the PN diode, so that the programming current has a current path opposite to the current path of the read current on the fuse element. The eFuse cell array of claim 12 further comprises: a sense amplifier configured to determine whether the fuse element is programmed. The eFuse cell array of claim 15 further comprises: a read current supplier configured to provide a read current, wherein the read current supplier comprises: a read current transistor; and a read current resistor coupled to the read current transistor. The eFuse cell array of claim 18 further comprises: a reference voltage supply configured to supply a reference voltage, wherein the reference voltage supply comprises: a first reference transistor corresponding to the read current transistor; and a first reference resistor corresponding to the read current resistor. The eFuse cell array of claim 19, wherein the reference voltage supply further comprises: a second reference transistor corresponding to the cell read transistor; a second reference resistor corresponding to the fuse element; and a third reference transistor corresponding to the common read transistor. The eFuse cell array of claim 12, wherein the PN diode includes: an N-type doped region in an N-type well region; a P-type doped region in the N-type well region; a trench isolation region surrounding the N-type well region; and a P-type guard ring structure surrounding the trench isolation region. An eFuse cell array as claimed in claim 21, wherein the cell read transistor comprises: a source region and a drain region in a well region; a gate insulating layer and a gate electrode, which are disposed between the source region and the drain region, wherein the source region is electrically coupled to the P-type doped region of the PN diode. An eFuse cell array as claimed in claim 22, wherein the fuse element comprises: a polysilicon layer formed on an isolation region; and a silicide layer formed on the polysilicon layer, wherein a cathode of the fuse element is electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor. The eFuse cell array of claim 12 further comprises: a word line driver configured to select one of the word lines in the cell array; a program driver configured to provide a programming current to the fuse element; and a control logic configured to control the word line driver and the program driver. An eFuse cell array includes: a memory element coupled to a bit line; a PN diode configured to couple the memory element to a write word line; a cell read transistor coupled to the memory element, and a gate of the cell read transistor coupled to a read word line; a common read transistor configured to couple the memory element to a ground through the bit line; and a common program transistor coupled to the memory element through the bit line. The eFuse cell array of claim 25 further comprises a source region of the cell read transistor, an anode of the PN diode, and a cathode of the memory element coupled to a common node thereof. An eFuse cell array as claimed in claim 25, wherein the write word line is coupled to a cathode of the PN diode, and the bit line is coupled to an anode of the memory element. An eFuse cell array as claimed in claim 25, wherein the memory element is a one-time programmable (OTP) memory element and is one of a fuse or an antifuse. An eFuse cell array includes: a plurality of unit cells, each of which includes a memory element coupled to a bit line, a diode configured to couple the memory element to a write word line, and a cell read transistor coupled to the memory element and a read word line; a common read transistor configured to couple the memory element to a ground through the bit line; and A common program transistor is coupled to the memory element through the bit line, wherein a first placement order of the memory element, the cell read transistor and the diode of the odd-numbered unit cells among the plurality of unit cells is opposite to a second placement order of the memory element, the cell read transistor and the diode of the even-numbered unit cells among the plurality of unit cells. An eFuse cell array as claimed in claim 29, wherein the write word line is coupled to a cathode of the diode, the read word line is coupled to a gate of the cell read transistor, and the bit line is coupled to an anode of the memory element. An eFuse cell array as claimed in claim 29, wherein in each of the plurality of unit cells, a source region of the cell read transistor, an anode of the diode, and a cathode of the memory element are coupled to each other via a common node.