TWI859200B - Memory device, method of operating memory device and memory system - Google Patents

Abstract

A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

Description

Memory device, method for operating memory device, and memory system [Cross reference to related applications]

This U.S. non-provisional patent application claims priority to U.S. provisional application No. 62/816,509 filed on March 11, 2019 in the U.S. Patent and Trademark Office and Korean patent application No. 10-2019-0161673 filed on December 6, 2019 in the Korean Intellectual Property Office. The disclosures of the above applications are fully incorporated into this application for reference.

The present invention relates to apparatus and methods, and more particularly to a memory device that performs internal processing operations by using a predefined protocol interface, a method of operating a memory device, and a memory system including a memory device.

High-performance applications and graphics algorithms are data-intensive and computationally intensive. Applications that run deep neural networks require computing systems with large computing power and memory capabilities to accurately train or learn different data sets. Processing-in-memory (PIM) processors can be located within a memory device to perform some of the computing system's computational operations in the form of internal processing. By internal processing in a memory device, the computing system's computational operation load can be reduced.

However, when a separate interface for internal processing is required, the hardware configuration of the memory device may become complicated to implement. Therefore, the cost of supporting the internal processing operation may increase.

At least one exemplary embodiment of the inventive concept provides a memory device that performs internal processing operations by using a predefined protocol interface, a method of operating the memory device, and a memory system including the memory device.

According to an exemplary embodiment of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array including a first memory area and a second memory area; a signal line (e.g., a command signal line/address signal line) configured to receive a command and an address from a source outside the memory device; a mode selector circuit configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command; a command converter circuit configured to convert the received command into an internal processing operation command in response to activation of the processing mode selection signal; and an internal processor configured to perform an internal processing operation on the first memory area in response to the internal processing operation command in the internal processing mode.

According to an exemplary embodiment of the inventive concept, a method for operating a memory device is provided, wherein the memory device includes a memory cell array and an internal processor, wherein the memory cell array includes a first memory area and a second memory area, and the internal processor is configured to perform an internal processing operation, wherein the method includes: receiving a command and an address from a source outside the memory device via a predefined protocol interface; The address received together with the command generates a processing mode selection signal for controlling the memory device to enter an internal processing mode; in response to the activation of the processing mode selection signal, the received command is converted into an internal processing operation command; and in the internal processing mode, the internal processor performs an internal processing operation on the first memory area in response to the internal processing operation command.

According to an exemplary embodiment of the inventive concept, a memory system is provided, the memory system including: a memory device; and a memory controller configured to control the memory device using a predefined protocol interface connected to the memory device. The memory device includes: a memory cell array including a first memory area and a second memory area; a mode selector circuit configured to receive a command and an address from the memory controller via the predefined protocol interface, and based on the address received together with the command, generate a processing mode selection signal for controlling the memory device to enter an internal processing mode; a command converter circuit configured to convert the received command into an internal processing operation command in response to activation of the processing mode selection signal; and an internal processor configured to perform an internal processing operation on the first memory area in response to the internal processing operation command in the internal processing mode.

100: System

110: Host device

112:Memory controller

114: Memory physical layer interface

116: Control register

120, 120a: memory device

121: Memory cell array

122: Processing area in memory

124: Normal memory area

126: Processing command converter in memory

130:Memory bus

132: Command/address signal line

134: Data line

210, 210a: Processing mode selector in memory

221: Input signal line

222: Output signal line

231: First switch

232: Second switch

240: Internal command signal line

250:PIM engine

260: Data input/output circuit

301: Memory layer/first memory layer/lower memory layer

302: Memory layer/Second memory layer/Lower memory layer

303: Memory layer/Third memory layer/Lower memory layer

304: Memory layer/Fourth memory layer/Lower memory layer

305: Fifth memory layer/upper memory layer/memory layer

306: Sixth memory layer/upper memory layer/memory layer

307: Seventh memory layer/upper memory layer/memory layer

308: Eighth memory layer/upper memory layer/memory layer

310: Buffer grain

810: Enter PIM mode to check circuit

820: PIM mode exit check circuit

830: PIM mode selection signal generation circuit

ADDR: address/address signal/sequential address

CH1: Common channel/first common channel

CH2: common channel/second common channel

CH3: common channel/third common channel

CH4: common channel/fourth common channel

CH5: Shared channel/fifth shared channel

CH6: Common channel/sixth common channel

CH7: Common channel/seventh common channel

CH8: Common channel/eighth common channel

CH1a, CH2a, CH3a, CH4a, CH5a, CH6a, CH7a, CH8a, CH1b, CH2b, CH3b, CH4b, CH5b, CH6b, CH7b, CH8b: Channel

CK: Clock signal

CMD: Command

DQ: Data to be written/data to be read/data

NOP:

P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b, P8b: electrode pads

PIM_CMD: Internal processing operation command

PIM_ENTER: PIM mode entry signal

PIM_EXIT: PIM mode exit signal

PIM_SEL: PIM mode selection signal

RD: Read command

S610, S620, S630, S640, S641, S642, S650, S651, S905, S911, S912, S920, S930, S940, S941, S942, S950, S951: Operation

SID: stack identification signal

Ta, Tb, Tc, Td: time point

tCCD: CAS to CAS delay/timing parameters

tRTW: read to write delay/timing parameters

TSV1, TSV2, TSV3, TSV4, TSV5, TSV6, TSV7, TSV8: Through Silicon Via

WR: write command

The exemplary embodiments of the present inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a diagram showing a system including a memory device that performs internal processing operations according to an exemplary embodiment of the present inventive concept.

FIG. 2 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

Figures 3 to 5 are diagrams illustrating a portion of the structure of the memory device shown in Figure 2.

FIG. 6 is a flow chart illustrating the operation of the memory device shown in FIG. 2 according to an exemplary embodiment of the inventive concept.

FIG. 7 is a timing diagram illustrating the operation of the memory device shown in FIG. 2 according to an exemplary embodiment of the inventive concept.

FIG8 is a diagram illustrating the PIM mode selector shown in FIG2 according to an exemplary embodiment of the concepts of the present invention.

FIG. 9 is a flow chart illustrating the operation of the memory device shown in FIG. 2 according to an exemplary embodiment of the inventive concept.

FIG. 1 is a diagram showing a system including a memory device that performs internal processing operations according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 , the system 100 includes a host device 110 and a memory device 120. The host device 110 can be communicatively connected to the memory device 120 via a memory bus 130.

The expressions "connected" and/or "coupled" and their derivatives may be used to illustrate some examples. These terms are not necessarily intended to be synonymous with each other. For example, descriptions using the terms "connected" and/or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. Additionally, the terms "connected" and/or "coupled" may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

The host device 110 may be, for example, a computing system such as a computer, a laptop, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, or a portable device. Alternatively, the host device 110 may be one of a plurality of components included in the computing system, such as a graphics card.

The host device 110 is a functional block that implements general computer operations in the system 100 and may correspond to a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or an application processor (AP). The host device 110 may include a memory controller 112 (e.g., a control circuit) that manages data transmission and reception to and from the memory device 120.

The memory controller 112 may access the memory device 120 according to the memory request of the host device 110. The memory controller 112 includes a memory physical layer interface 114 for interfacing with the memory device 120. For example, the memory controller 112 may be used to select a row and a column corresponding to a memory location, write data to a memory location, or read written data. The memory physical layer interface 114 may be referred to as a memory PHY 114.

The memory controller 112 includes a control register 116. The control register 116 may be used to initialize the memory device 120 and/or control the memory device 120 according to the operating characteristics of the memory device 120. After power is supplied to the system 100, the memory controller 112 may set the control register 116. The control register 116 may store various codes configured to allow the memory controller 112 to interoperate normally with the memory device 120. For example, codes indicating frequency, timing, and detailed operating parameters of the memory device 120 may be stored in the control register 116. In addition, the control register 116 may store specific address information used by the memory controller 112 to physically or logically divide the memory cell array 121 of the memory device 120 according to the operation mode.

For example, the specific address information may indicate a specific address for dividing the memory cell array 121 into the PIM area 122 and the normal memory area 124. The PIM area 122 may be a memory cell area accessed when the memory device 120 operates in the internal processing mode, and the normal memory area may be a memory cell area accessed when the memory device 120 operates in the normal mode. For example, the specific address may indicate an address for accessing the PIM area 122 and may be used as a basic signal for allowing the memory device 120 to enter the internal processing mode. The specific address may include, for example, a stack identification signal, a channel address, or a memory bank address. According to an embodiment, the specific address may include a combination of a stack identification signal, a channel address and/or a memory bank address.

The memory controller 112 may control a write operation or a read operation of the memory device 120 by providing a command CMD (e.g., a read command, a write command, a verification command, etc.) and an address ADDR to the memory device 120. In addition, data DQ to be written and data DQ to be read may be transmitted and received between the memory controller 112 and the memory device 120. During a first memory access operation, data DQ may be transmitted from the memory controller 112 to the memory device 120, the memory device 120 may receive the transmitted data DQ, and then the memory device 120 may write the received data DQ to the memory cell array 121. During the second memory access operation, the memory device 120 may read the data DQ from the memory cell array 121, the memory device 120 may transmit the read data DQ to the memory controller 112, and then the memory controller 112 may receive the transmitted data DQ. This memory access operation may be performed between the memory controller 112 and the memory device 120 via the memory PHY 114 and the memory bus 130.

The memory PHY 114 provides the signals, frequencies, timings, detailed operating parameters, and functional physical or electrical layers and logical layers required for efficient communication between the memory controller 112 and the memory device 120. The memory PHY 114 may support the features of the double data rate (DDR) protocol and/or the low power double data rate (LPDDR) protocol of the Joint Electronic Device Engineering Council (JEDEC) standard.

The memory PHY 114 may include a connector for connecting the memory controller 112 and the memory device 120. The connector may be implemented in the form of a pin, a ball, a signal line, or other hardware components. For example, a clock signal CK (FIG. 7), a command CMD, an address ADDR, and data DQ may be transmitted and received between the memory controller 112 and the memory device 120 via the memory PHY 114.

Reusing existing connectors in the memory PHY 114 can save a significant amount of space in the integrated circuit IC and avoid the cost of extending additional wiring to the memory device 120. In addition, avoiding additional pins and wiring eliminates potential electromagnetic interference (EMI) caused by the presence of additional wiring, and power savings can be achieved because a large number of drivers and receivers are not required.

The memory bus 130 may include a command/address signal line 132 for transmitting a command/address CMD/ADDR and a data line 134 for transmitting data DQ. To simplify the diagram, the command/address signal line 132 and the data line 134 are illustrated as a single line between the memory controller 112 and the memory device 120, but the command/address signal line 132 and the data line 134 may actually be multiple signal lines.

The memory device 120 may write data or read data under the control of the memory controller 112. For example, the memory device 120 may be a DDR synchronous dynamic random access memory (SDRAM) device. However, the inventive concept is not limited thereto, and the memory device 120 may be any of volatile memory devices, such as LPDDR SDRAM, wide input/output (I/O) DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC). According to an embodiment, the memory device 120 may be any of non-volatile memory devices, such as flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

In an exemplary embodiment of the inventive concept, the memory device 120 operates in one of a normal mode and an internal processing mode. The normal mode refers to an operation mode in which general data transaction operations are performed, and the internal processing mode refers to an operation mode in which internal processing operations are performed.

In normal mode, the memory device 120 performs general data transaction operations under the control of the memory controller 112. General data transaction operations are data exchange operations performed according to a predefined protocol (such as the DDR protocol and/or the LPDDR protocol).

In the internal processing mode, the memory device 120 performs internal processing operations under the control of the memory controller 112. The memory controller 112 may provide a specific address to the memory device 120 via the command/address signal line 132 using a predefined protocol (such as the DDR protocol and/or the LPDDR protocol), and the specific address is the basis for the internal processing operation to be performed by the memory device 120. The memory device 120 may enter the internal processing mode based on the specific address. The specific address may be provided via an existing connection of the memory PHY 114.

For example, when the memory device 120 is installed in the system 100, a specific address that is the basis for internal processing operations can be statically set. Static setting means that a specific address information can be used to fix the specific address. According to an exemplary embodiment, the specific address is dynamically set before and after the internal processing operation of the memory device 120. Various combinations of specific address information can be used to change the specific address during dynamic setting.

The memory device 120 includes a memory cell array 121 and a PIM command converter 126 (e.g., a processor or a logic circuit). The memory cell array 121 includes a PIM area 122 and a normal memory area 124 that are physically or logically divided according to the operation mode of the memory device 120.

The PIM area 122 may refer to a memory cell area configured to access internal processing data for internal processing operations performed in an internal processing mode. The internal processing operations of the memory device 120 may include operations of writing to the PIM area 122 and/or operations of reading from the PIM area 122.

The normal memory area 124 may refer to a memory cell area configured to access data according to a general data transaction operation performed in a normal mode. The data transaction operation of the memory device 120 may include an operation of writing to the normal memory area 124 and/or an operation of reading from the normal memory area 124.

When the address ADDR received via the command/address signal line 132 includes a specific address that is the basis of the internal processing operation, the PIM command converter 126 converts the command CMD received via the command/address signal line 132 into the internal processing operation command PIM_CMD. For example, the PIM command converter 126 can convert the command CMD received via the command/address signal line 132 into the internal processing operation command PIM_CMD indicating the type of internal processing operation, and the internal processing operation type includes, for example: data search, data arithmetic operation (such as addition, subtraction, multiplication, division, etc.), data movement, data inversion, data shift, data exchange, data comparison, logical operation, data processing/operation, etc. The internal processing operation command PIM_CMD may include an internal processing read command and/or an internal processing write command associated with the internal processing operation.

An internal processing operation of reading internal processing data from the PIM area 122 or writing internal processing data to the PIM area 122 may be performed according to the internal processing operation command PIM_CMD. The internal processing data may refer to reference data or target data used in the internal processing operation. In addition, the internal processing data may include address information related to the internal processing operation (such as data exchange).

FIG. 2 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

1 and 2, the memory device 120 includes: a memory cell array 121, including a PIM area 122 and a normal memory area 124; a PIM command converter 126; a PIM mode selector 210 (e.g., a logic circuit); a first switch 231; a second switch 232; a PIM engine 250 (e.g., a processor or a logic circuit); and a data input/output circuit 260.

In the memory cell array 121, the PIM area 122 may be an area defined to access (e.g., store) and output internal processing data for internal processing operations when the memory device 120 operates in the internal processing mode. The normal memory area 124 may be an area defined to access data according to general data transaction operations when the memory device 120 operates in the normal mode. The PIM area 122 and the normal memory area 124 may be set as fixed areas in the memory cell array 121. In an exemplary embodiment where the area is fixed, its size and physical position within the memory cell array 121 remain constant. According to an embodiment, the PIM area 122 and the normal memory area 124 may be set as variable areas in the memory cell array 121. In the exemplary embodiment where the region is variable, its size and physical location within the memory cell array 121 can be changed dynamically based on one or more conditions.

When the memory device 120 operates in the internal processing mode, the PIM command converter 126 can convert the command CMD received via the command/address signal line 132 into the internal processing operation command PIM_CMD.

The PIM mode selector 210 may receive the address ADDR from the memory controller 112 via the command/address signal line 132 of the memory bus 130 and output the PIM mode selection signal PIM_SEL in response to the received address ADDR. The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL according to the determination result. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate an internal processing mode when the received address ADDR is within a predefined range of addresses, and outputs a PIM mode selection signal PIM_SEL set to a second other logic level to indicate a normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or may be the specific address itself.

In an exemplary embodiment, the specific address learned by the PIM mode selector 210 is the same as the specific address stored in the control register 116 of the memory controller 112 and used to address the PIM area 122. For example, one or more addresses may be stored in the control register 116 as the specific address. The PIM mode selection signal PIM_SEL is used as a control signal to determine whether the memory device 120 enters the internal processing mode and operates in the internal processing mode or enters the normal mode and operates in the normal mode. Alternatively, the specific address may be stored outside the control register 116 of the memory controller 112, in the memory of the memory controller 112, or in the memory of the host device 110 outside the memory controller.

When the address ADDR received via the command/address signal line 132 includes a specific bit address, the PIM mode selector 210 may enable the PIM mode selection signal PIM_SEL. By enabling the PIM mode selection signal PIM_SEL, the memory device 120 may operate in the internal processing mode. When the address ADDR received via the command/address signal line 132 does not include a specific bit address, the PIM mode selector 210 may disable the PIM mode selection signal PIM_SEL. For example, the PIM mode selection signal PIM_SEL may be enabled by setting the PIM mode selection signal PIM_SEL to a first logic level, and the PIM mode selection signal PIM_SEL may be disabled by setting the PIM mode selection signal PIM_SEL to a second logic level. By disabling the PIM mode selection signal PIM_SEL, the memory device 120 can operate in a normal mode. The PIM mode selection signal PIM_SEL can be provided to the first switch 231 and the second switch 232.

The first switch 231 can selectively connect the command/address signal line 132 to the input signal line 221 or the internal command signal line 240 of the PIM command converter 126 in response to the PIM mode selection signal PIM_SEL. The second switch 232 can selectively connect the output signal line 222 or the internal command signal line 240 of the PIM command converter 126 to the memory cell array 121 and the PIM engine 250 in response to the PIM mode selection signal PIM_SEL.

The first switch 231 may selectively connect the command/address signal line 132 to the input signal line 221 of the PIM command converter 126 in response to the activation of the PIM mode selection signal PIM_SEL. The first switch 231 may provide the command CMD received via the command/address signal line 132 to the PIM command converter 126. The PIM command converter 126 may convert the command CMD received via the input signal line 221 into an internal processing operation command PIM_CMD and output the internal processing operation command PIM_CMD to the output signal line 222. The internal processing operation command PIM_CMD may be a command associated with an internal processing operation performed in the internal processing mode.

The second switch 232 may connect the output signal line 222 of the PIM command converter 126 to the memory cell array 121 and/or the PIM engine 250 in response to the activation of the PIM mode selection signal PIM_SEL. The second switch 232 may provide the internal processing operation command PIM_CMD outputted via the output signal line 222 of the PIM command converter 126 to the PIM area 122 of the memory cell array 121 and/or the PIM engine 250. The PIM engine 250 may access the PIM area 122 and perform internal processing operations according to the internal processing operation command PIM_CMD. For example, the internal processing operation may include processing operations performed on the internal processing data stored in the PIM area 122, such as data search, data arithmetic operation (such as addition, subtraction, multiplication, division, etc.), data movement, data inversion, data shift, data exchange, data comparison, logical operation, data processing/operation, etc.

The first switch 231 can connect the command/address signal line 132 to the internal command signal line 240 in response to the disabling of the PIM mode selection signal PIM_SEL and the command CMD received via the command/address signal line 132 to the internal command signal line 240. The command CMD provided to the internal command signal line 240 can be a command associated with a data transaction operation performed in the normal mode.

The second switch 232 can connect the internal command signal line 240 to the memory cell array 121 in response to the disabling of the PIM mode selection signal PIM_SEL. The normal memory area 124 of the memory cell array 121 can be accessed according to the command CMD provided to the internal command signal line 240, and thus a data transaction operation can be implemented. For example, the second switch 232 can connect the internal command signal line 240 to the normal memory area 124 in response to the disabling of the PIM mode selection signal PIM_SEL.

When the memory device 120 operates in the internal processing mode, the PIM engine 250 may perform the internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 may perform the internal processing operation on the internal processing data by using the PIM area 122 of the memory cell array 121 according to the internal processing operation command PIM_CMD.

The PIM engine 250 is hardware having processing functionality, similar to a processor (e.g., a CPU) included in the host device 110. When the PIM engine 250 is referred to as an internal processor, the term "internal" means that the PIM engine 250 exists within the memory device 120. Therefore, a processor existing "outside" the memory device 120 may refer to, for example, a processor of the host device 110.

The data input/output circuit 260 can be used as a write driver (e.g., a driver circuit) or a sense amplifier of the memory device 120. The data input/output circuit 260 can receive data DQ from the memory controller 112 via the data line 134 of the memory bus 130, and provide the received data DQ to the memory cell array 121 and/or the PIM engine 250. The data input/output circuit 260 can receive data DQ from the memory cell array 121 and/or the PIM engine 250, and transmit the received data DQ to the memory controller 112 via the data line 134.

When the memory device 120 operates in the internal processing mode, the PIM engine 250 may perform internal processing operations. In this case, the PIM engine 250 may transmit data DQ to/receive data DQ from the memory controller 112 via the data input/output circuit 260 and the data line 134.

For example, when the PIM engine 250 performs an internal processing operation in response to the internal processing operation command PIM_CMD, the data DQ received via the data line 134 and the data input/output circuit 260 may be stored in the PIM area 122 of the memory cell array 121 as internal processing data. The PIM engine 250 may store the internal processing data according to the internal processing operation performed in response to the internal processing operation command PIM_CMD in the PIM area 122. The PIM engine 250 may read the internal processing data from the PIM area 122 according to the internal processing operation command PIM_CMD. The PIM engine 250 may perform an internal processing operation based on the internal processing data read from the PIM area 122. The PIM engine 250 can transmit the internal processing data processed by the internal processing operation to the memory controller 112 via the data input/output circuit 260 and the data line 134.

The internal processing operation may be partially or mainly a data exchange operation performed according to the internal processing operation command PIM_CMD. The data exchange operation may include an operation of reading internal processing data (e.g., reference data, source data, destination data, or target data) used for the internal processing operation from the PIM area 122 and/or an operation of writing the result of the internal processing operation to the PIM area 122. For example, it is considered that the PIM engine 250 performs internal processing operations such as data search, data movement, data arithmetic operations (e.g., addition, subtraction, multiplication, division, etc.) and data exchange according to the internal processing operation command PIM_CMD.

When the internal processing operation command PIM_CMD is a data search command, the PIM engine 250 may search whether the internal processing data corresponding to the data search is stored in the PIM area 122. The PIM engine 250 may output hit/miss information and/or corresponding address information according to the result of the data search operation. The PIM engine 250 may write the hit/miss information or corresponding address information associated with the data search operation to the PIM area 122. For example, the hit/miss information may be a first value indicating that the data exists in the PIM area 122 and a second other value indicating that the data does not exist in the PIM area 122. For example, the address information may be set to the physical address of the data in the PIM area 122 when the data exists, and the address information may be set to an invalid address (e.g., -1) when the data does not exist.

When the internal processing operation command PIM_CMD is a data move command, the PIM engine 250 may move the data corresponding to the reference address information in the PIM area 122 to the target area. The PIM engine 250 may output the address information of the data move-in area as a result of the data move operation. The data move operation performed by the PIM engine 250 and the operation of writing the address information about the data move-in area may be implemented in the PIM area 122. The target area may be the PIM area 122 or the normal memory area 124. For example, the data move operation may move the data stored in the first location of the PIM area 122 to a second other location located in the PIM area 122 or the normal memory area 124.

When the internal processing operation command PIM_CMD is a data addition command, the PIM engine 250 may read data corresponding to the reference address information from the PIM area 122, add the internal processing data and the read data to generate a sum, and store the added data (e.g., the sum) in the PIM area 122. The PIM engine 250 may output address information about the area storing the added data as a result of the data addition operation. The data addition operation performed by the PIM engine 250 and the operation of writing the address information about the area storing the added data may be performed in the PIM area 122. In an alternative embodiment, the internal processing operation command PIM_CMD is a command of one of various arithmetic operations (e.g., data subtraction, data multiplication, or data division). For example, the internally processed data can be subtracted from the read data, the internally processed data can be multiplied by the read data, or the read data can be divided by the internally processed data.

When the internal processing operation command PIM_CMD is a data exchange command, the PIM engine 250 can read the first data and the second data corresponding to the first reference address information and the second reference address information respectively from the PIM area 122, exchange the first data and the second data with each other, and store the exchanged first data and second data in the memory cells corresponding to the first reference address information and the second reference address information of the PIM area 122. The data exchange operation performed by the PIM engine 250 can be implemented in the PIM area 122.

When the memory device 120 operates in the normal mode, the data input/output circuit 260 can receive the data DQ received from the memory controller 112 via the data line 134, store (write) the data DQ in the normal memory area 124 of the memory cell array 121, and transmit the data read from the normal memory area 124 to the memory controller 112 via the data line 134. The memory device 120 can perform data transaction operations by using the normal memory area 124.

FIG3 is a diagram illustrating a portion of the structure of the memory device shown in FIG2.

2 and 3 , the memory device 120 includes a plurality of stacked memory layers 301 to 308. For example, the memory device 120 may be an HBM. The memory layers 301 to 308 may be referred to as core dies. The memory layers 301 to 308 may constitute a plurality of independent interfaces referred to as channels. The memory layers 301 to 308 may each include two channels. To conceptually illustrate the present invention and simplify the diagram, FIG3 shows an exemplary configuration in which odd channels (e.g., CH1a, CH3a, CH5a, CH7a, CH1b, CH3b, CH5b, and CH7b) are arranged on the left side of memory layers 301 to 308 and even channels (e.g., CH2a, CH4a, CH6a, CH8a, CH2b, CH4b, CH6b, and CH8b) are arranged on the right side of memory layers 301 to 308, but the arrangement of memory layers 301 to 308 according to the present invention is not limited thereto.

For example, the first memory layer 301 may include a channel CH1a and a channel CH2a, the second memory layer 302 may include a channel CH3a and a channel CH4a, the third memory layer 303 may include a channel CH5a and a channel CH6a, and the fourth memory layer 304 may include a channel CH7a and a channel CH8a. The fifth memory layer 305 may include a channel CH1b and a channel CH2b, the sixth memory layer 306 may include a channel CH3b and a channel CH4b, the seventh memory layer 307 may include a channel CH5b and a channel CH6b, and the eighth memory layer 308 may include a channel CH7b and a channel CH8b. In the embodiment of the present invention of FIG. 3 , the example of the memory device 120 is illustrated as being stacked with eight memory layers 301 to 308. However, the concept of the present invention is not limited thereto. According to an embodiment, various numbers of memory layers (e.g., 2, 4, etc.) can be stacked in the memory device 120.

The memory device 120 may further include a buffer die 310 located below the stacked memory layers 301 to 308. The buffer die 310 may be referred to as a memory buffer. The buffer die 310 may include an input buffer (or receiver) that receives a clock signal CK, a command CMD, an address ADDR, and data DQ from the memory controller 112 ( FIG. 1 ). The buffer die 310 can provide signal distribution functions and data input/output functions by means of channels CH1a, CH2a, CH3a, CH4a, CH5a, CH6a, CH7a, CH8a, CH1b, CH2b, CH3b, CH4b, CH5b, CH6b, CH7b and CH8b, and through silicon vias TSV1 to TSV8. The buffer die 310 can communicate with the memory controller 112 via a conductive unit (such as a bump or solder ball) formed on the outer surface of the memory device 120.

The buffer die 310 may include the PIM command converter 126, the PIM mode selector 210, the first switch 231, the second switch 232, the PIM engine 250, and the data input/output circuit 260 described above with reference to FIG. 2.

The stacked memory layers 301 to 308 may correspond to the memory cell array 121 including the PIM area 122 and the normal memory area 124 described above with reference to FIG. 2 . The lower four memory layers 301 to 304 of the stacked memory layers 301 to 308 may be assigned to the PIM area 122, and the upper four memory layers 305 to 308 may be assigned to the normal memory area 124. According to an exemplary embodiment of the inventive concept, the lower four memory layers 301 to 304 of the stacked memory layers 301 to 308 are assigned to the normal memory area 124, and the upper four memory layers 305 to 308 are assigned to the PIM area 122.

The memory layers 301 to 304 of the PIM region 122 and the memory layers 305 to 308 of the normal memory region 124 may form common channels CH1 to CH8 via through silicon vias TSV1 to TSV8 and electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b and P8b electrically connected to the through silicon vias TSV1 to TSV8. For simplicity of the drawing, the electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b and P8b are shown as circles. It can be understood that the electrode pads P1a, P2a, P3a, P4a, P5a, P6a, P7a, P8a, P1b, P2b, P3b, P4b, P5b, P6b, P7b and P8b are electrically connected to the through-silicon vias TSV1 to TSV8, respectively.

For example, the channel CH1a of the first memory layer 301 can be connected to the through-silicon via TSV1 via the electrode pad P1a, and the channel CH1b of the fifth memory layer 305 can be connected to the through-silicon via TSV1 via the electrode pad P1b. The channel CH1a and the channel CH1b electrically connected to the through-silicon via TSV1 can form a first common channel CH1. In addition, the channel CH2a of the first memory layer 301 can be connected to the through-silicon via TSV2 via the electrode pad P2a, and the channel CH2b of the fifth memory layer 305 can be connected to the through-silicon via TSV2 via the electrode pad P2b. The channel CH2a and the channel CH2b electrically connected to the through-silicon via TSV2 can form a second common channel CH2.

The channel CH3a of the second memory layer 302 can be connected to the through-silicon via TSV3 via the electrode pad P3a, and the channel CH3b of the sixth memory layer 306 can be connected to the through-silicon via TSV3 via the electrode pad P3b. The channel CH3a and the channel CH3b electrically connected to the through-silicon via TSV3 can form a third common channel CH3. In addition, the channel CH4a of the second memory layer 302 can be connected to the through-silicon via TSV4 via the electrode pad P4a, and the channel CH4b of the sixth memory layer 306 can be connected to the through-silicon via TSV4 via the electrode pad P4b. The channel CH4a and the channel CH4b electrically connected to the through-silicon via TSV4 can form a fourth common channel CH4.

The channel CH5a of the third memory layer 303 can be connected to the through-silicon via TSV5 via the electrode pad P5a, and the channel CH5b of the seventh memory layer 307 can be connected to the through-silicon via TSV5 via the electrode pad P5b. The channel CH5a and the channel CH5b electrically connected to the through-silicon via TSV5 can form a fifth common channel CH5. In addition, the channel CH6a of the third memory layer 303 can be connected to the through-silicon via TSV6 via the electrode pad P6a, and the channel CH6b of the seventh memory layer 307 can be connected to the through-silicon via TSV6 via the electrode pad P6b. The channel CH6a and the channel CH6b electrically connected to the through-silicon via TSV6 can form a sixth common channel CH6.

The channel CH7a of the fourth memory layer 304 can be connected to the through-silicon via TSV7 via the electrode pad P7a, and the channel CH7b of the eighth memory layer 308 can be connected to the through-silicon via TSV7 via the electrode pad P7b. The channel CH7a and the channel CH7b electrically connected to the through-silicon via TSV7 can form the seventh common channel CH7. In addition, the channel CH8a of the fourth memory layer 304 can be connected to the through-silicon via TSV8 via the electrode pad P8a, and the channel CH8b of the eighth memory layer 308 can be connected to the through-silicon via TSV8 via the electrode pad P8b. The channel CH8a and the channel CH8b electrically connected to the through-silicon via TSV8 can form the eighth common channel CH8.

The first common channel CH1 to the eighth common channel CH8 of the memory cell array 121 may be connected to the buffer die 310. In the first common channel CH1 to the eighth common channel CH8, the PIM area 122 and the normal memory area 124 may be selectively accessed according to the stack identification signal SID that distinguishes the lower memory layers 301 to 304 from the upper memory layers 305 to 308. For example, when the stack identification signal SID is logical "0", the lower memory layers 301 to 304 (i.e., the PIM area 122) among the first common channel CH1 to the eighth common channel CH8 may be accessed. When the stack identification signal SID is logical "1", the upper memory layers 305 to 308 (i.e., the normal memory area 124) in the first common channel CH1 to the eighth common channel CH8 can be accessed.

As described above with reference to FIG. 2 , when the memory device 120 operates in the internal processing mode, the PIM area 122 can be accessed. In an exemplary embodiment, when the stack identification signal SID set to logic "0" is included in the address ADDR received via the command/address signal line 132 of the memory bus 130 and the PIM mode selector 210 enables the PIM mode selection signal PIM_SEL, the memory device 120 operates in the internal processing mode. Since the PIM mode selection signal PIM_SEL is enabled, the memory device 120 can access the PIM area 122 and operate in the internal processing mode.

When the memory device 120 operates in the normal mode, the normal memory area 124 can be accessed. In an exemplary embodiment, when the stack identification signal SID set to logic "1" is included in the address ADDR received via the command/address signal line 132 of the memory bus 130 and the PIM mode selector 210 disables the PIM mode selection signal PIM_SEL, the memory device 120 operates in the normal mode. Since the PIM mode selection signal PIM_SEL is disabled, the memory device 120 can access the normal memory area 124 and operate in the normal mode.

In the embodiment of the present invention, the stack identification signal SID may be a specific address that is stored in the control register 116 and divides the memory cell array 121 of the memory device 120 into the PIM area 122 and the normal memory area 124. In addition, the stack identification signal SID may be a specific address for addressing the PIM area 122 identified by the PIM mode selector 210.

FIG4 is a diagram illustrating a portion of the structure of the memory device shown in FIG2.

Referring to FIG. 4 , the memory device 120a is different from the memory device 120 shown in FIG. 3 in that the memory cell array 121 of the memory device 120a includes the first memory layer 301 to the fourth memory layer 304. In the following text, the description of the memory device 120a that is the same as the description given above with reference to FIG. 3 will be omitted.

In the memory cell array 121 of the memory device 120a, the first memory layer 301 and the second memory layer 302 may be assigned to the PIM area 122, and the third memory layer 303 and the fourth memory layer 304 may be assigned to the normal memory area 124. According to an exemplary embodiment of the inventive concept, the first memory layer 301 and the second memory layer 302 are assigned to the normal memory area 124, and the third memory layer 303 and the fourth memory layer 304 are assigned to the PIM area 122.

The eight channels CH1a to CH8a of the first memory layer 301 to the fourth memory layer 304 can be connected to the buffer die 310 through silicon vias TSV1 to TSV8, respectively. The eight channels CH1a to CH8a can be addressed by a 3-bit channel address. When the most significant bit of the channel address is "0", the channels CH1a, CH2a, CH3a and CH4a of the first memory layer 301 and the second memory layer 302 can be selected. On the contrary, when the most significant bit of the channel address is "1", the channels CH5a, CH6a, CH7a and CH8a of the third memory layer 303 and the fourth memory layer 304 can be selected. Therefore, the PIM area 122 and the normal memory area 124 can be selectively accessed according to the most significant bit of the channel address.

The most significant bit of the channel address is a specific address for dividing the memory cell array 121 of the memory device 120a into the PIM area 122 and the normal memory area 124, and can be stored in the control register 116 of the memory controller 112. In addition, the most significant bit of the channel address can be a specific address for addressing the PIM area 122 identified by the PIM mode selector 210.

FIG5 is a diagram illustrating a portion of the structure of the memory cell array shown in FIG2.

5 , the memory cell array 121 may include, for example, eight memory banks BANK1 to BANK8. The first memory bank BANK1 to the fourth memory bank BANK4 may be assigned to the PIM area 122, and the fifth memory bank BANK5 to the eighth memory bank BANK8 may be assigned to the normal memory area 124. The eight memory banks BANK1 to BANK8 may be addressed by a 3-bit memory bank address. When the most significant bit of the memory bank address is "0", the first memory bank BANK1 to the fourth memory bank BANK4 may be selected. On the contrary, when the most significant bit of the memory bank address is "1", the fifth memory bank BANK5 to the eighth memory bank BANK8 may be selected. Therefore, the PIM area 122 and the normal memory area 124 can be selectively accessed based on the most significant bit of the memory library address.

The most significant bit of the memory bank address is a specific address for dividing the memory cell array 121 into the PIM area 122 and the normal memory area 124, and can be stored in the control register 116 of the memory controller 112. In addition, the most significant bit of the memory bank address can be a specific address for addressing the PIM area 122 identified by the PIM mode selector 210.

The PIM area 122 and the normal memory area 124 described above with reference to FIGS. 3 to 5 are examples of fixed areas in the memory cell array 121 that are set by the stack identification signal SID, the channel address, or the memory bank address. The specific address information for setting the PIM area 122 and the normal memory area 124 as fixed areas can be statically set in the control register 116 of the memory controller 112.

According to an embodiment of the present invention, the PIM area 122 and the normal memory area 124 are set as variable areas in the memory cell array 121 according to a combination of the stack identification signal SID, the channel address and/or the memory library address. Specific address information for setting the PIM area 122 and the normal memory area 124 as variable areas can be dynamically set in the control register 116 of the memory controller 112.

FIG. 6 is a flow chart illustrating the operation of the memory device shown in FIG. 2 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 , FIG. 2 , and FIG. 6 , in operation S610 , the memory device 120 provides specific address information about the PIM area 122 and the normal memory area 124 of the memory cell array 121 to the memory controller 112 . The specific address information may include a specific address for dividing the memory cell array 121 into the PIM area 122 and the normal memory area 124 . The specific address is an address for addressing the PIM area 122 and may include, for example, a stack identification signal SID, a channel address, and/or a memory bank address. The specific address information may be stored in the control register 116 of the memory controller 112 .

In operation S620, the memory device 120 receives a command CMD and a specific address from the memory controller 112 via the command/address signal line 132. The memory controller 112 may issue a command CMD for accessing the memory device 120 based on a memory request of the host device 110. In this case, the command CMD and the specific address may be provided between the memory controller 112 and the memory device 120 via the memory PHY 114, which supports the DDR protocol and/or the LPDDR protocol of the JEDEC standard. For example, the specific address is considered to be a stack identification signal SID, as described above with reference to FIG. 3.

In operation S630, the memory device 120 determines whether the stack identification signal SID received as a specific address together with the command CMD in operation S620 addresses the PIM area 122 of the memory cell array 121. As described above with reference to FIG. 3, when the stack identification signal SID is provided as a logic "0", the lower memory layers 301 to 304 (i.e., the PIM area 122) among the first common channel CH1 to the eighth common channel CH8 can be accessed. On the contrary, when the stack identification signal SID is provided as a logic "1", the upper memory layers 305 to 308 (i.e., the normal memory area 124) among the first common channel CH1 to the eighth common channel CH8 can be accessed.

When the stack identification signal SID is logical "0", in operation S640, the memory device 120 enters the internal processing mode. The PIM mode selector 210 of the memory device 120 may enable the PIM mode selection signal PIM_SEL in response to the stack identification signal SID being logical "0". By enabling the PIM mode selection signal PIM_SEL, the memory device 120 may operate in the internal processing mode.

In operation S641, the memory device 120 converts the command CMD received in operation S620 into an internal processing operation command PIM_CMD. The PIM command converter 126 of the memory device 120 may convert the received command CMD into an internal processing operation command PIM_CMD indicating an internal processing operation type, the internal processing operation type including, for example: data search, data arithmetic operation (e.g., addition, subtraction, multiplication, division, etc.), data movement, data inversion, data shift, data exchange, data comparison, logical operation and/or data processing/operation.

In operation S642, the memory device 120 performs an internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 of the memory device 120 may perform the internal processing operation using the PIM area 122 of the memory cell array 121 according to the internal processing operation command PIM_CMD. The PIM engine 250 may store internal processing data, which is a result of the internal processing operation performed in the PIM area 122 in response to the internal processing operation command PIM_CMD. Alternatively, the PIM engine 250 may read the internal processing data from the PIM area 122 in response to the internal processing operation command PIM_CMD and perform the internal processing operation based on the read internal processing data. When the internal processing operation of operation S642 is completed, the memory device 120 can proceed to operation S620 and receive the next command CMD and a specific address.

In operation S640, when the stack identification signal SID is not a logical "0", the memory device 120 enters the normal mode in operation S650. The PIM mode selector 210 of the memory device 120 may disable the PIM mode selection signal PIM_SEL in response to the stack identification signal SID being a logical "1". By disabling the PIM mode selection signal PIM_SEL, the memory device 120 may operate in the normal mode.

In operation S651, the memory device 120 performs a data transaction operation according to the command CMD received in operation S620. The command CMD may be associated with a data transaction operation performed in a normal mode. The memory device 120 may store (write) the data DQ received from the memory controller 112 in the normal memory area 124 of the memory cell array 121 via the data line 134 according to the command CMD, read data from the normal memory area 124, and transmit the read data to the memory controller 112 via the data line 134 as data DQ. When the data transaction operation of operation S651 is completed, the memory device 120 may proceed to operation S620 and receive the next command CMD and a specific address.

FIG. 7 is a timing diagram illustrating the operation of the memory device shown in FIG. 2 . FIG. 7 shows a timing diagram of the operation performed based on the clock signal CK according to the DDR protocol and/or the LPDDR protocol. To make the diagram simple and easy to explain, FIG. 7 conceptually shows the write operation and read operation of inputting data DQ to/outputting data DQ from the memory device 120 via the data line 134.

Referring to FIG. 1, FIG. 2 and FIG. 7, at time point Ta, the memory device 120 receives the address ADDR including the stack identification signal SID from the memory controller 112 together with the read command RD. At this time, the stack identification signal SID is set to logical "0". Although not shown, an activation command associated with the read command RD may be received from the memory controller 112 before time point Ta.

In response to the stack identification signal SID being a logical "0" at the time point Ta, the memory device 120 enters the internal processing mode. In the internal processing mode, the PIM command converter 126 converts the read command RD into an internal processing read command, and the PIM engine 250 reads the internal processing data written to the memory cell corresponding to the address ADDR in the PIM area 122 of the memory cell array 121 according to the internal processing read command, and performs the internal processing operation using the read internal processing data. The embodiment of the present invention shows a case where the internal processing data read from the PIM area 122 is not transmitted to the memory controller 112 outside the memory device 120. According to another embodiment, the internal processing data processed by the PIM engine 250 is transmitted as data DQ via the data line 134 of the memory bus 130 to the memory controller 112.

At time point Tb, the memory device 120 receives the address ADDR including the stack identification signal SID from the memory controller 112 together with the read command RD. At this time, the stack identification signal SID is set to logic "1".

In response to the stack identification signal SID being logical "1" at time point Tb, the memory device 120 enters the normal mode. In the normal mode, the memory device 120 reads the data D written to the memory cell corresponding to the address signal ADDR in the normal memory area 124 of the memory cell array 121 according to the read command RD. The read data D can be transmitted to the memory controller 112 as data DQ via the data line 134 of the memory bus 130.

At time point Tc, the memory device 120 receives the address ADDR including the stack identification signal SID from the memory controller 112 together with the write command WR. At this time, the stack identification signal SID is set to logical "0".

In response to the stack identification signal SID being logical "0" at time point Tc, the memory device 120 enters the internal processing mode. In the internal processing mode, the PIM command converter 126 converts the write command WR into an internal processing write command, and the PIM engine 250 writes the internal processing data obtained according to the processing result of the internal processing operation to the memory cell corresponding to the address ADDR in the PIM area 122 of the memory cell array 121 according to the internal processing write command.

At time point Td, the memory device 120 receives the address ADDR including the stack identification signal SID from the memory controller 112 together with the write command WR. At this time, the stack identification signal SID is set to logic "1".

In response to the stack identification signal SID being logical "1" at time point Td, the memory device 120 enters the normal mode. In the normal mode, the memory device 120 writes the data D to the memory cell corresponding to the address signal ADDR in the normal memory area 124 of the memory cell array 121 according to the write command WR. Here, the data D to be written can be received from the memory controller 112 as data DQ via the data line 134 of the memory bus 130.

There is a timing parameter called CAS to CAS delay tCCD between the read command RD at time point Ta and the read command RD at time point Tb, which is the minimum time interval required between consecutive read commands. In addition, there is a timing parameter tCCD between the write command WR at time point Tc and the write command WR at time point Td, which is the minimum time interval required between consecutive write commands. The timing parameter tCCD between time point Ta and time point Tb can meet the tCCD timing parameter requirements defined in the DDR specification and/or LPDDR specification of the JEDEC standard. In addition, the timing parameter tCCD between the time point Tc and the time point Td can meet the tCCD timing parameter requirements defined in the JEDEC standard DDR specification and/or LPDDR specification.

There is a timing parameter called read-to-write delay tRTW between the read command RD at time point Tb and the write command WR at time point Tc. The timing parameter tRTW between time point Tb and time point Tc can meet the tRTW timing parameter requirements defined in the JEDEC standard DDR specification and/or LPDDR specification.

FIG8 is a diagram illustrating the PIM mode selector shown in FIG2.

Referring to FIG. 8 , compared with the PIM mode selector 210 shown in FIG. 2 , the PIM mode selector 210a determines whether the address ADDR received together with the command CMD is consistent with the PIM mode entry code and determines whether the address ADDR is consistent with the PIM mode exit code, instead of determining whether the address ADDR received together with the command CMD via the command/address signal line 132 of the memory bus 130 includes a specific address for addressing the PIM area 122.

The PIM mode selector 210a includes a PIM mode entry check circuit 810, a PIM mode exit check circuit 820, and a PIM mode selection signal generation circuit 830.

The PIM mode entry check circuit 810 can store the PIM mode entry code, compare the bit value of the address ADDR sequentially received by the PIM mode selector 210a with the bit value of the PIM mode entry code, and output the PIM mode entry signal PIM_ENTER according to the comparison result. When the bit value of the sequential address ADDR is consistent with the bit value of the PIM mode entry code, the PIM mode entry check circuit 810 can output the PIM mode entry signal PIM_ENTER with a logical "1". Otherwise, the PIM mode entry check circuit 810 can output the PIM mode entry signal with a logical "0". The PIM mode entry signal PIM_ENTER can be provided to the PIM mode selection signal generation circuit 830.

In the PIM mode entry code, for example, the bit values of the addresses respectively corresponding to the sequential write commands WR may be set to a back-to-back address sequence, such as 0xFFFF, 0x1F1F, 0xAAFF, 0x0000, 0x1111, 0x4444, 0x3333, and 0x0000. For example, if the memory controller 112 transmits the first write command together with the first address 0xFFFF at time 1, transmits the second write command together with the second address 0x1F1F at time 2, transmits the third write command together with the third address 0xAAFF at time 3, transmits the fourth write command together with the fourth address 0x0000 at time 4, transmits the fifth write command together with the fifth address 0x1111 at time 5, and transmits the fifth write command together with the fifth address 0x0000 at time 6. At time 7, the sixth write command and the sixth address 0x4444 are transmitted together, at time 7, the seventh write command and the seventh address 0x3333 are transmitted together, and at time 8, the eighth write command and the eighth address 0x0000 are transmitted together, then the PIM mode selector 210a may interpret the reception of this sequence (i.e., the consecutive addresses) as an instruction for the PIM mode selector 210a to output the PIM mode entry signal PIM_ENTER with a logical "1". Although 8 pairs of command and address sequences are described above to send the consecutive addresses representing the PIM mode entry code, embodiments of the inventive concept are not limited thereto. For example, there may be less than 8 pairs or more than 8 pairs in alternative embodiments. Furthermore, although the above describes the use of bit values 0xFFFF, 0x1F1F, 0xAAFF, 0x0000, 0x1111, 0x4444, 0x3333, and 0x0000, embodiments of the present inventive concept are not limited thereto. For example, the bit values may have different values in alternative embodiments.

The PIM mode exit check circuit 820 can store the PIM mode exit code, compare the bit value of the address ADDR received sequentially by the PIM mode selector 210a with the bit value of the PIM mode exit code, and output the PIM mode exit signal PIM_EXIT according to the comparison result. When the bit value of the sequential address ADDR is consistent with the bit value of the PIM mode exit code, the PIM mode exit check circuit 820 can output the PIM mode exit signal PIM_EXIT with a logical "1". Otherwise, the PIM mode exit check circuit 820 can output the PIM mode exit signal PIM_EXIT with a logical "0". The PIM mode exit signal PIM_EXIT can be provided to the PIM mode selection signal generation circuit 830.

In the PIM mode exit code, for example, the bit values of the addresses respectively corresponding to the sequential write commands WR may be set to a close address sequence, such as 0x0000, 0x2F2F, 0xFFAA, 0x0000, 0x6666, 0xF2F3, 0x2333, and 0xFFFF. For example, if the memory controller 112 transmits the ninth write command together with the ninth address 0x0000 at time 9, transmits the tenth write command together with the tenth address 0x2F2F at time 10, transmits the eleventh write command together with the eleventh address 0xFFAA at time 11, transmits the twelfth write command together with the twelfth address 0x0000 at time 12, transmits the thirteenth write command together with the thirteenth address 0x6666 at time 13, and transmits the thirteenth write command together with the thirteenth address 0x6666 at time At time 14, the fourteenth write command and the fourteenth address 0xF2F3 are transmitted together, at time 15, the fifteenth write command and the fifteenth address 0x2333 are transmitted together, and at time 16, the sixteenth write command and the sixteenth address 0xFFFF are transmitted together, then the PIM mode selector 210a can interpret the reception of this sequence (i.e., the consecutive addresses) as an instruction for the PIM mode selector 210a to output the PIM mode exit signal PIM_EXIT with a logical "1". Although the above describes an 8-pair command and address sequence to send the consecutive addresses representing the PIM mode exit code, the embodiments of the present inventive concept are not limited thereto. For example, there may be less than 8 pairs or more than 8 pairs in an alternative embodiment. Furthermore, although the above describes the use of bit values 0x0000, 0x2F2F, 0xFFAA, 0x0000, 0x6666, 0xF2F3, 0x2333, and 0xFFFF, embodiments of the inventive concept are not limited thereto. For example, the bit values may have different values in alternative embodiments.

The PIM mode selection signal generating circuit 830 can generate the PIM mode selection signal PIM_SEL based on the PIM mode entry signal PIM_ENTER and the PIM mode exit signal PIM_EXIT. The PIM mode selection signal generating circuit 830 can enable the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER having a logic "1" and the PIM mode exit signal PIM_EXIT having a logic "0". By enabling the PIM mode selection signal PIM_SEL, the memory device 120 can operate in the internal processing mode.

The PIM mode selection signal generating circuit 830 may disable the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER having a logic "0" or the PIM mode exit signal PIM_EXIT having a logic "1". By disabling the PIM mode selection signal PIM_SEL, the memory device 120 may operate in a normal mode.

The PIM mode entry code and the PIM mode exit code described above with reference to FIG. 8 are merely examples, and the present inventive concept is not limited thereto. According to an embodiment of the present inventive concept, the PIM mode entry code and the PIM mode exit code may be configured in various ways. The PIM mode entry code and the PIM mode exit code may be stored in the control register 116 of the memory controller 112 and the PIM mode selector 210a according to the same code value.

FIG. 9 is a flow chart illustrating the operation of the memory device shown in FIG. 2 according to an exemplary embodiment of the inventive concept.

Referring to Figures 1, 2, 8 and 9, in operation S905, the memory device 120 sequentially receives the command CMD and the address ADDR from the memory controller 112 via the command/address signal line 132.

In operation S911, the memory device 120 compares the bit value of the sequentially received address ADDR with the bit value of the PIM mode entry code through the PIM mode entry check circuit 810 of the PIM mode selector 210a, and outputs the PIM mode entry signal PIM_ENTER according to the comparison result.

In operation S912, the memory device 120 compares the bit value of the sequentially received address ADDR with the bit value of the PIM mode exit code through the PIM mode exit check circuit 820 of the PIM mode selector 210a, and outputs the PIM mode exit signal PIM_EXIT according to the comparison result.

In operation S920, the memory device 120 generates a PIM mode selection signal PIM_SEL based on the PIM mode entry signal PIM_ENTER and the PIM mode exit signal PIM_EXIT via the PIM mode selection signal generation circuit 830 of the PIM mode selector 210a. For example, the PIM mode selection signal generation circuit 830 may enable the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER having a logic "1" and the PIM mode exit signal PIM_EXIT having a logic "0". The PIM mode selection signal generating circuit 830 may disable the PIM mode selection signal PIM_SEL in response to the PIM mode entry signal PIM_ENTER having a logic "0" or the PIM mode exit signal PIM_EXIT having a logic "1".

In operation S930, the memory device 120 determines whether to enable the PIM mode selection signal PIM_SEL generated in operation S920.

When the PIM mode selection signal PIM_SEL is enabled, the memory device 120 enters the internal processing mode in operation S940.

In operation S941, the memory device 120 converts the command CMD received in operation S920 into an internal processing operation command PIM_CMD. The PIM command converter 126 of the memory device 120 may convert the received command CMD into an internal processing operation command PIM_CMD indicating an internal processing operation type, wherein the internal processing operation type includes, for example, data search, data arithmetic operation (e.g., addition, subtraction, multiplication, division, etc.), data movement, data inversion, data shift, data exchange, data comparison, logical operation and/or data processing/operation.

In operation S942, the memory device 120 performs an internal processing operation according to the internal processing operation command PIM_CMD. The PIM engine 250 of the memory device 120 may perform the internal processing operation according to the internal processing operation command PIM_CMD by using the PIM area 122 of the memory cell array 121. The PIM engine 250 may store internal processing data in the PIM area 122, the internal processing data being the result of the internal processing operation performed in response to the internal processing operation command PIM_CMD. Alternatively, the PIM engine 250 may read the internal processing data from the PIM area 122 in response to the internal processing operation command PIM_CMD, and perform the internal processing operation based on the read internal processing data.

Meanwhile, when it is determined in operation S930 that the PIM mode selection signal PIM_SEL is disabled, in operation S950, the memory device 120 enters the normal mode.

In operation S951, the memory device 120 performs a data transaction operation according to the command CMD received in operation S905. The command CMD may be associated with a data transaction operation performed in a normal mode. The memory device 120 may store the data DQ received from the memory controller 112 via the data line 134 in the normal memory area 124 of the memory cell array 121 according to the command CMD, read the data DQ from the normal memory area 124, and transmit the read data to the memory controller 112 via the data line 134 as the data DQ.

Although the inventive concept has been particularly shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made to the inventive concept without departing from the spirit and scope of the inventive concept.

100: System

110: Host device

112:Memory controller

114: Memory physical layer interface

116: Control register

120: Memory device

121: Memory cell array

122: Processing area in memory

124: Normal memory area

126: Processing command converter in memory

130:Memory bus

132: Command/address signal line

134: Data line

ADDR: address/address signal/sequential address

CMD: Command

DQ: Data to be written/data to be read/data

PIM_CMD: Internal processing operation command

Claims (22)

A memory device comprises: a memory cell array including a first memory area and a second memory area; a signal line configured to receive a command and an address from a source outside the memory device; a mode selector circuit configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command; and a command converter circuit configured to convert the processing mode selection signal into an internal processing mode in response to activation of the processing mode selection signal. The received command is converted into an internal processing operation command; and the internal processor is configured to perform an internal processing operation on the first memory area in response to the internal processing operation command in the internal processing mode, wherein the mode selector circuit generates the processing mode selection signal in response to a specific address, the specific address is included in the address received together with the command and distinguishes the first memory area from the second memory area. A memory device as described in claim 1, wherein the signal line is connected to a memory physical layer interface, the memory physical layer interface supports a double data rate (DDR) protocol or a low power double data rate (LPDDR) protocol and the memory physical layer interface is located outside the memory device. A memory device as described in claim 1, wherein the memory cell array includes a stacked memory layer, the stacked memory layer includes a common channel, a silicon via, and an electrode pad electrically connected to the silicon via, and in the common channel, the stacked memory layer belonging to the first memory area and the stacked memory layer belonging to the second memory area are selectively accessed according to a stack identification signal, and the specific address includes the stack identification signal for accessing the stacked memory layer belonging to the first memory area. A memory device as described in claim 1, wherein the memory cell array includes a stacked memory layer, the stacked memory layer includes a common channel, a through silicon via, and an electrode pad electrically connected to the through silicon via, and in the common channel, the stacked memory layer belonging to the first memory area and the stacked memory layer belonging to the second memory area are selectively accessed according to a channel address, and the specific address includes the channel address for accessing the stacked memory layer belonging to the first memory area. A memory device as described in claim 1, wherein the memory cell array includes a plurality of memory libraries, among which the memory libraries belonging to the first memory area and the memory libraries belonging to the second memory area are selectively accessed according to the memory library addresses, and the specific address includes the memory library address for accessing the memory library belonging to the first memory area. A memory device as described in claim 1, wherein the first memory area and the second memory area are set as fixed areas by the specific address. A memory device as described in claim 1, wherein the first memory area and the second memory area are set as variable areas by the specific address. A memory device as described in claim 1, wherein when the specific address is not included in the address received together with the command, the mode selector circuit disables the processing mode selection signal to cause the memory device to enter a normal mode. A memory device as described in claim 1, wherein the memory device sequentially receives a first command via the signal line, and sequentially receives addresses corresponding to the first commands received sequentially, and the mode selector circuit determines whether the addresses received sequentially are consistent with an internal processing mode entry code and an internal processing mode exit code, and generates the processing mode selection signal based on the determination result. A memory device as described in claim 9, wherein when the sequentially received addresses are consistent with the internal processing mode entry code and the sequentially received addresses are inconsistent with the internal processing mode exit code, the mode selector circuit enables the processing mode selection signal. A memory device as described in claim 9, wherein when the sequentially received address is inconsistent with the internal processing mode entry code or the sequentially received address is consistent with the internal processing mode exit code, the mode selector circuit disables the processing mode selection signal to enable the memory device to enter normal mode. A method for operating a memory device, the memory device comprising a memory cell array and an internal processor, the memory cell array comprising a first memory area and a second memory area, the internal processor being configured to perform an internal processing operation, the method comprising: receiving a command and an address from a source outside the memory device via a predefined protocol interface; generating a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command; converting the received command into an internal processing operation command in response to activation of the processing mode selection signal; ; and in the internal processing mode, the internal processor performs an internal processing operation on the first memory area in response to the internal processing operation command, wherein generating the processing mode selection signal includes: determining whether the address received together with the command includes a specific address for distinguishing the first memory area from the second memory area; when the address received together with the command includes the specific address, enabling the processing mode selection signal; and when the address received together with the command does not include the specific address, disabling the processing mode selection signal. A method as described in claim 12, wherein the predefined protocol interface is a memory physical layer interface, and the memory physical layer interface supports a double data rate (DDR) protocol or a low power double data rate (LPDDR) protocol. The method as claimed in claim 12 further includes: entering the normal mode in response to disabling of the processing mode selection signal. A method as described in claim 12, wherein the specific address includes a stack identification signal, a channel address, and a memory bank address for addressing the first memory area. The method as described in claim 12, wherein the first memory area and the second memory area are set as fixed areas by the specific address. The method as described in claim 12, wherein the first memory area and the second memory area are set as variable areas by the specific address. The method of claim 12, wherein generating the processing mode selection signal comprises: sequentially receiving a first command via the predefined protocol interface; sequentially receiving addresses corresponding to the first commands received sequentially via the predefined protocol interface; determining whether the addresses received sequentially are consistent with an internal processing mode entry code and an internal processing mode exit code; and generating the processing mode selection signal based on the determination result. A method as described in claim 18, wherein generating the processing mode selection signal comprises: enabling the processing mode selection signal when the sequentially received address is consistent with the internal processing mode entry code and the sequentially received address is inconsistent with the internal processing mode exit code; and disabling the processing mode selection signal when the sequentially received address is inconsistent with the internal processing mode entry code or the sequentially received address is consistent with the internal processing mode exit code. The method as described in claim 19 further includes: entering the normal mode in response to disabling of the processing mode selection signal. A memory system comprises: a memory device; and a memory controller configured to control the memory device using a predefined protocol interface connected to the memory device, wherein the memory device comprises: a memory cell array including a first memory area and a second memory area; a mode selector circuit configured to receive a command and an address from the memory controller via the predefined protocol interface, and based on the address received together with the command, generate a processing mode selection signal for controlling the memory device to enter an internal processing mode; A command converter circuit is configured to convert the received command into an internal processing operation command in response to the activation of the processing mode selection signal; and an internal processor is configured to perform an internal processing operation on the first memory area in response to the internal processing operation command in the internal processing mode, wherein the mode selector circuit generates the processing mode selection signal in response to a specific address, the specific address is included in the address received together with the command and distinguishes the first memory area from the second memory area. A memory system as described in claim 21, wherein the predefined protocol interface is a memory physical layer interface, and the memory physical layer interface is a double data rate (DDR) protocol or a low power double data rate (LPDDR) protocol.

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