TWI858642B - Automatic motherboard testing system - Google Patents

Abstract

An automatic motherboard testing system is suitable for electrically connecting a debugging host. The main technology includes a motherboard and a signal branching module. The first circuit and the second circuit of the motherboard are used to provide the first and second debugging data respectively. For the second debugging data, the transmission module is electrically connected to the first circuit and the second circuit, and has a VGA connector, and the VGA connector has at least one idle pin, and the transmission module is used for communicating the first debugging data with the second circuit. One of the second debugging data is output from an idle pin of the VGA connector as a data to be tested. The signal splitting module is electrically connected to the idle pin of the VGA connector and the debugging host to receive the data to be tested from the idle pin, and convert the signal format of the data to be tested.

Description

Automated Motherboard Test System

The present invention relates to a debugging technology, and more particularly to an automated motherboard testing system.

In the current motherboard development stage, before it is shipped to customers, some debugging components, such as debugging pins, will be installed on the motherboard. When the development is completed, the debugging pins on the motherboard will be removed first, and the motherboard will be shipped to customers after the pre-shipment test is completed. Whether it is during the pre-shipment test or after the shipment, if the motherboard has a problem and needs to be debugged again, the debugging pins used in the initial development stage have been removed. Therefore, the existing motherboard debugging technology is as shown in FIG1. The motherboard must be removed from the server machine to expose the internal components, such as the baseboard manager (hereinafter referred to as BMC) 11, the programmable logic device (CPLD) 12, and the digital timer (retimer) 13. The components can be seen by the tester, and then the BMC 11, CPLD 12, and retimer 13 are tested one by one by using an external instrument through a probe 14, resulting in the following disadvantages:

Disadvantage 1: If the client is overseas, the motherboard must be removed from the machine, and the shipping cost from the client to the original manufacturer is a waste of manpower, time and money. Even if it has not yet been shipped, as long as the debugging pins are removed, the motherboard can only be removed and debugged using a probe. Disadvantage 2: Some pins of the motherboard's Video Graphics Array (VGA) connector are not fully utilized. They are idle pins that do not transmit image signals (also called empty pins), resulting in low overall pin utilization of the VGA connector.

Therefore, an object of the present invention is to provide an automated motherboard testing system that can overcome the disadvantages of the prior art that the motherboard must be removed from the machine.

Therefore, the automated motherboard test system is suitable for electrically connecting a debugging host, including a motherboard and a signal splitter module.

The motherboard includes a first circuit for providing a first debug data, a second circuit for providing a second debug data, and a transmission module. The transmission module electrically connects the first circuit and the second circuit and has a VGA connector. The VGA connector has at least one idle pin. The transmission module is used to output one of the first debug data and the second debug data from the idle pin of the VGA connector as data to be detected.

The signal splitter module is electrically connected to the idle pin of the VGA connector and the debugging host to receive the data to be detected from the idle pin, convert the data to be detected into a signal format, and transmit the data to the debugging host.

The effect of the present invention is that the idle pins of the VGA connector are used in conjunction with the split cable to provide a transmission path for debugging data, so as to connect the debugging host of the tester with the motherboard that needs to be debugged without removing the motherboard from the machine, thereby reducing costs and time.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

Referring to FIG. 2 , an embodiment of the automated motherboard test system of the present invention is shown, which is suitable for electrically connecting a screen 2 and a debugging host 3 , and includes a motherboard 4 , a signal splitter module 30 , and an input interface 49 electrically connected to the motherboard 4 .

The motherboard 4 includes a first circuit 41 for providing a first debug data, a second circuit 42 for providing a second debug data, a third circuit 43 for providing a third debug data, and a transmission module 44. The transmission module 44 includes a line switch 5, a video graphics array (VGA) connector 6 having at least one idle pin, and a chip control group 7 electrically connected to the line switch 5. The chip control group 7 includes a platform controller hub (PCH) 71 and a processor (CPU) 72.

The first circuit 41 has a baseboard management controller (BMC) 411. The second circuit 42 has a complex programmable logic device (CPLD) 421. The third circuit 43 has a digital retimer 431.

The transmission module 44 is electrically connected to the first circuit 41, the second circuit 42 and the third circuit 43, and is used to output one of the first debugging data, the second debugging data and the third debugging data from the idle pin of the VGA connector 6 to be transmitted as a data to be detected to the signal splitter module 30. When the signal splitter module 30 transmits the debugging data, the screen 2 still retains the original function of displaying the debugging data on the screen, and can execute the screen function according to the original design, and display the debugging data in conjunction with the command.

The line switch 5 has a first terminal 51 electrically connected to the first circuit 41 to receive the first debug data, a second terminal 52 electrically connected to the second circuit 42 to receive the second debug data, a third terminal 53 electrically connected to the third circuit 43 to receive the third debug data, a total transceiver terminal 54, and a control terminal 55 receiving a switching signal. The line switch 5 determines, according to the control of the switching signal, whether one of the first terminal 51, the second terminal 52 and the third terminal 53 is connected to the total transceiver terminal 54, and outputs one of the first debug data, the second debug data and the third debug data from the total transceiver terminal 54 as a data to be detected. To further explain, when the computer is turned on and the CPU executes the BIOS, if a password input command (key debug) is received from an input interface 49 and indicates entering a debug menu, the BIOS will enter the debug menu, and you can choose to read the debug data file (debug log) stored in one of the BMC/CPLD/Retimer, and generate the switching signal. If the BMC is selected, the switching signal connects the first end 51 to the total transceiver end 54. If the CPLD is selected, the switching signal connects the second end 52 to the total transceiver end 54. If the Retimer is selected, the switching signal connects the third end 53 to the total transceiver end 54.

When the line switch 5 connects the first end 51 to the total transceiver end 54 according to the switching signal, the second end 52 is not connected to the total transceiver end 54, and the first circuit 41 generates the first debugging data according to a file acquisition command from the debugging host 3. The file acquisition command is sequentially transmitted to the first circuit 41 via the signal splitter module 30, the VGA connector 6, the total transceiver end 54 of the line switch 5 to the first end 51.

When the line switch 5 connects the second end 52 to the main transceiver end 54 according to the switching signal, the first end 51 is not connected to the main transceiver end 54, and the second circuit 42 generates the second debugging data according to a file request command from the debugging host 3. The file request command is sequentially transmitted to the second circuit 42 via the signal splitter module 30, the VGA connector 6, the main transceiver end 54 of the line switch 5 to the second end 52.

Here, the connection methods of BMC, CPLD, Retimer and line switch are further described. BMC is connected to the first end 51 of the line switch 5 via a data transmission line (hereinafter referred to as TXD) 511 and a data receiving line (hereinafter referred to as RXD) 512. TXD511 is used to unidirectionally transmit the first debugging data from BMC411 to the first end of the line switch 5, and RXD512 is used to unidirectionally transmit the signal from the first end of the line switch 5 to BMC411. Referring to FIG. 2 , for example, for BMC411, the file request command from the debug host 3 is transmitted to BMC411 via RXD512, and BMC411 provides the first debug data to be transmitted to the debug host 3 via TXD511. After receiving the first debug data, the debug host 3 transmits a confirmation signal indicating that the data is received correctly to BMC411 via RXD512.

CPLD421 is connected to the second end 52 of the line switch 5 via a first serial data line (hereinafter referred to as the first SDA) 521 and a first serial clock line (hereinafter referred to as the first SCL) 522. The first SDA 521 is used to transmit data bidirectionally between CPLD421 and the second end 52 of the line switch 5, and the first SCL 522 is used to transmit a clock signal (clock) to the line switch 5. Retimer431 is connected to the third end 53 of the line switch 5 via a second serial data line (hereinafter referred to as the second SDA) 531 and a second serial clock line (hereinafter referred to as the second SCL) 532. The second SDA 531 is used to transmit data bidirectionally between Retimer431 and the third end 53 of the line switch 5.

Referring to FIG. 3 , which is a diagram of the external connection structure of the VGA connector 6 , the VGA connector 6 has an external pin set 61 and an internal pin set 62 correspondingly connected to the external pin set 61 . As shown in FIG. 4 , the external pin set 61 includes a plurality of external pins (hereinafter referred to as pin1 to pin15 ), wherein pins 4 , 9 , and 11 of some of the external pins are idle pins, and pins 1 to 3 , 5 to 8 , 10 , and 12 to 15 of the other pins (hereinafter referred to as other pins ) are non-idle pins for transmitting image signals.

The inner pin group 62 includes a plurality of inner pins (hereinafter referred to as pin1'~pin15'). A portion of the inner pins (pin4', pin9') are electrically connected to the total transceiver end of the line switch to receive the data to be detected and transmit to the idle pins (pin4, pin9). The inner pins pin4', pin9', pin11' correspond to the external pins pin4, pin9, pin11 respectively, wherein pin11' is grounded, and the other portions of the inner pins pin1'~pin3', pin5'~pin8', pin10', pin12'~pin15' correspond to the external pins pin1~pin3, pin5~pin8', pin10, pin12~pin15 respectively. The connection correspondence of each component of the motherboard is shown in Table 1~Table 3:

Table 1, when the first terminal 51 is electrically connected to the main transceiver terminal 54. Inner pin pin4' pin9' External pin pin4 pin9 BMC TXD RxD

Table 2, when the second terminal 52 is electrically connected to the main transceiver terminal 54. Inner pin pin4' pin9' External pin pin4 pin9 CLPD First SDA First SCL

Table 3, when the third terminal 53 is electrically connected to the main transceiver terminal 54. Inner pin pin4' pin9' External pin pin4 pin9 Retimer Second SDA Second SCL

The signal splitter module 3 electrically connects the VGA connector 6 and the debug host 3 to transmit the data to be detected to the debug host 3, and includes a splitter cable 31 and an adapter board 32. The splitter cable 31 has a first cable segment A electrically connected to the external pin set 61, a second cable segment B electrically connected to the first cable segment A and a screen 2, and a third cable segment C electrically connected to the first cable segment A to correspond to the transmission of the data to be detected from the internal pins (pin4', pin9'). The first cable segment A is used to transmit signals corresponding to pins 1 to 15, that is, image signals and data to be detected. The second cable segment B is used to transmit signals corresponding to other pins, and transmits the image signal from the first cable segment A to the screen 2. The third cable segment C is used to transmit signals corresponding to pins 4, pin 9, and pin 11, and transmits the data to be detected from the first cable segment A to the adapter board 32.

The adapter board 32 is electrically connected between the third cable segment C and the debugging host 3 to convert the signal format of the data to be detected to generate a detection output, which is analyzed by the debugging host 3. The adapter board 32 has a first switch 81 electrically connected to the third cable segment C, a first converter 84, a second converter 85, a second switch 82, and a switch controller 83.

The first switch 81 has a first end 811 electrically connected to the third cable segment C, a second end 812, a third end 813, and a control end for receiving a control signal. The first switch 81 selects one of the second end 812 and the third end 813 to switch between conduction and non-conduction with the first end 811 according to the control signal. When the first end 811 and the second end 812 are conductive, there is no conduction between the first end 811 and the third end 813. When the first end 811 and the third end 813 are conductive, there is no conduction between the first end 811 and the second end 812. In this embodiment, the first end 811 of the first switch 81 has a first line TX and a second line RX, and the first line TX and the second line RX of the first end 811 are electrically connected to the lines corresponding to the idle pins pin4 and pin 9 in the third cable segment C respectively; the second end 812 of the first switch 81 has a first line TX' and a second line RX', which correspond to the first line TX and the second line RX of the first end 811 respectively; the third end 813 of the first switch 81 has a first line SDA' and a second line SCL', which correspond to the first line TX and the second line RX of the first end 811 respectively.

The second switch 82 has a first end 821 electrically connected to the debugging host 3, a second end 822, a third end 823, and a control end for receiving the control signal. The second switch 82 selects one of the second end 822 and the third end 823 to switch between conduction and non-conduction with the first end 821 according to the control signal. When the first end 821 and the second end 822 are conductive, there is no conduction between the first end 821 and the third end 823. When the first end 821 and the third end 823 are conductive, there is no conduction between the first end 821 and the second end 822.

The first converter 84 is electrically connected between the second end 812 of the first switch 81 and the second end 822 of the second switch 82, and is used for converting the format of the received signal. In this embodiment, the first converter 84 is a CP2105 chip, which corresponds to converting the signal format of the first debug data from the BMC411 of the main board 4 (UART TX/RX format to USB format).

The second converter 85 is electrically connected between the third end 813 of the first switch 81 and the third end 823 of the second switch 82, and is used for converting the format of the received signal. In this embodiment, the second converter 85 is a CY8C24894 chip, which corresponds to converting the signal format of the second debug data/third debug data from the CPLD421/Retimer431 of the main board 4 (SMBUS format to USB format).

The switch controller 83 is electrically connected to the control terminals of the first switch 81 and the second switch 82 to generate the control signal. When the first debug data of the BMC411 of the motherboard 4 is selected to be read, the control signal is used to set the first terminals 811 and 821 of the first switch 81 and the second switch 82 to be connected to the second terminals 812 and 822 thereof, respectively. Referring to FIG. 2 and FIG. 5 , the transmission path of the first debug data is from the BMC411, TXD511, from the first terminal 51 of the line switch 5 to the total transceiver terminal 54, the pin 4' of the inner pin group 62, Pin 4 of the external pin set 61, the first cable segment A, the third cable segment C, the first line TX from the first end 811 of the first switch 81 to the first line TX' from the second end 812, the first converter 84, the second end 822 to the first end 821 of the second switch 82, and the debugging host 3.

When the second debug data of the CPLD of the motherboard 4 is selected to be read, the control signal is used to set the first ends 811 and 821 of the first switch 81 and the second switch 82 to be connected to the third ends 813 and 823 respectively, and the transmission path of the second debug data is from CPLD421, SDA521, from the second end 52 of the line switch 5 to the total transceiver end 54, pin4' of the inner pin group 62, pin4 of the outer pin group 61, the first cable segment A, the third cable segment C, the first line TX of the first end 811 of the first switch 81 to the first line SDA' of the third end 813, the second converter 85, the third end 823 of the second switch 82 to the first end 821, and the debug host 3.

In summary, the above embodiment has the following advantages: 1. The idle pins (pin 4, pin 9) of the VGA connector 6 are used in conjunction with the branch cable 51 and the adapter plate 52 to provide a transmission path for debugging data, so that the debugging host of the tester can be connected to the motherboard that needs to be debugged without removing the motherboard from the machine, thereby reducing costs and time. 2. The idle pins that do not transmit image signals are used to transmit debugging data, thereby improving the overall pin utilization rate of the VGA connector.

However, the above is only an embodiment of the present invention and should not be used to limit the scope of implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the present patent.

2: Screen 3: Debug host 30: Signal splitter module 31: Split cable 32: Adapter board A: First cable segment B: Second cable segment C: Third cable segment 4: Mainboard 41: First circuit 411: Baseboard manager 42: Second circuit 421: Complex programmable logic device 43: Third circuit 431: Digital timer 44: Transmission module 49: Input interface 5: Line switch 51: First end 52: Second end 53: Third end 54: Total transceiver 55: Control end 511: Data transmission line 512: Data receiving line 521: First serial data line 522: First serial clock line 531: Second serial data line 532: Second serial clock line 6: VGA connector 61: External pin set 62: Internal pin set 7: Chip control set 71: Platform path controller 72: Processor 81: First switch 811: First end 812: Second end 813: Third end 82: Second switch 821: First end 822: Second end 823: Third end 83: Switch controller 84: First converter 85: Second converter TX: First line RX: Second line SDA’: First line SCL’: Second line TX’: First line RX’: Second line

Other features and effects of the present invention will be clearly presented in the implementation method with reference to the drawings, in which: Figure 1 is a diagram of a motherboard test system of the prior art; and Figure 2 is a system diagram of an embodiment of the automated motherboard test system of the present invention; Figure 3 is a diagram of the external connection structure of the VGA connector; Figure 4 is a schematic diagram of the external pins; and Figure 5 is a system diagram of the adapter board of the present embodiment.

2: Screen

3: Debug host

30:Signal splitter module

31: Branch cable

32: Adapter board

A: First cable segment

B: Second cable segment

C: The third cable segment

4: Motherboard

41: First circuit

42: Second circuit

43: The third circuit

44: Transmission module

49: Input interface

5: Line switch

6: VGA connector

61: External pin set

62: Inner pin set

Claims (8)

An automated motherboard test system, suitable for electrically connecting to a debugging host, comprises: a motherboard, including a first circuit for providing a first debugging data, a second circuit for providing a second debugging data, and a transmission module, the transmission module electrically connecting the first circuit and the second circuit, and having a VGA connector, the VGA connector having at least one idle pin, the transmission module being used to output one of the first debugging data and the second debugging data from the idle pin of the VGA connector as a data to be tested; a signal splitter module electrically connecting the VGA connector to the first circuit; a signal splitter module electrically connecting the VGA connector to the second ... The idle pin of the VGA connector and the debugging host are connected to receive the data to be tested from the idle pin, and the data to be tested is converted into a signal format and transmitted to the debugging host. The signal branching module includes a branching cable and an adapter board. The branching cable has a first cable segment electrically connected to the VGA connector, a second cable segment electrically connected to the first cable segment and a screen, and a third cable segment electrically connected to the first cable segment to transmit the data to be tested from the idle pin. The adapter board is electrically connected between the third cable segment and the debugging host to convert the data to be tested to the VGA connector. The signal format of the data to be tested is converted to generate a test output, which is analyzed by the debugging host. The adapter board has a first switch, a first converter, a second converter, a second switch, and a switch controller. The first switch has a first end electrically connected to the third cable segment, a second end, a third end, and a control end receiving a control signal. The first switch selects one of the second end and the third end to switch between the first end and the non-conduction state according to the control signal. The second switch has a first end electrically connected to the debugging host, a second end, and a control end receiving a control signal. , a third end, and a control end for receiving the control signal. The second switch selects one of the second end and the third end to switch between the first end and the first end to be conductive or non-conductive according to the control signal. The first converter is electrically connected between the second end of the first switch and the second end of the second switch to convert the format of the received signal. The second converter is electrically connected between the third end of the first switch and the third end of the second switch to convert the format of the received signal. The switch controller is electrically connected between the control ends of the first switch and the second switch to generate the control signal. The automated motherboard test system as described in claim 1, wherein the transmission module further includes a line switch, the line switch having a first end electrically connected to the first circuit to receive the first debug data, a second end electrically connected to the second circuit to receive the second debug data, a general transceiver end electrically connected to the VGA connector, and a control end receiving a switching signal, the line switch determines one of the first end and the second end to be connected to the general transceiver end according to the control of the switching signal, and outputs one of the first debug data and the second debug data as the data to be tested from the general transceiver end to the VGA connector. The automated motherboard test system as described in claim 1, wherein the transmission module further includes a chip control group electrically connected to the line switch, and when the chip control group receives a password input command indicating entering a debug menu, the chip control group generates the switching signal. In the automated motherboard test system as described in claim 1, when the line switch connects the first end to the total transceiver end according to the switching signal, the second end is not connected to the total transceiver end, and the first circuit generates the first debugging data according to a file request command from the debugging host, wherein the file request command is sequentially transmitted to the first circuit via the signal splitter module, the VGA connector, the total transceiver end of the line switch to the first end. The automated motherboard test system as described in claim 1, wherein when the line switch connects the second end to the total transceiver end according to the switching signal, the first end is not connected to the total transceiver end, and the second circuit generates the second debugging data according to a file request command from the debugging host, and the file request command is sequentially transmitted to the second circuit via the signal splitter module, the VGA connector, the total transceiver end of the line switch to the second end. An automated motherboard testing system as described in claim 1, wherein the first circuit has a substrate manager. An automated motherboard testing system as described in claim 1, wherein the second circuit has a complex programmable logic device. The automated motherboard test system as described in claim 1, wherein the VGA connector has an external pin set electrically connected to the debug host and an internal pin set correspondingly connected to the external pin set, the external pin set has a plurality of external pins, and the internal pin set has a plurality of internal pins, wherein a portion of the external pins are the idle pins, and a portion of the internal pins are electrically connected to the total transceiver end of the line switch to receive the data to be tested and transmit it to the idle pins.

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