TWI855786B - Memory device and pre-charge method - Google Patents

Abstract

Provided are a memory device and a pre-charge method for a memory device. The pre-charge method includes: applying a plurality of independently-controlled pre-charge voltages to a plurality of turned-on word lines, wherein the plurality of pre-charge voltages are selected among a plurality of reference pre-charge voltages; and applying a plurality of turned-off voltages to a plurality of turned-off word lines. On a predetermined direction, a target turned-on word line among the plurality of turned-on word lines is adjacent to a next adjacent target turned-off word line among the plurality of turned-off word lines; and a voltage difference from the target turned-on word line toward the next adjacent target turned-off word line is smaller than a predetermined reference voltage difference.

Description

Memory device and pre-charging method thereof

The present invention relates to a memory device and a pre-charging method thereof.

As the storage density of memory devices increases, how to obtain a better read window becomes increasingly important. Program disturbance is a factor that affects the read window. Excessive write voltage, insufficient boosting channel at the inhibit cell, or abrupt slope of the boosting channel may reduce the read window, thereby affecting the performance of the memory device.

The sudden drop in channel potential may cause hot carrier injection (HE) effect, resulting in a smaller read window. In the current pre-charge method, the same voltage is applied to the word lines to be pre-charged. If the voltage difference between the adjacent pre-charged on word lines and pre-charged off word lines is too large, it will cause hot carrier injection effect, resulting in a smaller read window.

FIG. 1 shows the hot carrier injection effect of the prior art. In FIG. 1, CSL represents a common source line, GSL represents a global source line, SSL represents a string select line, and BL represents a bit line. As shown in FIG. 1, in the precharge stage, the word lines WL0, WL4, WL5, ... are turned off; and the word lines WL1, WL2, and WL3 are turned on. Here, for example, the turn-off voltage applied to the word lines WL0, WL4, WL5, ... is 0V, and the turn-on voltage applied to the word lines WL1, WL2, and WL3 is 4.5V. In this assumption, word lines WL0-WL3 are all in the erase state (eR) (with the lowest critical voltage), while word lines WL4 and WL5 are in state G (with the highest critical voltage). At the junction of word lines WL3 and WL4, the voltage difference is 4.5-0=4.5V. This large voltage difference will lead to hot carrier injection effect, thereby reducing the read window, causing programming interference, and affecting the performance of the memory device.

Therefore, the industry strives to avoid the hot carrier injection effect to obtain a better read window and thus increase the performance of memory devices.

According to one aspect of the present invention, a precharging method for a memory device is provided, comprising: applying a plurality of independently controlled precharging voltages to a plurality of on word lines, the precharging voltages being selected from a plurality of reference precharging voltages; and applying a plurality of off voltages to a plurality of off word lines, wherein, in a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; and a voltage difference from the target on word line to the next adjacent target off word line is less than a given reference voltage difference.

According to another aspect of the present invention, a memory device is provided, comprising: a memory array; a drive circuit coupled to and driving the memory array; and a memory control circuit coupled to and controlling the drive circuit. In a precharge phase, under the control of the memory control circuit, the drive circuit applies a plurality of independently controlled precharge voltages to a plurality of on word lines of the memory array, the precharge voltages being selected from a plurality of reference precharge voltages; and under the control of the memory control circuit, the drive circuit applies a plurality of off voltages to a plurality of off word lines of the memory array. In a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; and a voltage difference from the target on word line to the next adjacent target off word line is less than a given reference voltage difference.

In order to better understand the above and other aspects of the present invention, the following is a specific example and a detailed description with the attached drawings as follows:

CSL: Common Source Line

GSL: Global Source Line

SSL: string selection line

BL: Bit Line

WL0~WL5, WLN-4~WLN+4: character line

500: Memory device

510: Memory control circuit

520:Drive circuit

530:Memory array

610, 620: Steps

Figure 1 shows the hot carrier injection effect of the conventional technology.

Figure 2 shows an operation waveform diagram of a memory device according to an embodiment of the present invention.

Figures 3A to 3D show schematic diagrams of the operation of the pre-charging stage according to an embodiment of the present invention.

Figures 4A to 4E show schematic diagrams of the operation of the pre-charging stage according to an embodiment of the present invention.

Figure 5 shows a functional block diagram of a memory device according to an embodiment of the present invention.

Figure 6 shows a flow chart of a pre-charging method for a memory device according to an embodiment of the present invention.

The technical terms in this manual refer to the customary terms in this technical field. If this manual explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this manual. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 2 shows an operation waveform diagram of a memory device according to an embodiment of the present invention. FIG. 2 shows several word lines WL0-WL5, but it should be noted that the present invention is not limited to this. Below, an example is given of turning on word lines WL1-WL3 and turning off other word lines WL0, WL4, etc. during the pre-charge stage, but it should be noted that the present invention is not limited to this. It is assumed here that word lines WL0-WL3 are all in the erase state (eR), while word lines WL4 and WL5 are in state G (with the highest critical voltage). It is assumed here that word line WL2 is to be programmed, but it should be noted that the present invention is not limited to this. The turn-off voltage applied to word lines WL0, WL4, WL5, etc. is 0V, but it should be noted that the present invention is not limited to this. In the following, in the pre-charge stage, the word lines that are turned on (such as WL1-WL3, etc.) can also be called "on word lines"; and the word lines that are turned off (such as WL0, WL4, etc.) can also be called "off word lines". In the pre-charge stage, the common source line CSL and the global source line GSL are turned on, and the string selection line SSL is turned off, and the bit line BL is turned on (disabled string) or off (non-disabled string) depending on whether it is a prohibited string.

As shown in FIG. 2, in the pre-charge stage, for example but not limited to, the pre-charge voltages applied to the turned-on word lines WL1-WL3 are 4.5V, 4.5V and 3V respectively. At the junction of word lines WL3 (turned on and having the lowest critical voltage) and WL4 (turned off and having the highest critical voltage), the voltage difference is 3-0=3V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, so that the performance of the memory device is less affected. In addition, in FIG. 2, the voltage of the common source line CSL decreases in a step-like manner at the junction of the word line WL3 (turned on and having the lowest critical voltage) and WL4 (turned off and having the highest critical voltage). Thus, the embodiment of the present case can reduce the hot carrier injection effect as in the prior art.

In the programming stage, the programming voltage VPGM is applied to the word line WL2, and the pass voltage VPASS is applied to other word lines WL0-WL1, WL3-WL5... In the programming stage, the common source line CSL is turned on, while the global source line GSL and the string selection line SSL are turned off, and the bit line BL is turned on (disabled string) or off (non-disabled string) depending on whether it is a prohibited string.

In other embodiments of the present invention, during the pre-charging stage, the pre-charging voltage applied to the conductive word lines can have more variations and is not limited to FIG. 2. Some examples will be described below, but it should be noted that the present invention is not limited thereto.

FIG. 3A to FIG. 3D are schematic diagrams showing the operation of the pre-charge stage according to an embodiment of the present invention. As shown in FIG. 3A, in the pre-charge stage, for example but not limited to, the pre-charge voltages applied to the turned-on word lines WL1-WL3 are respectively a high reference pre-charge voltage HV, a medium reference pre-charge voltage MV and a low reference pre-charge voltage LV, wherein HV>MV>LV. As shown in Figure 3A, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is LV-0=LV. This voltage difference is smaller (that is, the voltage difference is smaller than a given reference voltage difference), which will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected. In one embodiment of the present case, the target on word line is defined as the on word line adjacent to the off word line in a given direction; and the target off word line is defined as the off word line adjacent to the on word line in a given direction. In one embodiment of the present case, the given direction is from the common source line CSL to the bit line BL. The given reference voltage difference is related to a voltage difference between a high reference pre-charge voltage HV and a low reference pre-charge voltage LV. In one example, the given reference voltage difference is equal to a voltage difference between a high reference pre-charge voltage HV and a low reference pre-charge voltage LV.

As shown in FIG. 3B , in the pre-charge stage, for example but not limited to, the pre-charge voltages applied to the turned-on word lines WL1 - WL3 are respectively a high reference pre-charge voltage HV, a high reference pre-charge voltage HV, and a medium reference pre-charge voltage MV. As shown in Figure 3B, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

As shown in FIG. 3C , in the pre-charge stage, for example but not limited to, the pre-charge voltages applied to the turned-on word lines WL1 - WL3 are respectively a high reference pre-charge voltage HV, a medium reference pre-charge voltage MV, and a medium reference pre-charge voltage MV. As shown in Figure 3C, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. The smaller the voltage difference, the less likely the hot carrier injection effect will occur, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

As shown in FIG. 3D , in the pre-charge stage, for example but not limited to, the pre-charge voltages applied to the turned-on word lines WL1 - WL3 are respectively a high reference pre-charge voltage HV, a low reference pre-charge voltage LV, and a medium reference pre-charge voltage MV. As shown in Figure 3D, at the junction of the on word line WL3 (also called the "target on word line") and the next adjacent off word line WL4 (also called the target off word line), the voltage difference is MV-0=MV. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

This case can also have other different pre-charge voltages. For the convenience of explanation, they are organized into the following Table 1 for explanation. Of course, this case is not limited to this. Those who are familiar with this technology can infer other types of pre-charge voltage settings from the embodiments of this case, which are all within the spirit of this case.

From Table 1 above, the precharge voltage applied to the target conductive word line (such as word line WL3 in FIG. 3A) can be the medium reference precharge voltage MV or the low reference precharge voltage LV, and the precharge voltage applied to the non-target conductive word line (such as word line WL1 or WL2 in FIG. 3A) can be the high reference precharge voltage HV, the medium reference precharge voltage MV or the low reference precharge voltage LV.

In an embodiment of the present case, the setting values of the high reference pre-charge voltage HV, the medium reference pre-charge voltage MV and the low reference pre-charge voltage LV are, for example but not limited to, 2~5V, 1~4V and 0~3V.

FIG. 4A to FIG. 4E are schematic diagrams showing the operation of the pre-charge stage according to an embodiment of the present invention. As shown in FIG. 4A, in the pre-charge stage, for example but not limited to, at least 7 word lines WLN-3 to WLN+3 are turned on, and the remaining word lines are turned off. The pre-charge voltages applied to the turned-on word lines WLN-3 to WLN+3 are 6V, 6V, 5V, 4V, 3V, 2V and 2V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. As shown in Figure 4A, at the junction of the on word line WLN+3 (target on word line) and the next adjacent off word line WIN+4 (i.e., target off word line), the voltage difference is 2V-0=2V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

As shown in FIG. 4B , in the pre-charge stage, for example but not limited to, at least 6 word lines WLN-3 to WLN+2 are turned on, and the remaining word lines are turned off. The pre-charge voltages applied to the turned-on word lines WLN-3 to WLN+2 are 6V, 6V, 5V, 4V, 3V, and 3V, respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. As shown in Figure 4B, at the junction of the on word line WLN+2 (i.e., the target on word line) and the next adjacent off word line WLN+3 (i.e., the target off word line), the voltage difference is 3V-0=3V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

As shown in FIG. 4C , in the pre-charge stage, for example but not limited to, at least four word lines WLN-3 to WLN are turned on, and the remaining word lines are turned off. The pre-charge voltages applied to the turned-on word lines WLN-3 to WLN are 6V, 6V, 5V, and 4V, respectively. It should be noted that these voltage values are only used for example, and the present invention is not limited thereto. As shown in Figure 4C, at the junction of the on word line WLN (i.e., the target on word line) and the next adjacent off word line WLN+1 (i.e., the target off word line), the voltage difference is 4V-0=4V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the read window and the impact of programming interference, making the performance of the memory device less affected.

As shown in FIG. 4D, in the pre-charge stage, for example but not limited to, at least 6 word lines WLN-3~WLN, WLN+2 and WLN+4 are turned on, and the remaining word lines are turned off. The pre-charge voltages applied to the turned-on word lines WLN-3~WLN, WLN+2 and WLN+4 are 6V, 6V, 5V, 4V, 3V and 2V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. As shown in FIG. 4D , at the junction of the turn-on word line WLN (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+1 (i.e., the target turn-off word line), the voltage difference is 4V-0=4V; at the junction of the turn-on word line WLN+2 (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+3 (i.e., the target turn-off word line), the voltage difference is 3V-0=3V; and, at the junction of the turn-on word line WLN+4 (i.e., the target turn-on word line) and the next adjacent turn-off word line WLN+5 (i.e., the target turn-off word line), the voltage difference is 2V-0=2V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the shrinkage of the read window and the impact of programming interference, making the performance of the memory device less affected. In Figure 4D, the closed word lines can be interspersed between the turned-on word lines, which is also within the spirit of the present invention.

As shown in FIG. 4E, in the pre-charge stage, for example but not limited to, at least 7 word lines WLN-3 to WLN+3 are turned on, and the remaining word lines are turned off. The pre-charge voltages applied to the turned-on word lines WLN-3 to WLN+3 are 2~5V, 2~5V, 1~4V, 1~4V, 0~3V, 0~3V and 0~3V respectively. It should be noted that these voltage values are only used for examples, and the present invention is not limited thereto. As shown in FIG. 4E, at the junction of the turned-on word line WLN+3 (i.e., the target turned-on word line) and the next adjacent turned-off word line WLN+4 (i.e., the target turned-off word line), the voltage difference is (0~3V)-0=0~3V. This smaller voltage difference will reduce the occurrence of hot carrier injection effect, thereby reducing the reduction of the reading window and the impact of programming interference, making the performance of the memory device less affected.

As can be seen from the above, in one embodiment of the present case, in order to reduce the hot carrier injection effect, in the pre-charge stage, (1) in a given direction, the voltage difference from the conductive word line to the next adjacent closed word line should be avoided to be too large. From Figure 2, Figures 3A to 3D, and Figures 4A to 4E, the given direction refers to the direction from the common source line CSL to the bit line BL. (2) The pre-charge voltage applied to the conductive word lines can be set in a variety of different ways (not limited to those shown in Table 1).

FIG. 5 shows a functional block diagram of a memory device according to an embodiment of the present invention. As shown in FIG. 5 , a memory device 500 according to an embodiment of the present invention includes a memory control circuit 510, a drive circuit 520, and a memory array 530. The memory control circuit 510 is coupled to and controls the drive circuit 520, and the drive circuit 520 is coupled to and drives the memory array 530. Under the control of the memory control circuit 510, in the pre-charging stage and the programming stage, the driving circuit 520 can output a driving voltage (such as the pre-charging voltage, programming voltage VPGM, pass voltage VPASS, etc. in the above figure) to drive the memory array 530 for pre-charging and programming.

FIG. 6 shows a flow chart of a precharge method for a memory device according to an embodiment of the present invention. In step 610, a plurality of independently controlled precharge voltages are applied to a plurality of on word lines, and the precharge voltages are selected from a plurality of reference precharge voltages. In step 620, a plurality of off voltages are applied to a plurality of off word lines, wherein, in a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; and a voltage difference from the target on word line to the next adjacent target off word line is less than a given reference voltage difference.

The above embodiments of the present case can be applied to a two-dimensional (2D) memory device or a three-dimensional (3D) memory device. In addition, the above embodiments of the present case can be applied to a single-bit cell (SLC) memory device, a multi-bit cell (MLC) memory device, a triple-bit cell (TLC) memory device, a quad-bit cell (QLC) memory device, etc.

In the above-mentioned embodiment of the present case, the pre-charging method can improve programming interference because it avoids a large voltage difference between adjacent word lines to avoid hot carrier injection effects, thereby obtaining a larger read window.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

610-620: Steps

Claims (8)

A precharge method for a memory device includes: applying a plurality of independently controlled precharge voltages to a plurality of on word lines, the precharge voltages being selected from a plurality of reference precharge voltages; and applying a plurality of off voltages to a plurality of off word lines, wherein, in a given direction, a target on word line of the on word lines is adjacent to the off word lines. A next adjacent target closed word line of a word line; and a voltage difference from the target turned-on word line to the next adjacent target turned-off word line is less than a predetermined reference voltage difference, wherein the predetermined reference voltage difference is related to a voltage difference between a highest reference pre-charge voltage of the reference pre-charge voltages and a lowest reference pre-charge voltage of the reference pre-charge voltages. A precharging method for a memory device as described in claim 1, wherein the predetermined direction is from a common source line to a bit line; and a voltage of the common source line decreases at a junction of the target on word line and the next adjacent target off word line. A precharge method for a memory device as described in claim 1, wherein the precharge voltage applied to one non-target conductive word line of the conductive word lines is a first reference precharge voltage, a second reference precharge voltage, or a third reference precharge voltage, the first reference precharge voltage is higher than the second reference precharge voltage, and the second reference precharge voltage is higher than the third reference precharge voltage; and the precharge voltage applied to the at least one target conductive word line is the second reference precharge voltage or the third reference precharge voltage. A precharging method for a memory device as described in claim 1, wherein one of the closed word lines is interspersed between the turned-on word lines. A memory device includes: a memory array; a drive circuit coupled to and driving the memory array; and a memory control circuit coupled to and controlling the drive circuit; wherein, in a pre-charge phase, under the control of the memory control circuit, the drive circuit applies a plurality of independently controlled pre-charge voltages to a plurality of conductive word lines of the memory array, the pre-charge voltages being selected from a plurality of reference pre-charge voltages; and under the control of the memory control circuit, the drive circuit applies a plurality of shutdown voltages To a plurality of closed word lines of the memory array, wherein, in a given direction, a target on word line of the on word lines is adjacent to a next adjacent target off word line of the off word lines; and a voltage difference from the target on word line to the next adjacent target off word line is less than a given reference voltage difference, wherein the given reference voltage difference is related to a voltage difference between a highest reference pre-charge voltage of the reference pre-charge voltages and a lowest reference pre-charge voltage of the reference pre-charge voltages. A memory device as described in claim 5, wherein the predetermined direction is from a common source line to a bit line; and a voltage of the common source line decreases at a junction of the target on word line and the next adjacent target off word line. A memory device as described in claim 5, wherein the precharge voltage applied to a non-target conductive word line of the conductive word lines is a first reference precharge voltage, a second reference precharge voltage, or a third reference precharge voltage of the reference precharge voltages, the first reference precharge voltage is higher than the second reference precharge voltage, and the second reference precharge voltage is higher than the third reference precharge voltage; and the precharge voltage applied to the at least one target conductive word line is the second reference precharge voltage or the third reference precharge voltage. A memory device as described in claim 5, wherein one of the OFF word lines is interspersed between the ON word lines.

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