TWI855367B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a semiconductor device including: providing a substrate which has a doped region; forming a first recess in the doped region of the substrate; conformally forming a first dielectric layer in the first recess; filling a first conductive structure in the first recess and on the first dielectric layer; partially removing the first conductive structure to form a second recess; conformally forming a second dielectric layer in a second recess; and filling a second conductive structure in the second recess and on the second dielectric layer.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a transistor and a manufacturing method thereof.

Dynamic random access memory (DRAM) is a volatile memory. Due to the structure and design of the components, there are various leakage mechanisms that cause the potential in the memory cell to be lost.

In transistors, gate-induced drain leakage (GIDL) has a great impact on the reliability of semiconductor devices and will have a negative impact on dynamic random access memory, thereby resulting in poor quality of dynamic random access memory.

Therefore, how to replace the traditional semiconductor devices and their manufacturing methods, and then solve the problem of gate-induced drain leakage current, has become one of the important topics.

In view of this, one object of the present invention is to provide a method for manufacturing a semiconductor device, which includes: providing a substrate, wherein the substrate has a doped region; forming a first groove in the doped region of the substrate; conformally forming a first dielectric layer in the first groove; filling a first conductive structure in the first groove and on the first dielectric layer; partially removing the first conductive structure to form a second groove; conformally forming a second dielectric layer in the second groove; and filling a second conductive structure in the second groove and on the second dielectric layer.

In some embodiments of the present invention, the work function of the second conductive structure is smaller than the work function of the first conductive structure.

In some embodiments of the present invention, the first dielectric layer surrounds the second dielectric layer, and the first dielectric layer laterally contacts the second dielectric layer.

In some embodiments of the present invention, the manufacturing method further includes: removing part of the second conductive structure to form a third groove; and filling the third groove with an insulating cap.

In some embodiments of the present invention, the manufacturing method further includes: removing a portion of the second conductive structure to form a third groove; conformally forming a third dielectric layer in the third groove; and filling an insulating cap in the third groove and on the third dielectric layer.

In some embodiments of the present invention, the second dielectric layer laterally contacts the third dielectric layer.

In some embodiments of the present invention, before forming the first conductive structure, a first barrier layer is conformally formed on the first dielectric layer.

In some embodiments of the present invention, after forming the first conductive structure, a second barrier layer is formed on the first conductive structure.

In some embodiments of the present invention, forming the second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; and laterally removing an upper sidewall portion of the barrier structure to form the second barrier layer.

In some embodiments of the present invention, forming a second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; laterally removing an upper sidewall portion of the barrier structure to form the second barrier layer; and laterally thinning an upper sidewall portion of the first dielectric layer.

In some embodiments of the present invention, the first dielectric layer includes a bottom and an upper sidewall portion, the upper sidewall portion is located above the bottom, and the thickness of the upper sidewall portion of the first dielectric layer is less than the thickness of the bottom of the first dielectric layer.

Another object of the present invention is to provide a semiconductor device, which includes a substrate, a first conductive structure, a second conductive structure, a first dielectric layer and a second dielectric layer. The substrate includes a source region and a drain region, and the first conductive structure is located between the source region and the drain region. The second conductive structure is located on the first conductive structure. The first dielectric layer surrounds the first conductive structure and the second conductive structure, and the second dielectric layer is partially located between the first conductive structure and the second conductive structure, and the second dielectric layer surrounds the second conductive structure, wherein the first dielectric layer further laterally contacts the second dielectric layer.

In some embodiments of the present invention, the work function of the second conductive structure is smaller than the work function of the first conductive structure.

In some embodiments of the present invention, the semiconductor device further includes a third dielectric layer, wherein the third dielectric layer is located on the second conductive structure.

In some embodiments of the present invention, the semiconductor device further includes a third dielectric layer and an insulating cap. The third dielectric layer is located on the second conductive structure, a portion of the third dielectric layer is located between the second conductive structure and the insulating cap, and the third dielectric layer surrounds the insulating cap.

In some embodiments of the present invention, the second dielectric layer further contacts the third dielectric layer laterally.

In some embodiments of the present invention, the inner wall of the first dielectric layer is stepped.

In some embodiments of the present invention, the first dielectric layer has a U-shaped cross-section, and the second dielectric layer has a U-shaped cross-section.

In some embodiments of the present invention, the third dielectric layer has a U-shaped cross-section.

In summary, the present invention provides a transistor device, whose gate structure is formed by stacking multiple dielectric layers, wherein the multiple dielectric layers are generally tubular, conical, cylindrical or test tube-shaped, so that the gate structure has a gradually increasing thickness. When the transistor structure of the present invention is applied to dynamic random access memory, it can effectively suppress the gate-induced drain leakage current. In addition, the thickness of part of the gate dielectric structure of the transistor of the present invention is thinner, so that the channel current, the standard critical voltage, and the sub-threshold swing can be improved, thereby improving the gate control capability. The gate metal of the transistor device of the present invention is protected by multiple barrier layers, so that the negative effects of the induced diffusion mechanism in the semiconductor manufacturing process can be effectively suppressed, thereby improving the quality of the finished product.

The above description is only used to explain the problem to be solved by the present invention, the technical means for solving the problem, and the effects produced, etc. The specific details of the present invention will be introduced in detail in the following implementation method and related drawings.

The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some commonly used structures and components will be depicted in the drawings in a simple schematic manner.

Please refer to FIG. 1. FIG. 1 shows a method 100 for manufacturing a semiconductor device 200 (see FIG. 11) in some embodiments of the present invention, wherein the method 100 begins at step 110, and step 110 includes providing a substrate, wherein the substrate has a doped region. Then, the method 100 proceeds to step 120, and step 120 includes forming a first groove in the doped region of the substrate. Then, the method 100 proceeds to step 130, wherein step 130 includes conformally forming a first dielectric layer in the first groove. Then, the method 100 proceeds to step 140, and step 140 includes filling a first conductive structure in the first groove and on the first dielectric layer. Next, the manufacturing method 100 proceeds to step 150, which includes removing a portion of the first conductive structure to form a second groove. Next, the manufacturing method 100 proceeds to step 160, which includes conformally forming a second dielectric layer in the second groove. Next, the manufacturing method 100 proceeds to step 170, which includes filling a second conductive structure in the second groove and on the second dielectric layer, wherein the work function of the second conductive structure is less than the work function of the first conductive structure. Next, the manufacturing method 100 proceeds to step 180, which includes removing a portion of the second conductive structure and forming a third groove, and filling the third groove with an insulating cap. In this specification, conformally forming a certain layered structure (single layer or multi-layer structure) means generating a layered structure with uniform thickness along a specific shape, so that the formed layered structure has a specific corresponding shape.

Please refer to FIG. 1 and FIG. 2, wherein FIG. 2 may be used to illustrate step 110 of the manufacturing method 100, wherein step 110 includes providing a substrate 210, the substrate 210 having a doped region 211, wherein the substrate 210 may include a semiconductor material (e.g., silicon) or a compound semiconductor material, wherein the compound semiconductor material includes silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide. The doped region 211 includes a p-type doped region 212 and an n-type doped region 213, wherein the n-type doped region 213 is located on the p-type doped region 212. In addition, the doped region 211 further includes an n-type lightly doped region 213a, wherein the n-type lightly doped region 213a is adjacent to and above the p-type doped region 212. Specifically, the p-type doped region 212 is doped with boron, gallium, indium or other suitable dopants in the third group (III) of the periodic table, and the n-type doped region 213 is doped with arsenic, phosphorus, and other suitable dopants in the fifth group (V) of the periodic table. In addition, the dopant concentration of the n-type lightly doped region 213a is lower than that of other regions of the n-type doped region 213.

Please refer to FIG. 1 and FIG. 3, wherein FIG. 3 may be used to represent step 120, step 130, and step 140 of the manufacturing method 100. In some embodiments of the present invention, step 120 includes forming a first groove 214 in a doped region 211 (see FIG. 2) of a substrate 210, thereby forming a source region 215 and a drain region 216, wherein the source region 215 includes a p-type region 215a and an n-type region 215b, wherein the n-type region 215b is located above the p-type region 215a, and the n-type region 215b may further include an n-type lightly doped region 215c, and the n-type lightly doped region 215c is adjacent to the p-type region 215a. The first groove 214 may be formed by a dry etching process, such as reactive-ion etching (RIE) or other suitable dry etching processes, but the present invention is not limited thereto. In addition, the drain region 216 includes a p-type region 216a and an n-type region 216b, wherein the n-type region 216b is located above the p-type region 216a, and the n-type region 216b may further include an n-type lightly doped region 216c, and the n-type lightly doped region 216c is adjacent to the p-type region 216a. It should be noted that the dopant concentration of the n-type lightly doped region 215c is lower than that of the n-type region 215b, and the dopant concentration of the n-type lightly doped region 216c is lower than that of the n-type region 216b. The provision of the n-type lightly doped region 215c and the n-type lightly doped region 216c helps to improve the gate leakage current problem.

In some embodiments of the present invention, step 130 of the manufacturing method 100 includes conformally forming a first dielectric layer 221 in the first groove 214, wherein the first dielectric layer 221 can be formed by oxidizing a portion of the substrate 210 (e.g., the inner wall of the first groove 214), wherein the first dielectric layer 221 is generally tubular, conical, cylindrical or test tube-shaped and has a single opening. Specifically, the first dielectric layer 221 is manufactured by an in-situ steam generation (ISSG) process, thereby obtaining the first dielectric layer 221 with excellent properties. However, the first dielectric layer 221 may also be manufactured by atomic layer deposition (ALD) or inductively coupled plasma-chemical vapor deposition (ICP-CVD), and the present invention is not limited thereto. In some embodiments, the first dielectric layer 221 may include silicon oxide ( _SiO2 ), helium oxide ( _HfO2 ), lumen oxide ( _La2O3 ), zirconium oxide ( _ZrO2 ), barium oxide ( _BaO ), titanium oxide ( _TiO2 ), tantalum oxide ( _Ta2O5 ), strontium oxide (SrO), _yttrium oxide ( _Y2O3 ) _, helium silicate ( _HfSiO4 ), zirconium silicate (ZrSiO4), aluminum oxide ( _Al2O3 ), magnesium oxide ( _MgO ), or calcium oxide (CaO), but the present invention is not limited thereto.

In some embodiments of the present invention, step 140 of the manufacturing method 100 includes filling the first conductive structure 231 in the first groove 214 and on the first dielectric layer 221. Specifically, a chemical mechanical polishing (CMP) process may be performed on the substrate 210, the first dielectric layer 221, the first conductive structure 231, and the first barrier layer 241, so that the top surface of the first dielectric layer 221, the top surface of the first conductive structure 231, and the top surface of the first barrier layer 241 are flush with the top surface of the substrate 210. In addition, the first conductive structure 231 may include ruthenium, palladium, platinum, tungsten, cobalt, nickel, benzirconia, zirconium, titanium, tantalum, aluminum and/or conductive metal oxides and conductive metal carbides (e.g., benzirconia carbide, zirconium carbide, titanium carbide and aluminum carbide). In addition, the first conductive structure 231 may be formed by chemical vapor deposition (CVD), sputtering or other suitable methods. In some embodiments, before forming the first conductive structure 231, a first barrier layer 241 is conformally formed on the first dielectric layer 221. In addition, the first barrier layer 241 may include titanium, titanium nitride (TiN, TiN ₂ ), tantalum or tantalum nitride, etc., and the first barrier layer 241 may be manufactured by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, etc. The provision of the first barrier layer 241 helps to prevent the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, thereby improving the quality of the finished product.

Please refer to FIG. 1 and FIG. 4. In some embodiments of the present invention, step 150 of the manufacturing method 100 includes partially removing the first conductive structure 231 and the first barrier layer 241 to form the second groove 217. Specifically, the second groove 217 can be formed by a dry etching process, such as reactive ion etching or other suitable dry etching processes, but the present invention is not limited thereto.

Please refer to FIG. 1 and FIG. 5 to FIG. 7. In some embodiments of the present invention, step 160 of the manufacturing method 100 includes conformally forming a second dielectric layer 223 in the second groove 217, wherein the first dielectric layer 221 surrounds the second dielectric layer 223, and the first dielectric layer 221 laterally contacts the second dielectric layer 223. In addition, in step 160, after forming the first conductive structure 231, a second barrier layer 243 is further formed on the first conductive structure 231.

In some embodiments, forming the second barrier layer 243 on the first conductive structure 231 further includes: conformally forming a barrier structure 242 in the second groove 217; and laterally removing an upper sidewall portion 242a of the barrier structure 242 to form the second barrier layer 243. The barrier structure 242 and the second barrier layer 243 may include titanium, titanium nitride (TiN, TiN ₂ ), tantalum, and tantalum nitride, and the barrier structure 242 may be manufactured by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., but the present invention is not limited thereto. Thus, the first barrier layer 241 and the second barrier layer 243 jointly cover the first conductive structure 231, thereby helping to prevent the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, thereby improving the quality of the finished product.

In addition, the cross section of the barrier structure 242 is substantially U-shaped and includes an upper sidewall portion 242a and a bottom portion 242b, wherein the upper sidewall portion 242a extends upward from the periphery of the bottom portion 242b. Specifically, the upper sidewall portion 242a of the barrier structure 242 may be laterally removed by performing an etching process (e.g., a dry etching process, a wet etching process, or a gas etching process) on the barrier structure 242, and the bottom portion 242b of the barrier structure 242 may also be partially removed by the aforementioned etching process, and the remaining portion of the barrier structure 242 forms the second barrier layer 243. In addition, the etching process performed on the barrier structure 242 also thins and partially removes the first dielectric layer 221 laterally, thereby forming an upper sidewall portion 221a of the first dielectric layer 221, wherein the thickness T1 of the upper sidewall portion 221a of the first dielectric layer 221 is less than the thickness T2 of other portions of the first dielectric layer 221. Specifically, the first dielectric layer 221 is substantially tubular, conical, cylindrical or test tube-shaped and has a single opening, wherein the first dielectric layer 221 has a U-shaped cross-section. In addition, the first dielectric layer 221 further includes a bottom portion 221b, and the upper sidewall portion 221a is located above the bottom portion 221b, wherein the thickness T1 of the upper sidewall portion 221a is less than the thickness T2 of the bottom portion 221b of the first dielectric layer 221. In addition, the bottom 221b is generally tubular, conical, cylindrical or test tube-shaped and has a single opening, and the upper side wall portion 221a extends upward along the outer circumference of the bottom 221b, so that the inner wall of the first dielectric layer 221 is stepped. In addition, a chemical mechanical polishing process can be performed on the substrate 210, the first dielectric layer 221 and the barrier structure 242 so that the top surface of the first dielectric layer 221 and the top surface of the barrier structure 242 are flush with the top surface of the substrate 210.

In Figure 7, the second dielectric layer 223 is conformally formed in the second groove 217, wherein the second dielectric layer 223 is substantially tubular, conical, cylindrical or test tube-shaped and has a single opening, and the second dielectric layer 223 has a U-shaped cross-section, wherein the first dielectric layer 221 surrounds the second dielectric layer 223, and the inner wall surface of the first dielectric layer 221 laterally contacts the outer wall surface of the second dielectric layer 223. The second dielectric layer 223 may also be manufactured by an on-site vapor generation process, an atomic layer deposition process or a high-density plasma chemical vapor deposition process, and the second dielectric layer 223 may include silicon oxide (SiO ₂ ), arsenic oxide (HfO ₂ ), lumen oxide (La ₂ O ₃ ), zirconium oxide (ZrO ₂ ), barium oxide (BaO), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), strontium oxide (SrO), yttrium oxide (Y 2 O ₃ ), arsenic silicate (HfSiO ₄ ), zirconium silicate (ZrSiO ₄ ), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO) or calcium oxide (CaO), but the present invention is not limited thereto.

1 and 8, FIG. 8 may be used to illustrate step 170 of the manufacturing method 100, and step 170 includes filling a second conductive structure 233 in the second recess 217 and on the second dielectric layer 223, wherein the work function of the second conductive structure 233 is less than the work function of the first conductive structure 231. In addition, the second conductive structure 233 may include doped polysilicon, ruthenium, palladium, platinum, tungsten, cobalt, nickel, uranium, zirconium, titanium, tantalum, aluminum, and/or conductive metal oxides and conductive metal carbides (e.g., uranium carbide, zirconium carbide, titanium carbide, and aluminum carbide). When the second conductive structure 233 is doped polysilicon, the second conductive structure 233 includes polysilicon and dopants, and the dopants may be the aforementioned n-type dopant or p-type dopant, but the present invention is not limited thereto. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the second conductive structure 233 so that the top surface of the first dielectric layer 221 and the top surface of the barrier structure 242 are flush with the top surface of the substrate 210.

Please refer to FIG. 1 and FIG. 9 to FIG. 11, where FIG. 9 to FIG. 11 may be used to represent step 180 of the manufacturing method 100. In some embodiments of the present invention, step 180 includes: partially removing the second conductive structure 233 to form a third groove 219; and filling the third groove 219 with an insulating cap 251. In addition, the insulating cap 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233. In some other embodiments of the present invention, step 180 of the manufacturing method 100 may further include: before filling the insulating cap 251, conformally forming a third dielectric layer 225 in the third groove 219; and filling the insulating cap 251 in the third groove 219 and on the third dielectric layer 225, so that a portion of the third dielectric layer 225 is located between the second conductive structure 233 and the insulating cap 251, wherein the insulating cap 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the insulating cap 251 so that the top surface of the insulating cap 251 is flush with the top surface of the substrate 210 .

Please refer to FIG. 9 , which may be used to illustrate that the second conductive structure 233 is partially removed to form the third groove 219. The third groove 219 may be formed by a dry etching process, such as reactive ion etching or other suitable dry etching processes, but the present invention is not limited thereto.

Please refer to Figure 10, which can be used to illustrate that a third dielectric layer 225 is conformally formed in the third groove 219. The third dielectric layer 225 is located on the second dielectric layer 223. The third dielectric layer 225 is generally tubular, conical, cylindrical or test tube-shaped and has a single opening, so that the third dielectric layer 225 has a U-shaped cross-section, wherein the inner surface of the second dielectric layer 223 laterally contacts the outer surface of the third dielectric layer 225, so that the second dielectric layer 223 surrounds the second conductive structure 233 and the third dielectric layer 225. The third dielectric layer 225 may also be formed by atomic layer deposition or high density plasma chemical vapor deposition, and the third dielectric layer 225 may include silicon oxide (SiO ₂ ), ferrous oxide (HfO ₂ ), lumen oxide (La ₂ O ₃ ), zirconium oxide (ZrO ₂ ), barium oxide (BaO), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), strontium oxide (SrO), yttrium oxide (Y 2 O _{3 ), ferrous silicate (HfSiO 4 )} , zirconium silicate (ZrSiO ₄ ), aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO) or calcium oxide (CaO), but the present invention is not limited thereto. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the third dielectric layer 225 so that the top surface of the third dielectric layer 225 is flush with the top surface of the substrate 210.

Please refer to FIG. 11 , which may be used to illustrate that an insulating cap 251 is filled in the third groove 219 . The insulating cap 251 may be manufactured by a chemical vapor deposition process, a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, wherein the insulating cap 251 includes silicon nitride (Si ₃ N ₄ ) or silicon oxynitride (Si ₂ ON ₂ ), but the present invention is not limited thereto.

Referring to FIG. 11 , another object of the present invention is to provide a semiconductor device 200, the semiconductor device 200 includes a substrate 210, a first conductive structure 231, a second conductive structure 233, a first dielectric layer 221, and a second dielectric layer 223. The substrate 210 includes a source region 215 and a drain region 216, the first conductive structure 231 is located between the source region 215 and the drain region 216, and the second conductive structure 233 is located on the first conductive structure 231 and between the source region 215 and the drain region 216. In addition, the first dielectric layer 221 surrounds the first conductive structure 231 and the second conductive structure 233, the second dielectric layer 223 is partially located between the first conductive structure 231 and the second conductive structure 233, and the second dielectric layer 223 surrounds the second conductive structure 233 but does not surround the first conductive structure 231, wherein the inner wall surface of the first dielectric layer 221 further laterally contacts the outer wall surface of the second dielectric layer 223. In some embodiments, the work function of the second conductive structure 233 is smaller than the work function of the first conductive structure 231. Thus, the first conductive structure 231 and the second conductive structure 233 serve as gate conductors, and the first dielectric layer 221 and the second dielectric layer 223 form a gate dielectric structure with increasing thickness, thereby suppressing the gate-induced drain leakage current. It can be seen that the semiconductor device 200 of the present invention can be a transistor device that can be used in dynamic random access memory and effectively reduce the problem caused by the gate-induced drain leakage current. In addition, the thickness of the gate dielectric structure around the first conductive structure 231 is relatively thin, so that the source-drain current, standard voltage threshold (SVT), and subthreshold swing can be improved, thereby improving the gate control capability.

In some embodiments of the present invention, the first dielectric layer 221 and the second dielectric layer 223 are substantially tubular, conical, cylindrical or test tube-shaped and have a single opening, and the first dielectric layer 221 and the second dielectric layer 223 have a U-shaped cross-section. In addition, the first dielectric layer 221 includes an upper sidewall portion 221a and a bottom portion 221b, the upper sidewall portion 221a is located above the bottom portion 221b, wherein the thickness T1 of the upper sidewall portion 221a is less than the thickness T2 of the bottom portion 221b of the first dielectric layer 221, the thickness T1 of the upper sidewall portion 221a is less than 5 nanometers, and the thickness T2 of the bottom portion 221b is less than or equal to 5 nanometers. In some embodiments, the thickness T1 of the upper wall portion 221a is less than 4.5 nanometers, and the thickness T2 of the bottom portion 221b is less than or equal to 4.5 nanometers. Specifically, the bottom portion 221b is substantially tubular, conical, cylindrical or test tube-shaped and has a single opening, and the upper wall portion 221a extends upwardly aligned with the outer circumference of the bottom portion 221b, so that the inner wall of the first dielectric layer 221 is stepped. The first dielectric layer 221 further surrounds the second dielectric layer 223, wherein the second dielectric layer 223 is substantially tubular, conical, cylindrical or test tube-shaped and has a single opening, so that the inner wall surface of the first dielectric layer 221 laterally contacts the outer wall surface of the second dielectric layer 223. In addition, the first dielectric layer 221 and the second dielectric layer 223 may include the same dielectric material, or may include different dielectric materials, but the present invention is not limited thereto. In some embodiments, the thickness T3 of the second dielectric layer 223 is less than or equal to 2 nanometers. In some embodiments, the thickness T3 of the second dielectric layer 223 is less than or equal to 1.5 nanometers.

In some embodiments of the present invention, the semiconductor device 200 further includes a third dielectric layer 225 and an insulating cap 251, wherein the third dielectric layer 225 is located on the second conductive structure 233, and a portion of the third dielectric layer 225 is located between the second conductive structure 233 and the insulating cap 251, and the third dielectric layer 225 surrounds the insulating cap 251, but the third dielectric layer 225 does not surround the first conductive structure 231 and the second conductive structure 233, wherein the second dielectric layer 223 further laterally contacts the third dielectric layer 225. In some embodiments, the thickness T4 of the third dielectric layer 225 is less than or equal to 1.5 nanometers. In some embodiments, the thickness T4 of the third dielectric layer 225 is less than or equal to 1.2 nm. Thus, the first conductive structure 231 and the second conductive structure 233 act as gate conductors, and the first dielectric layer 221, the second dielectric layer 223 and the third dielectric layer 225 form a gate dielectric structure with increasing thickness, thereby suppressing gate-induced drain leakage current. In some other embodiments of the present invention, the semiconductor device 200 does not include the third dielectric layer 225, so the insulating cap 251 directly contacts the second dielectric layer 223 and the second conductive structure 233, wherein the insulating cap 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233.

Specifically, the third dielectric layer 225 is generally tubular, conical, cylindrical or test tube-shaped and has a single opening, wherein the third dielectric layer 225 has a U-shaped cross section, the second dielectric layer 223 surrounds the third dielectric layer 225 and the insulating cap 251, and the inner wall surface of the second dielectric layer 223 laterally contacts the outer wall surface of the third dielectric layer 225, so that the second dielectric layer 223 and the third dielectric layer 225 together serve as a gate dielectric structure and suppress gate-induced drain leakage current. In addition, the first dielectric layer 221, the second dielectric layer 223 and the third dielectric layer 225 may include the same dielectric material, but may also include different dielectric materials, and the present invention is not limited thereto.

In some embodiments of the present invention, the semiconductor device 200 includes a first barrier layer 241 and a second barrier layer 243, wherein the first barrier layer 241 surrounds the first conductive structure 231, wherein the first barrier layer 241 is substantially tubular, conical, cylindrical or test tube-shaped and has a single opening, and the second barrier layer 243 is located above the first conductive structure 231 and closes the opening of the first barrier layer 241. Specifically, the first barrier layer 241 is located between the first conductive structure 231 and the first dielectric layer 221, and the second barrier layer 243 is located between the first conductive structure 231 and the second dielectric layer 223. Thereby, the first barrier layer 241 and the second barrier layer 243 jointly cover the first conductive structure 231 , and the first barrier layer 241 and the second barrier layer 243 help to prevent the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, thereby improving the quality of the finished product.

In summary, the present invention provides a transistor device, whose gate structure is formed by stacking multiple dielectric layers, wherein the multiple dielectric layers are generally tubular, conical, cylindrical or test tube-shaped, so that the gate structure has a gradually increasing thickness. When the transistor structure of the present invention is applied to dynamic random access memory, it can effectively suppress the gate-induced drain leakage current. In addition, the thickness of part of the gate dielectric structure of the transistor of the present invention is thinner, so that the channel current, the standard critical voltage, and the sub-threshold swing can be improved, thereby improving the gate control capability. The gate metal of the transistor device of the present invention is protected by multiple barrier layers, so that the negative effects of the induced diffusion mechanism in the semiconductor manufacturing process can be effectively suppressed, thereby improving the quality of the finished product.

The various embodiments of the present invention have been described above. It should be understood that the various embodiments are presented as examples only and are not intended to be limiting. Many modifications may be made to the embodiments of the present invention based on the disclosure herein without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above.

100: Manufacturing method 110, 120, 130, 140, 150, 160, 170, 180: Steps 200: Semiconductor device 210: Substrate 211: Doped region 212: P-type doped region 213: N-type doped region 213a: N-type lightly doped region 214: First groove 215: Source region 215a: P-type region 215b: N-type region 215c: N-type lightly doped region 216: Drain region 216a: P-type region 216b: N-type region 216c: N-type lightly doped region 217: second groove 219: third groove 221: first dielectric layer 221a: upper side wall 221b: bottom 223: second dielectric layer 225: third dielectric layer 231: first conductive structure 233: second conductive structure 241: first barrier layer 242: barrier structure 242a: upper side wall 242b: bottom 243: second barrier layer 251: insulating cap T1, T2, T3, T4: thickness

In order to achieve the above advantages and features, the principles briefly described above will be explained more specifically with reference to the implementation methods, and the specific implementation methods are shown in the accompanying drawings. These drawings only describe the present invention by way of example and therefore do not limit the scope of the invention. Through the accompanying drawings, the principles of the present invention will be clearly explained, and the additional features and details will be fully described, wherein: FIG. 1 is a flow chart of a method for manufacturing a semiconductor device in some embodiments of the present invention; and FIG. 2 to FIG. 11 are schematic diagrams of the various steps of the manufacturing method in FIG. 1.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100: Manufacturing method

110,120,130,140,150,160,170,180: Steps

Claims (20)

A method for manufacturing a semiconductor device includes: providing a substrate, wherein the substrate has a doped region; forming a first groove in the doped region of the substrate; conformally forming a first dielectric layer in the first groove; filling a first conductive structure in the first groove and on the first dielectric layer; partially removing the first conductive structure to form a second groove; conformally forming a second dielectric layer in the second groove, wherein the first dielectric layer and the second dielectric layer form a gate dielectric structure with an increasing thickness upward; and filling a second conductive structure in the second groove and on the second dielectric layer. A manufacturing method as described in claim 1, wherein the work function of the second conductive structure is less than the work function of the first conductive structure. A manufacturing method as described in claim 1, wherein the first dielectric layer surrounds the second dielectric layer, and the first dielectric layer laterally contacts the second dielectric layer. The manufacturing method as described in claim 1 further includes: removing part of the second conductive structure to form a third groove; and filling the third groove with an insulating cap. The manufacturing method as described in claim 1 further comprises: Partially removing the second conductive structure to form a third groove; conformally forming a third dielectric layer in the third groove; and filling an insulating cap in the third groove and on the third dielectric layer. A manufacturing method as described in claim 5, wherein the second dielectric layer laterally contacts the third dielectric layer. In the manufacturing method as described in claim 1, before forming the first conductive structure, a first barrier layer is conformally formed on the first dielectric layer. In the manufacturing method described in claim 1 or 7, after forming the first conductive structure, a second barrier layer is formed on the first conductive structure. In the manufacturing method as described in claim 8, forming a second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; and laterally removing the upper sidewall portion of the barrier structure to form the second barrier layer. In the manufacturing method as described in claim 8, forming a second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; Laterally removing the upper sidewall portion of the barrier structure to form the second barrier layer; and laterally thinning the upper sidewall portion of the first dielectric layer. A manufacturing method as described in claim 1, wherein the first dielectric layer includes a bottom and an upper sidewall portion, the upper sidewall portion is located above the bottom, and the thickness of the upper sidewall portion of the first dielectric layer is less than the thickness of the bottom of the first dielectric layer. A manufacturing method as described in claim 1, wherein the first dielectric layer is manufactured by an on-site vapor generation process, and the second dielectric layer is manufactured by an atomic layer deposition process. A semiconductor device includes: a substrate including a source region and a drain region; a first conductive structure located between the source region and the drain region; a second conductive structure located on the first conductive structure; a gate dielectric structure including: a first dielectric layer surrounding the first conductive structure and the second conductive structure; and a second dielectric layer partially located between the first conductive structure and the second conductive structure, and the second dielectric layer surrounding the second conductive structure, wherein the first dielectric layer further contacts the second dielectric layer laterally, and the thickness of the gate dielectric structure increases upward. A semiconductor device as claimed in claim 13, wherein the work function of the second conductive structure is less than the work function of the first conductive structure. The semiconductor device of claim 13 further includes a third dielectric layer, wherein the third dielectric layer is located on the second conductive structure. The semiconductor device of claim 13 further comprises: a third dielectric layer located on the second conductive structure, and a portion of the third dielectric layer is located between the second conductive structure and the insulating cap; and an insulating cap, wherein the third dielectric layer surrounds the insulating cap. A semiconductor device as claimed in claim 15 or 16, wherein the second dielectric layer further contacts the third dielectric layer laterally. A semiconductor device as claimed in claim 13, wherein the inner wall of the first dielectric layer is stepped. A semiconductor device as claimed in claim 13, wherein the first dielectric layer has a U-shaped cross-section and the second dielectric layer has a U-shaped cross-section. A semiconductor device as claimed in claim 15 or 16, wherein the third dielectric layer has a U-shaped cross-section.

Images