TWI854099B - Esd protection circuit structure - Google Patents

Abstract

A ESD protection circuit is provided, including a substrate; a first well with first conductive type in the substrate; a second well with second conductive type in first well; a first ring area with first conductive type in first well, and coupled to ground; plural first conductive doping areas in the second well, having at least a first, a second, a third area; plural second conductive doping area in the first well, having at least a first, a second, a third area. The first and the third areas of the plural first conductive doping areas are coupled to a high potential end, the first and the third areas of the plural second conductive doping areas are coupled to ground. The second areas of the plural first and second conductive doping areas are electrically connected.

Description

Electrostatic discharge protection circuit structure

The present invention relates to an electrostatic discharge protection circuit, and in particular to an electrostatic discharge protection circuit with a high holding voltage.

In semiconductor integrated circuits (ICs), in order to prevent static electricity from damaging the internal circuits, an electrostatic discharge protection circuit is often set between the internal circuits and the input pads. Among them, the SCR circuit has excellent high current behavior and can provide good area gain, so it is often used as an electrostatic discharge protection circuit.

As is known to all, the SCR circuit is very strong, but due to its circuit characteristics, it has a deep snapback effect, which makes the SCR only have a low holding voltage. This problem will produce the latch-up (LU) effect. Therefore, if the SCR circuit is affected by noise and triggered during IC circuit operation, it will cause the SCR circuit to burn out, thereby affecting the protection of electrostatic discharge.

To solve this problem, the prior art provides two solutions. One is the method shown in Figure 1A, which is to increase the trigger current; that is, to prevent the SCR circuit from being easily triggered and causing false operation. The other is the method shown in Figure 1B, which is to increase the holding voltage.

However, there is still a need in this field to provide an electrostatic discharge protection circuit that can increase the holding voltage and reduce the triggering voltage without causing false operation.

According to an embodiment of the present invention, an electrostatic discharge protection circuit is provided, which includes: a substrate; a first well region having a first conductivity type and disposed in the substrate; a second well region having a second conductivity type and disposed in the first well region; a first ring region having the first conductivity type and disposed in the first well region and coupled to a ground terminal; a plurality of first conductivity type doped regions disposed in the second well region and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to a high potential terminal; and a plurality of second conductivity type doped regions disposed in the first well region and at least including a first, second and third region in sequence, wherein the first region and the third region are coupled to the ground terminal. At least the second region of the plurality of first conductivity type doped regions and the second region of the plurality of second conductivity type doped regions are electrically connected to each other. The first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.

According to an embodiment of the present invention, the electrostatic discharge protection circuit may further include: a second ring region having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and coupled to the high potential end; and a third ring region having the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground end.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, each of the plurality of first conductive type doped regions is disposed adjacent to each other at a certain interval in the first direction of the substrate, and extends in a second direction perpendicular to the first direction.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the triggering voltage of the first electrostatic discharge path is greater than the triggering voltage of the second electrostatic discharge path, and the triggering voltage of the second electrostatic discharge path is greater than the triggering voltage of the third electrostatic discharge path.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the holding voltages corresponding to the first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path are approximately equal.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier.

According to another embodiment of the present invention, an electrostatic discharge protection circuit structure is provided, which includes: a substrate; a first well region, having a first conductivity type, disposed in the substrate; a second well region, having a second conductivity type, disposed in the first well region; a first ring region, having the first conductivity type, disposed in the first well region, and coupled to a ground terminal; a plurality of first conductivity type doped regions, disposed in the second well region, and at least including first, second, and third regions in sequence, wherein the first region and the third region are coupled to a high potential terminal, and gates are disposed on the substrate and between the first, second, and third regions in pairs; and a plurality of second conductivity type doped regions, disposed in the first well region, and at least including first, second, and third regions in sequence, wherein the first region and the third region are coupled to the ground terminal, and gates are disposed on the substrate and between the first, second, and third regions in pairs. At least the second region of the plurality of first conductive type doped regions and the second region of the plurality of second conductive type doped regions are electrically connected to each other. The first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path. The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path. The second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path.

According to an embodiment of the present invention, the electrostatic discharge protection circuit may further include: a second ring region having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high potential end; and a third ring region having the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground end.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the gates disposed between the first, second and third regions of the plurality of first conductive type doped regions serve as PMOS trigger nodes, and the gates disposed between the first, second and third regions of the plurality of second conductive type doped regions serve as NMOS trigger nodes.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, each of the plurality of first conductive type doped regions is arranged at a certain interval in the first direction of the substrate and extends in a second direction perpendicular to the first direction.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the triggering voltage of the first electrostatic discharge path is greater than the triggering voltage of the second electrostatic discharge path, and the triggering voltage of the second electrostatic discharge path is greater than the triggering voltage of the third electrostatic discharge path.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the holding voltages corresponding to the first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path are approximately equal.

According to an embodiment of the present invention, in the above-mentioned electrostatic discharge protection circuit, the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier.

Based on the above, the electrostatic discharge protection circuit structure according to the embodiment of the present invention provides three electrostatic discharge paths with different triggering voltages, so that electrostatic discharge can be further effectively performed. In addition, the parasitic silicon-controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so the transistor spacing in the parasitic silicon-controlled rectifier can be increased, thereby further increasing the holding voltage. In addition, by improving the electrostatic discharge performance, the area of the electrostatic discharge protection circuit structure can also be further reduced.

100, 200: base

102, 202: First well area

104, 204: Second well area

110, 210: First Ring Road

112, 212: Second Ring Road

114, 214: Multiple first conductivity type doped regions

114a, 114b, 114c: District 1, District 2, District 3

214a, 214b, 214c: District 1, District 2, District 3

122, 224: Multiple second conductivity type doped regions

122a, 122b, 122c: District 1, District 2, District 3

224a, 224b, 224c: District 1, District 2, District 3

120, 210: Third Ring Road

216a, 216b, 226a, 226b: Gate

P11, P12, P31, P32: parasitic transistors

N11, N12, N31, N32: parasitic transistors

P2, P4: parasitic transistors

ESD1~ESD3: The first to third electrostatic discharge current

GND: Ground terminal

Figure 1A and Figure 1B are two known ways to solve the SCR circuit latching problem.

FIG2 is a top view of an electrostatic discharge protection circuit according to an embodiment of the present invention.

Figure 3A is a schematic cross-sectional diagram of the electrostatic discharge protection circuit cut along the section line A-A’ in Figure 2.

FIG3B is a schematic diagram showing the doping example and parasitic transistor of the cross-sectional view of FIG3A.

FIG4A is a schematic diagram of the equivalent circuit and discharge path of FIG3B according to an embodiment of the present invention.

FIG4B is a schematic diagram of the discharge path according to an embodiment of the present invention.

FIG5 is a transmission line pulse (TLP) current-voltage curve diagram of the electrostatic discharge protection circuit according to an embodiment of the present invention.

FIG6A is a cross-sectional doping schematic diagram of an electrostatic discharge protection circuit of another embodiment of the present invention.

FIG6B is a schematic diagram showing the doping example and parasitic transistor of the cross-sectional view of FIG6A.

FIG6C is a schematic diagram of the equivalent circuit and discharge path of FIG6B.

FIG2 is a top view of an electrostatic discharge protection circuit according to an embodiment of the present invention. FIG3A is a cross-sectional schematic diagram of the electrostatic discharge protection circuit cut along the section line A-A' of FIG2. The semiconductor structure of the electrostatic discharge protection circuit of the present invention will be described below in conjunction with FIG2 and FIG3A.

As shown in FIGS. 2 and 3A, the electrostatic discharge protection circuit includes a substrate 100, a first well region 102, a second well region 104, a first ring region 110, a plurality of first conductivity type doped regions 114, and a plurality of second conductivity type doped regions 122. The substrate 100 may have a first conductivity type, such as a P-type doped region. The first well region 102 has the same first conductivity type as the substrate 100 and is disposed in the substrate 100. The second well region 104 has a second conductivity type and is disposed in the first well region 102. Here, the second conductivity type is, for example, an N-type doped region.

In addition, the first ring region 110 has a first conductivity type, is disposed in the first well region 102, and is coupled to the ground terminal GND. Here, the ground terminal GND may be the lowest potential of the entire circuit system. In addition, although the first ring region 110 shown in FIG. 2 is a slightly square or rectangular structure, it is not actually limited to this shape and can be designed according to actual needs.

In addition, the plurality of first conductive type doped regions 114 may include a plurality of regions separated by a certain interval and disposed in the first well region 102. In this embodiment, the first region 114a, the second region 114b and 114c are used as an example for illustration. Similarly, the plurality of second conductive type doped regions 122 may also include a plurality of regions separated by a certain interval and disposed in the first well region 102. In this embodiment, the first region 122a, the second region 122b and 122 are used as an example for illustration. With respect to the plurality of first conductive type doped regions 114 and the plurality of second conductive type doped regions 122, those skilled in the art may appropriately change or modify their quantity and electrical connection method based on the description of this embodiment, without departing from the scope of implementation of the present invention.

In addition, as shown in FIG. 2 , each of the plurality of first conductive type doped regions 114 (e.g., 114a, 114b, 114c) is sequentially arranged in the first direction X of the substrate 100 at a certain interval, and extends in the second direction Y perpendicular to the first direction X. Similarly, each of the plurality of second conductive type doped regions 122 (e.g., 122a, 122b, 122c) is sequentially arranged in the first direction X of the substrate 100 at a certain interval, and extends in the second direction Y perpendicular to the first direction X.

In addition, as shown in FIG. 3A, at least the second region 114b of the plurality of first conductive type doped regions 114 and the second region 122b of the plurality of second conductive type doped regions 122 are electrically connected to each other. In addition, the first region 114a and the third region 114c of the plurality of first conductive type doped regions 114 are coupled to a high potential end. Here, the so-called high potential end can be an input pad, a circuit power rail, etc., in short, an end with a relatively high potential in the circuit. The first region 122a and the third region 122c of the plurality of second conductive type doped regions 122 are coupled to the ground end GND.

In addition, according to an embodiment of the present invention, the electrostatic discharge protection circuit structure may further include a second ring region 112 and a third ring region 120. The second ring region 112 is of the second conductivity type, is disposed in the second well region 104, surrounds a plurality of first conductivity type doped regions 114, and is coupled to the high potential end. The third ring region 120 has the first conductivity type, is disposed in the first well region 102, surrounds a plurality of second conductivity type doped regions 122, and is coupled to the ground end GND. In addition, although the second ring region 112 and the third ring region 120 shown in FIG. 2 are slightly square or rectangular structures, they are not actually limited to this shape and can be designed according to actual needs.

Next, the circuit structure and operation mode of the electrostatic discharge protection circuit of the embodiment of the present invention are described. FIG3B shows the doping example and the schematic diagram of the parasitic transistor of the cross-sectional view of FIG3A. In the following description example, the first conductivity type and the second conductivity type will be described as P-type doping and N-type doping respectively.

As shown in FIG. 3B , although the second ring region 112 is N-doped and the third ring region 120 is P-doped, as mentioned above, the second ring region 112 and the third ring region 120 can still be selectively provided. In addition, in this example, although the diagram shows the P+ doped region and the N+ doped region, in practice, P+ or N+ doping is not required, but only the type of doping is sufficient, for example, a lighter doping such as P- or N- can be used.

As shown in FIG. 3B , the first region (in this example, P+ doping) 114a, the second region (in this example, P+ doping) 114b and the second well region (in this example, N well) 104 of the plurality of first conductive type doped regions 114 constitute a first parasitic transistor P11 (i.e., a parasitic PNP transistor), and the second region (in this example, N+ doping) 122b, the third region (in this example, N+ doping) 112c and the first well region (in this example, P well) 102 of the plurality of second conductive type doped regions 122 constitute a second parasitic transistor N11 (i.e., a parasitic NPN transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 102, the substrate 100 and the first well region 102 form a third parasitic transistor P2 (i.e., a parasitic PNP transistor), thereby forming a second electrostatic discharge path ESD 2. The second region, the third region and the second well region 104 in the plurality of first conductive type doped regions 114 form a fourth parasitic transistor P12 (i.e., a parasitic PNP transistor), and the first region 122a, the second region 122b and the first well region 102 in the plurality of second conductive type doped regions 122 form a fifth parasitic transistor N12, thereby forming a third electrostatic discharge path ESD 3. The fourth parasitic transistor P12 and the fifth parasitic transistor N12 form a silicon-controlled rectifier SCR.

FIG4A is a schematic diagram of the equivalent circuit and discharge path of FIG3B according to an embodiment of the present invention. FIG4B is a schematic diagram of the discharge path according to an embodiment of the present invention. The equivalent circuit diagram of the electrostatic discharge protection circuit structure described in FIG3B is shown in FIG4A. According to an embodiment of the present invention, three first to third electrostatic discharge paths ESD 1~ESD 3 with different triggering voltages are provided between the high potential end and the ground end GND. The first electrostatic discharge path ESD 1 is composed of a first parasitic transistor P11 and a second parasitic transistor N11 coupled between the high potential end and the ground end GND, and is the earliest triggered discharge path. The second electrostatic discharge path ESD 2 is composed of the third parasitic transistor P2 coupled between the high potential terminal and the ground terminal GND (PNP type), and is the discharge path that is triggered next. The third electrostatic discharge path ESD 3 (SCR type) is composed of the fourth parasitic transistor P12 and the fifth parasitic transistor N12 coupled between the high potential terminal and the ground terminal GND, and is the discharge path that is triggered last.

As shown in FIGS. 4A and 4B , when an electrostatic discharge event occurs at a high potential end (e.g., an input pad), the first electrostatic discharge path ESD1 will be triggered to conduct first, and the conduction voltage at this time is the breakdown voltage of the first parasitic transistor P11 and the second parasitic transistor N12. Thus, the ESD current can be guided to the ground terminal GND through the first electrostatic discharge path ESD1. As shown in FIG. 3A , the ESD current enters from the first region 114a of the plurality of first conductive type doped regions 114, passes through the second region 114b, and then enters the second region 122b of the plurality of second conductive type doped regions 122 through electrical connection, and then discharges to the ground terminal GND through the third region 122c.

Then, after the first ESD path ESD 1 is turned on, the secondary current will successively turn on the second ESD path ESD 2 and the second ESD path ESD 3. After the second ESD path ESD 2 is triggered and turned on, the discharge current will enter the second well region 104 (or enter the second well region 104 from the N+ doping 112 of the second ring region), pass through the first well region 102, and discharge from the first ring region (P+ doping) 110 to the ground terminal GND. Then, after the third electrostatic discharge path ESD 3 is turned on, the discharge current enters from the second region 114b of the plurality of first conductive type doped regions 114, passes through the third region 114c, and then enters the second region 122b of the plurality of second conductive type doped regions 122 through electrical connection, and then discharges to the ground terminal GND through the first region 122a.

As described above, according to the electrostatic discharge protection circuit of the embodiment of the present invention, since the third electrostatic discharge path ESD 3 is triggered by the secondary current, the interval d (see Figures 3A and 3B) of the parasitic silicon-controlled rectifier SCR constituting the third electrostatic discharge path ESD 3 can be further increased, thereby obtaining a higher holding voltage characteristic.

FIG5 is a transmission line pulse (TLP) current-voltage curve diagram of the electrostatic discharge protection circuit according to the embodiment of the present invention. As shown in FIG5, the electrostatic discharge protection circuit of the present embodiment can have three triggering stages, which correspond to the first to third electrostatic discharge paths ESD 1~ESD 3 mentioned above. As can be seen from FIG5 , the trigger voltage Vt of the first electrostatic discharge path ESD 1 is about 23.3 V and the holding voltage Vh is about 18.3 V, the trigger voltage Vt of the second electrostatic discharge path ESD 2 is about 18.88 V and the holding voltage Vh is about 18 V, and the trigger voltage Vt of the third electrostatic discharge path ESD 3 is about 19.66 V and the holding voltage Vh is about 18.37 V. It can be seen that the trigger voltage of the first electrostatic discharge path is greater than the trigger voltage of the second electrostatic discharge path, and the trigger voltage of the second electrostatic discharge path is less than the trigger voltage of the third electrostatic discharge path. In addition, the holding voltages corresponding to the first to third electrostatic discharge paths are roughly equal. From this result, it can be seen that the electrostatic discharge protection circuit of the embodiment of the present invention can be applied to operations with higher holding voltages.

In summary, in an experimental example of the ESD protection circuit of the embodiment of the present invention, the breakdown voltage is about 23V, and can reach 1.953V/ ^μm2 under the human body model (HBM) test. Compared with the performance of the existing ESD protection circuit, the human body model (HBM) test is generally only 0.549V/ ^μm2 . In terms of performance, the performance of the ESD protection circuit of the embodiment of the present invention can be improved by at least three times.

In addition, according to the experimental results of the electrostatic discharge protection circuit of the embodiment of the present invention, the area is only about 4095 μm ^2. Compared with the current general area size of at least 9000 μm ² , the area of the electrostatic discharge protection circuit disclosed in this embodiment can be reduced by nearly half.

Next, another embodiment of the present invention is described. FIG. 6A is a schematic diagram of a cross-sectional doping of an electrostatic discharge protection circuit of another embodiment of the present invention. FIG. 6B is a schematic diagram of doping and parasitic transistors in the cross-sectional view of FIG. 6A. FIG. 6C is a schematic diagram of an equivalent circuit and discharge path of FIG. 6B.

In addition, the embodiment shown in FIG. 6A to FIG. 6C differs from the embodiment described above in that the gate structure is formed between the two doped regions in the well region, and the remaining structures are basically the same or similar. The following will be explained in conjunction with FIG. 6A to FIG. 6C.

As shown in FIG. 6A , the electrostatic discharge protection circuit includes a substrate 200, a first well region 202, a second well region 204, a first ring region 210, a plurality of first conductivity type doped regions 214, and a plurality of second conductivity type doped regions 224. The substrate 200 may have a first conductivity type, such as a P-type doped region. The first well region 202 has the same first conductivity type as the substrate 200 and is disposed in the substrate 200. The second well region 204 has a second conductivity type and is disposed in the first well region 202. Here, the second conductivity type is, for example, an N-type doped region.

In addition, the first ring region 210 has a first conductivity type, is disposed in the first well region 202, and is coupled to the ground terminal GND. Here, the ground terminal GND may be the lowest potential of the entire circuit system. As in the previous embodiment, the first ring region 210 here may be a slightly square or rectangular structure, but is not actually limited to this shape, and may be designed according to actual needs.

In addition, the plurality of first conductive type doped regions 214 may include a plurality of regions separated by a certain interval and disposed in the first well region 202. In this embodiment, the first region 214a, the second region 214b and 214c are sequentially used as an example for illustration. Similarly, the plurality of second conductive type doped regions 224 may also include a plurality of regions separated by a certain interval and disposed in the first well region 202. In this embodiment, the first region 224a, the second region 224b and 224c are sequentially used as an example for illustration. Regarding the multiple first conductivity type doped regions 214 and the multiple second conductivity type doped regions 224, those skilled in the art can appropriately change or modify their quantity and electrical connection method based on the description of this embodiment without departing from the scope of implementation of the present invention.

In addition, as shown in FIG6A , gates 216a and 216b are disposed between the first region 214a, the second region 214b and the third region 214c of the plurality of first conductive type doped regions 214. Gates 226a and 226b are disposed between the first region 224a, the second region 224b and the third region 224c of the plurality of second conductive type doped regions 224.

In addition, as shown in FIG. 6A , at least the second region 214b of the plurality of first conductive type doped regions 214 and the second region 224b of the plurality of second conductive type doped regions 224 are electrically connected to each other. In addition, the first region 214a and the third region 214c of the plurality of first conductive type doped regions 214 are coupled to the high potential end. The first region 224a and the third region 224c of the plurality of second conductive type doped regions 224 are coupled to the ground end GND.

In addition, according to an embodiment of the present invention, the electrostatic discharge protection circuit structure may further include a second ring region 212 and a third ring region 222. The second ring region 212 is of the second conductivity type, disposed in the second well region 204, surrounds a plurality of first conductivity type doped regions 214, and is coupled to the high potential terminal. The third ring region 222 has the first conductivity type, is disposed in the first well region 202, surrounds a plurality of second conductivity type doped regions 224, and is coupled to the ground terminal GND. Similarly, the second ring region 112 and the third ring region 120 may be a slightly square or rectangular structure, but are not actually limited to this shape, and may be designed according to actual needs. In addition, as mentioned above, the second ring area 212 and the third ring area 222 can still be set selectively.

As an example, FIG6B shows that the first conductivity type and the second conductivity type are respectively illustrated as P-type doping and N-type doping. In this example, gates 216a and 216b can be used as trigger nodes of PMOS transistors, and gates 226a and 226b can be used as trigger nodes of NMOS transistors. As shown in FIG6B , the first region (in this example, P+ doping) 214a, the second region (in this example, P+ doping) 214b, the second well region (in this example, N well) 204 and the gate 216a of the plurality of first conductive type doped regions 214 constitute a first parasitic transistor P31 (i.e., a parasitic PMOS transistor), and the second region (in this example, N+ doping) 224b, the third region (in this example, N+ doping) 224c, the gate 226b and the first well region (in this example, P well) 202 of the plurality of second conductive type doped regions 224 constitute a second parasitic transistor N31 (i.e., a parasitic NMOS transistor), thereby constituting a first electrostatic discharge path ESD 1. The second well region 202, the substrate 200 and the first well region 202 form a third parasitic transistor P4 (i.e., a parasitic PNP transistor), thereby forming a second electrostatic discharge path ESD 2. The second region 214b, the third region 214c, the gate 216b and the second well region 204 in the plurality of first conductive type doped regions 214 form a fourth parasitic transistor P32 (i.e., a parasitic PNP transistor), and the first region 224a, the second region 224b, the gate 226a and the first well region 202 in the plurality of second conductive type doped regions 224 form a fifth parasitic transistor N32, thereby forming a third electrostatic discharge path ESD 3. The fourth parasitic transistor P32 and the fifth parasitic transistor N32 form a silicon-controlled rectifier SCR.

In addition, the equivalent circuit diagram of the electrostatic discharge protection circuit structure shown in FIG6B is shown in FIG6C. In addition to adding gates 216a, 216b, 226a, and 226c, the parasitic transistors constituting the first electrostatic discharge path ESD 1 are composed of parasitic NMOS transistors N31 and parasitic PMOS transistors P31. The remaining parasitic transistor components are the same. In addition, in this embodiment, the triggering method and operation method of the first to third electrostatic discharge paths ESD 1~ESD 3 are the same as the previous embodiments, so they will not be described in detail here.

In summary, according to the electrostatic discharge protection circuit structure of the embodiment of the present invention, it provides three electrostatic discharge paths with different triggering voltages, so that electrostatic discharge can be further effectively performed. In addition, the parasitic silicon-controlled rectifier part in the electrostatic discharge protection circuit structure is triggered by the secondary current, so the transistor spacing in the parasitic silicon-controlled rectifier can be increased, thereby further increasing the holding voltage. In addition, by improving the electrostatic discharge performance, the area of the electrostatic discharge protection circuit structure can also be further reduced.

100: Base

102: First Well Area

104: Second well area

110: First Ring District

112: Second Ring Road

114: Multiple first conductivity type doped regions

114a, 114b, 114c: District 1, District 2, District 3

122: Multiple second conductivity type doped regions

122a, 122b, 122c: District 1, District 2, District 3

120: Third Ring Road

P11, P12, N11, N12, P2: parasitic transistors

GND: Ground terminal

Claims (15)

An electrostatic discharge protection circuit structure includes: a substrate; a first well region, having a first conductivity type, disposed in the substrate; a second well region, having a second conductivity type, disposed in the first well region; a first ring region, having the first conductivity type, disposed in the first well region, and coupled to a ground terminal; a plurality of first conductivity type doped regions, disposed in the second well region, and at least including a first, second, and third region in sequence, wherein the first region and the third region are coupled to a high potential terminal; and a plurality of second conductivity type doped regions, disposed in the first well region, and at least including a first, second, and third region in sequence, wherein the first region and the third region are coupled to the ground terminal, wherein at least the second region of the plurality of first conductivity type doped regions and the plurality of second conductivity type doped regions are coupled to the ground terminal. The second region of the doped region is electrically connected to each other, wherein the first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic discharge path, the second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path, and the second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path. The electrostatic discharge protection circuit structure as described in claim 1 further includes: a second ring region having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high potential end; and a third ring region having the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground end. The electrostatic discharge protection circuit structure as described in claim 2, wherein the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type. The electrostatic discharge protection circuit structure as described in claim 1, wherein each of the plurality of first conductive type doped regions is arranged at a certain interval in the first direction of the substrate and extends in a second direction perpendicular to the first direction. The electrostatic discharge protection circuit structure as described in claim 1, wherein the triggering voltage of the first electrostatic discharge path is greater than the triggering voltage of the second electrostatic discharge path, and the triggering voltage of the second electrostatic discharge path is less than the triggering voltage of the third electrostatic discharge path. The electrostatic discharge protection circuit structure as described in claim 5, wherein the holding voltages corresponding to the first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path are approximately equal. The electrostatic discharge protection circuit structure as described in claim 1, wherein the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier. An electrostatic discharge protection circuit structure includes: a substrate; a first well region having a first conductivity type and arranged in the substrate; a second well region having a second conductivity type and arranged in the first well region; a first ring region having the first conductivity type and arranged in the first well region and coupled to a ground terminal; a plurality of first conductivity type doped regions arranged in the second well region and at least including first, second and third regions in sequence, wherein the first region and the third region are coupled to a high potential terminal, and gates are arranged on the substrate and between the first, second and third regions in pairs; and a plurality of second conductivity type doped regions arranged in the first well region and at least including first, second and third regions in sequence, wherein the first region and the third region are coupled to the ground terminal, and gates are arranged on the substrate and between the first, second and third regions in pairs. The first conductive type doped region is a first conductive type doped region, wherein at least the second region of the plurality of first conductive type doped regions and the second region of the plurality of second conductive type doped regions are electrically connected to each other, wherein the first region, the second region and the second well region of the plurality of first conductive type doped regions constitute a first parasitic transistor, and the second region, the third region and the first well region of the plurality of second conductive type doped regions constitute a second parasitic transistor, thereby constituting a first electrostatic The second well region, the substrate and the first well region constitute a third parasitic transistor, thereby constituting a second electrostatic discharge path, and the second region, the third region and the second well region of the plurality of first conductive type doped regions constitute a fourth parasitic transistor, and the first region, the second region and the first well region of the plurality of second conductive type doped regions constitute a fifth parasitic transistor, thereby constituting a third electrostatic discharge path. The electrostatic discharge protection circuit structure as described in claim 8 further includes: a second ring region having the second conductivity type, disposed in the second well region, surrounding the plurality of first conductivity type doped regions, and connected to the high potential end; and a third ring region having the first conductivity type, disposed in the first well region, surrounding the plurality of second conductivity type doped regions, and connected to the ground end. The electrostatic discharge protection circuit structure as described in claim 9, wherein the first conductivity type is P type, the second conductivity type is N type, and the substrate is P type. In the electrostatic discharge protection circuit structure as described in claim 10, the gates disposed between the first, second and third regions of the plurality of first conductive type doped regions serve as PMOS trigger nodes, and the gates disposed between the first, second and third regions of the plurality of second conductive type doped regions serve as NMOS trigger nodes. The electrostatic discharge protection circuit structure as described in claim 8, wherein each of the plurality of first conductive type doped regions is arranged at a certain interval in the first direction of the substrate and extends in a second direction perpendicular to the first direction. An electrostatic discharge protection circuit structure as described in claim 8, wherein the triggering voltage of the first electrostatic discharge path is greater than the triggering voltage of the second electrostatic discharge path, and the triggering voltage of the second electrostatic discharge path is less than the triggering voltage of the third electrostatic discharge path. The electrostatic discharge protection circuit structure as described in claim 13, wherein the holding voltages corresponding to the first electrostatic discharge path, the second electrostatic discharge path and the third electrostatic discharge path are approximately equal. An electrostatic discharge protection circuit structure as described in claim 8, wherein the fourth and fifth parasitic transistors of the third electrostatic discharge path constitute a silicon-controlled rectifier.

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