TWI851495B - Page buffer circuit and operating method thereof adapted for page read device - Google Patents

Abstract

A page buffer circuit adapted for a page-read device which including a memory array having several pages and several bit lines. The page buffer circuit comprises the following elements. First latches, receive a weight-vector from a corresponding one of the pages through the bit lines, and import an input-vector through a data input/output path. The weight-vector has a plurality of weight bit-data, and the input-vector has a plurality of input bit-data. Second latches, store the input bit-data of the input-vector. Logic operation units, coupled to the first latches to receive the weight bit-data, and coupled to the second latches to receive the input bit-data, perform a logic operation of the input bit-data and the weight bit-data to generate a logic operation result. The logic operation result is sent to one the first latches. A control circuit, selectively enables the logic operation units to perform the logic operation.

Description

Page buffer circuit suitable for page reading device and its operation method

The present disclosure relates to a semiconductor device, and more particularly to a page buffer circuit for a memory device and an operating method thereof.

With the rise of artificial intelligence technology, various basic operations required for artificial intelligence computing have been developed, such as vector-vector multiplication (VVM) and multiply-accumulate (MAC). Based on the high-speed access characteristics of memory, VVM operations and MAC operations can be achieved through in-memory-computing (IMC) performed by the memory.

However, when the bit width of VVM operations and MAC operations is larger (i.e., performing operations on multiple bits), the execution time required for in-memory operations will increase significantly.

To address the above issues, an improved page read and page buffer mechanism is needed to read the page data stored in the memory array more efficiently and cooperate with the pipeline operation mechanism to reduce the execution time of VVM and MAC operations.

According to one aspect of the present disclosure, a page buffer circuit is provided, which is adapted for a page read device, wherein the page read device includes a memory array having a plurality of pages and a plurality of bit lines. The page buffer circuit includes the following elements. A plurality of first latches, for receiving a weight vector from a corresponding one of the pages via the bit lines, and for importing an input vector via a data input/output path, wherein the weight vector has a plurality of weight bit data, and the input vector has a plurality of input bit data. A plurality of second latches, for storing the input bit data of the input vector. A plurality of logic operation units are coupled to the first latches to receive the weight bit data, and coupled to the second latches to receive the input bit data. Each of the logic operation units is used to perform a logic operation on a corresponding one of the input bit data and a corresponding one of the weight bit data to generate a logic operation result, and the logic operation result is transmitted to one of the first latches. A control circuit is used to selectively enable the logic operation units to perform the logic operation.

According to one aspect of the present disclosure, a method for operating a page buffer circuit adapted for a page read device is provided, wherein the page read device includes a memory array having a plurality of pages and a plurality of bit lines, and the method includes the following steps. A weight vector is received from a corresponding one of the pages via the bit lines by a plurality of first latches of the page buffer circuit, and an input vector is imported into the first latches via a data input/output path, wherein the weight vector has a plurality of weight bit data, and the input vector has a plurality of input bit data. The input bit data of the input vector is stored in a plurality of second latches of the page buffer circuit. The weight bit data are received from the first latch and the input bit data are received from the second latch by a plurality of logic operation units of the page buffer circuit. The logic operation corresponding to the input bit data and the weight bit data are executed by each logic operation unit to generate a logic operation result. The logic operation result is transmitted to one of the first latches. The logic operation units are selectively enabled to execute the logic operation by the control circuit of the page buffer circuit.

Other aspects and advantages of the present disclosure may be seen by reading the following drawings, detailed descriptions and claims.

21: Inductive amplifier

100: Lock register unit

200: decoding circuit

300:Logical operation circuit

400: Control circuit

1001,1001b,1001c: Page buffer circuit

1500:Memory array

1800: Accumulation circuit

2000: Memory devices

31,32,33,34,3(N-2),3(N-1): Logical Operation Unit

311,312,314,321,322,324,331,332,334: Input terminal

341,342,344: Input port

313,323,333,343: output port

42: Multiplexer

426: Input port

421,422,423,424: Input port

425: Output port

PB: Page Buffer Unit

pg(0),pg(m+1),pg(m):page

BL1, BL2, BL(M-1), BLM: bit lines

P1: Data input/output path

In: Input vector

We: weight vector

In(0)~In(3): bit data

We(0)~We(3): bit data

L1, L2, L3, L4, L5: lock register

L(N-1),LN: latch

DL, WDL, CDL: lock register

T1~T4: operation cycle

t1~t11: time point

t2’~t10’: time point

t2”~t7”: time point

T_ac_1,T_ac_2: Period

T_im_1~T_im_4: Period

T_op_1~T_op_3: Period

T_rd_1,T_rd_2: Period

T_int_rd_1,T_int_rd_2: period

S100~S118,S200~S206,S300~S308: Steps

S400~S412,S600~S610: Steps

Figure 1 is a circuit diagram of a memory device 2000 according to an embodiment of the present disclosure.

Figure 2A is a circuit diagram of a page buffer circuit 1001 according to an embodiment of the present disclosure.

Figure 2B is a circuit diagram of a page buffer circuit 1001b of another embodiment of the present disclosure.

Figure 2C is a circuit diagram of a page buffer circuit 1001c of another embodiment of the present disclosure.

Figure 3 is a schematic diagram of the basic operation of the page buffer circuit 1001.

Figure 4A is a flow chart of the main procedures of the VVM/MAC operation performed by the page buffer unit PB and the accumulation circuit 1800.

Figure 4B is a flowchart of the weight vector We reading procedure.

Figure 4C is a flowchart of the import procedure of the input vector In.

Figure 4D is a flowchart of VVM operation.

Figures 5A to 5H are schematic diagrams of the operation of the page buffer circuit 1001.

FIG. 6 is a flow chart of another embodiment of the VVM/MAC operation performed by the page buffer unit PB and the accumulation circuit 1800.

FIG. 7 is a timing diagram of the operation of the page buffer circuit 1001 of the embodiment of FIGS. 5A to 5H.

Figure 8 is a timing diagram of the operation of a vector-vector multiplier-adder as a comparison example.

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Please refer to FIG. 1, which is a circuit diagram of a memory device 2000 according to an embodiment of the present disclosure. The memory device 2000 includes a memory array 1500, a page buffer unit PB, and an accumulation circuit 1800. The memory device 2000 has a configuration suitable for performing a page read operation (e.g., has a page read feature), so the memory device 2000 can be referred to as a "page read device". Correspondingly, the memory array 1500 is suitable for page read operations. For example, the type of the memory array 1500 may be a non-volatile memory or a volatile memory, including: NAND flash memory, NOR flash memory, phase change memory (PCM), dynamic random access memory (DRAM), static random access memory (SRAM) or magnetoresistive random access memory (MRAM). The memory array 1500 may have a two-dimensional (2D) structure or a three-dimensional (3D) structure. The memory array 1500 may also have a single-plane structure or a multi-plane structure.

The memory array 1500 includes a plurality of pages, for example, page pg(1), ..., page pg(m), and page pg(m+1). Each page includes a plurality of memory blocks (not shown in the figure), and each memory block includes a plurality of memory cells. The memory cells may be SLC cells (single-order memory cells), MLC cells (second-order memory cells), TLC cells (third-order memory cells), QLC cells (fourth-order memory cells), or PLC cells (fiveth-order memory cells), etc. The memory cells are used to store data, for example, weight data. In this embodiment, one page stores a weight vector We.

The memory array 1500 is accessed via a plurality of bit lines, such as M bit lines BL1, BL2, BL3, BL4, ..., BL(M-1) and BLM. The page buffer unit PB can perform a page-read operation on pages pg(1) to pg(m+1) of the memory array 1500. The page buffer unit PB includes a plurality of page buffer circuits, such as M page buffer circuits 1001, 1002, 1003, 1004, ..., 100(M-1) and 100M. These page buffer circuits 1001 to 100M have the same number "M" as the bit lines BL1 to BLM. Page buffer circuits 1001~100M are coupled to bit lines BL1~BLM respectively. The weight vector We stored in pages pg(1)~pg(m+1) can be read to page buffer circuits 1001~100M via the corresponding bit lines BL1~BLM.

The weight vector We may have a bit width "N", where "N" is less than or equal to the number "M". The weight vector We includes bit data We _x (0), We _x (1), ..., We _x (N-1) stored in one of the pages pg(1)~pg(m+1) of the memory array 1500. The bit width "N" represents the number of bits of the weight vector We, and the parameter "x" represents the xth dimension. For example, page pg(1) has a data size of 16KB, and page pg(1) can store a total of 64 weight vectors We, each weight vector We has a bit width of "4" and a dimension of "512". The bit data We _j (n) is the bit data of the jth bit and the nth dimension. In the following paragraphs, the bit width is "4" (i.e., N=4) and the first dimension (i.e., x=1) is used as an example for explanation. The bit data _Wei (n) of the weight vector We includes bit data We(0), We(1), We(2), and We(3), and the four page buffer circuits 1001~1004 in the page buffer unit PB are used to process the bit data We(0)~We(3) accordingly. The bit data We(0)~We(3) can be provided to the page buffer circuits 1001~1004 via the bit lines BL1~BL4.

Each of the page buffer circuits 1001-1004 is coupled to a data input/output path, for example, the page buffer circuit 1001 is coupled to the data input/output path P1, the page buffer circuit 1002 is coupled to the data input/output path P2, the page buffer circuit 1003 is coupled to the data input/output path P3, and the page buffer circuit 1004 is coupled to the data input/output path P4 (not shown in FIG. 1). The data input/output paths P1-P4 may correspond to the bit lines BL1-BL4. Furthermore, an input vector In having a bit width of "4" is imported into one of the page buffer circuits 1001 to 1004 through the corresponding data input/output paths P1 to P4. Each of the page buffer circuits 1001 to 1004 performs a logical operation on the input vector In and the weight vector We.

Page buffer circuits 1001-1004 are coupled to accumulation circuit 1800. Accumulation circuit 1800 performs accumulation operation on the result of the logic operation performed by page buffer circuits 1001-1004. The logic operation of page buffer circuits 1001-1004 is combined with the accumulation operation of accumulation circuit 1800 to form a vector-vector multiplication (also called "vector-vector-multiply, VVM") operation.

Next, please refer to FIG. 2A, which is a circuit diagram of a page buffer circuit 1001 of the embodiment of FIG. 1 of the present disclosure. The page buffer circuit 1001 is coupled to the memory array 1500 via the bit line BL1. The page buffer circuit 1001 includes a latch circuit 100, a decoding circuit 200, a logic operation circuit 300, and a control circuit 400. The latch circuit 100 includes, for example, a plurality of latches, such as eight latches DL, WDL, CDL, and L1~L5. The latch DL can be referred to as a "first stage latch", which is disposed at the first stage (or first level) of the latch circuit 100. The latch WDL may be referred to as a "weight latch", which is set at an address between latch L1 and latch L2. The latch CDL may be referred to as a "last stage latch", which is set at the last stage (or the last stage) of the latch circuit 100. The latches L2 to L5 are set at addresses between the latch WDL and latch CDL, and the latches L2 to L5 are set at consecutive addresses. The logic operation circuit 300 includes a plurality of logic operation units 31 to 34. The number of logic operation units 31 to 34 is equal to the number of latches L2 to L5 (which is "4").

The latch WDL may be selectively set according to the design constraint of the page buffer circuit 1001. If the design constraint is that the delay (i.e., execution time) of executing the read procedure of the weight vector We is less than the delay of executing the operation procedure of the VVM of the weight vector We and the input vector In, the latch WDL may be set in the page buffer circuit 1001. If the delay of the read procedure of the weight vector We does not need to be considered, the latch WDL is not set.

The bit line BL1 is coupled to the decoding circuit 200 via the sensing amplifier (SA) 21, and the decoding circuit 200 is coupled to the latch DL. The data transmitted by the bit line BL1 is processed by the sensing amplifier 21 and then transmitted to the decoding circuit 200 for decoding. For example, if the memory cells of the memory array 1500 are TLC cells, the decoding circuit 200 decodes the 3-bit data of each TLC cell. In other examples, the memory cells of the memory array 1500 can be SLC cells, MLC cells, QLC cells, or PLC cells. If the memory cells are SLC cells, the decoding circuit 200 does not need to be set.

The logic operation unit 31 has input terminals 311, 312 and 314 and an output terminal 313. The input terminal 311 is coupled to the lock L2, and the input terminal 312 is coupled to the lock WDL. The logic operation unit 31 performs a logic operation according to the data stored in the lock L2 and the data stored in the lock WDL, such as a logic "AND" operation, a logic "OR" operation, a logic "exclusive OR" operation or a logic "anti-exclusive OR" operation. The control circuit 400 transmits a control signal to the input terminal 314 of the logic operation unit 31 to enable the logic operation unit 31 to perform logic operation. The operation result is transmitted to the latch CDL via the output terminal 313.

The operation mechanism of the logic operation units 32, 33 and 34 and the coupling method of their input terminals and output terminals are similar to those of the logic operation unit 31. For example, the input terminals 321, 331 and 341 of the logic operation units 32, 33 and 34 are coupled to the latches L3, L4 and L5 respectively. The input terminals 322, 332 and 342 of the logic operation units 32, 33 and 34 are coupled to the latch WDL. The logic operation units 32, 33 and 34 perform logic operations according to the data of the latches L3, L4 and L5 and the data of the latch WDL respectively. In this embodiment, the logic operation units 31-34 all perform the same type of logic operation, for example, all perform a logic "and" operation. The output terminals 313-343 of the logic operation units 31-34 are commonly coupled to the latch CDL. The control circuit 400 transmits a control signal to the input terminals 314-344 of the logic operation units 31-34. In the same operation cycle, only one of the logic operation units 31-34 transmits the operation result to the latch CDL.

The data input/output path P1 is coupled to the latch CDL. The calculation result stored in the latch CDL is transmitted to the external circuit (such as the accumulation circuit 1800) via the data input/output path P1.

Next, please refer to FIG. 2B, which is a circuit diagram of a page buffer circuit 1001b of another embodiment of the present disclosure. The page buffer circuit 1001b of the present embodiment can be provided with more latches, such as N latches L1~LN, according to design requirements or design restrictions. Correspondingly, the page buffer circuit 1001b is provided with (N-1) logic operation units 31~3(N-1) to respectively perform logic operations on the data of the latches L2~LN and the data of the latch WDL.

Next, please refer to FIG. 2C, which is a circuit diagram of a page buffer circuit 1001c of another embodiment of the present disclosure. The page buffer circuit 1001c of this embodiment further includes a multiplexer 42, which selects the operation result of one of the logic operation units 31-34 to be transmitted to the latch CDL, without the need to enable and select the logic operation units 31-34 by the control signal of the control circuit 400.

The output terminals 313, 323, 333 and 343 of the logic operation units 31, 32, 33 and 34 are respectively coupled to the input terminals 421, 422, 423 and 424 of the multiplexer 42 to transmit the operation results. The input terminal 426 of the multiplexer 42 receives the control signal of the control circuit 400 to select the operation result received by one of the input terminals 421, 422, 423 and 424 to be transmitted to the output terminal 425, and then transmitted to the latch CDL.

Next, please refer to Figure 3, which is a schematic diagram of the basic operation of the page buffer circuit 1001. The page buffer circuit 1001 performs logical operations on the input vector In and the weight vector We. The bit width of the input vector In is "N", and the input vector In includes N bits of data In(0), In(1), ..., and In(N-1). The bit data In(0)~In(N-1) of the input vector In are sequentially imported into the page buffer circuit 1001 through the data input/output path P1.

On the other hand, the weight vector We is stored in the memory array 1500. The bit width of the weight vector We is also equal to "N" and includes N bit data We(0), We(1), ..., and We(N-1). The bit data We(0)~We(N-1) of the weight vector We are stored in one page of the memory array 1500 and read in parallel to the corresponding page buffer circuit through the corresponding bit line. Taking the bit width "N" equal to "4" as an example, the bit data We(0) of the weight vector We is read to the corresponding page buffer circuit 1001, the bit data We(1) is read to the corresponding page buffer circuit 1002, the bit data We(2) is read to the corresponding page buffer circuit 1003, and the bit data We(3) is read to the corresponding page buffer circuit 1004.

Then, in each of the page buffer circuits 1001-1004, partial-product operations are sequentially performed on the bit data of the input vector In and the corresponding bit data of the weight vector We.

Then, the page buffer circuit 1001 transmits the operation result of the partial product to the accumulation circuit 1800. The accumulation circuit 1800 performs the weighted accumulation operation in a sequential manner to obtain the final operation result of the VVM/MAC operation.

Next, please refer to Figures 4A to 4D, which are flow charts of the VVM/MAC operation performed by the page buffer unit PB and the accumulation circuit 1800, and refer to Figures 5A to 5H for schematic diagrams of the operation of the page buffer circuit 1001. Figures 4A to 4D and 5A to 5H are explained by taking the case where the bit width of the input vector In and the weight vector We are both equal to "4" and the logic operation units 31 to 34 all perform the logic "and" operation as an example.

First, please refer to FIG. 4A , which is a flow chart of the main procedures of the VVM/MAC operation performed by the page buffer unit PB and the accumulation circuit 1800. In step S100, the input vector In is imported into the page buffer circuit 1001 via the corresponding bit line (e.g., bit line BL1). Then, in step S102, it is confirmed that the input vector In has been imported. On the other hand, step S104 is executed: the weight vector We is read into the page buffer circuit 1001. Step S104 can be executed synchronously with step S100, or before or after step S100. The weight vector We is originally stored in the current page (e.g., page pg(m)) of the memory array 1500. The weight vector We is read to the page buffer circuit 1001 via the bit line BL1, and the weight vector We is decoded via the decoding circuit 200. In addition, the corresponding bit data of the weight vector We (e.g., We(0)) is stored in the corresponding latch DL of the page buffer circuit 1001.

In the embodiment of FIG. 4A , the design constraint of the page buffer circuit 1001 is that the latency of the read process of the weight vector We (i.e., the required execution time) is less than the latency of the VVM/MAC operation process of executing the weight vector We and the input vector In. Therefore, the process of FIG. 4A includes steps S106, S110 and S112: the weight vector We stored in the latch DL is transferred to the latch WDL. More specifically, in steps S106, S110 and S112, the weight vector We is selectively transferred from the latch DL to the latch WDL according to the value of the flag. The weight vector We is transferred from the latch DL to the latch WDL in the page buffer circuit 1001 in the form of "internally transfer".

First, in step S106, determine whether the value of the flag is equal to "0". If the determination result is "yes", execute step S110: trigger the value of the flag to "1". If the determination result is "no", re-execute step S106.

When the value of the flag in step S110 is triggered to "1", it means that the weight vector We should be transferred to the latch WDL, and then step S112 is executed: the weight vector We is transferred from the latch DL to the latch WDL. Then, step S114 is executed: the VVM operation of the weight vector We and the input vector In is performed inside the page buffer circuit 1001. The VVM operation of step S114 may include partial product operation and accumulation operation. First, the partial product operation is performed as follows: the partial product operation of the bit data of the weight vector We and the corresponding bit data of the input vector In is sequentially executed. For example, a partial product operation of bit data We(0) and bit data In(0) is performed, a partial product operation of bit data We(0) and bit data In(1) is performed, and then a partial product operation of bit data We(0) and bit data In(2) is performed, and so on. Furthermore, the accumulation operation is performed as follows: the results of the partial product operations are added up. For example, the product of bit data We(0) and bit data In(0) is added to the product of bit data We(0) and bit data In(1), and then added to the product of bit data We(0) and bit data In(2), and so on.

Then, execute step S116: determine whether the partial product operation of the weight vector We and each bit data of the input vector In has been completed. If the judgment result of step S116 is "yes", execute step S118: determine whether there is a new request, which is used to request the execution of the operation of the next input vector In and the weight vector We of the first page pg(1). If the judgment result of step S116 is "no", re-execute step S108: reset the flag to "0".

In step S118, if the judgment result is "No", the process ends. If the judgment result is "Yes", step S100 is re-executed to import the new input vector In into the page buffer circuit 1001, and step S104 is synchronously executed to read the new weight vector We' into the page buffer circuit 1001.

Next, please refer to FIG. 4B, which is a flowchart of the reading procedure of the weight vector We (i.e., the detailed process of step S104 in FIG. 4A). The process of FIG. 4B can be explained in conjunction with the schematic diagram of the operation of the page buffer circuit 1001 in FIG. 5A. First, execute step S200: read the weight vector We stored in the current page (e.g., page pg(m)) from the memory array 1500. Then, execute step S202: decode the weight vector We by the decoding circuit 200.

Then, execute step S204: the corresponding bit data of the decoded weight vector We is stored in the corresponding register DL of the page buffer circuit 1001~1004. For example, the bit data We(0) is stored in the register DL of the page buffer circuit 1001, the bit data We(1) is stored in the register DL of the page buffer circuit 1002, the bit data We(2) is stored in the register DL of the page buffer circuit 1003, and the bit data We(3) is stored in the register DL of the page buffer circuit 1004.

Then, execute step S206: trigger the value of the flag to "1", and transfer the weight vector We stored in the latch DL to the latch WDL. The latches WDL of the page buffer circuits 1001~1004 store bit data We(0)~We(3) respectively. For example, the latch WDL of the page buffer circuit 1001 stores bit data We(0), the latch WDL of the page buffer circuit 1002 stores bit data We(1), the latch WDL of the page buffer circuit 1003 stores bit data We(2), and the latch WDL of the page buffer circuit 1004 stores bit data We(3).

Next, please refer to Figure 4C, which is a flowchart of the import process of the input vector In (i.e., the detailed process of step S100 in Figure 4A). The process of Figure 4C can be explained in conjunction with the schematic diagram of the operation of the page buffer circuit 1001 in Figures 5B to 5D.

First, referring to FIG. 5B, in step S300 of FIG. 4C, the first bit data In(0) of the input vector In is imported into the latch CDL via the corresponding data input/output path P1. At this time, the initial value of the count value cnt is "0". Then, step S302 is executed: the bit data In(0) of the input vector In is stored from the latch CDL to the corresponding latch L(i) (e.g., latch L2). Then, in step S304, it is determined whether the count value cnt is equal to the bit width N of the input vector In (N in this embodiment is equal to "4"). If the judgment result is "No", it means that the bit data of the input vector In has not been fully imported into the page buffer circuit 1001, then execute step S306: increment the count value cnt from "0" to "1". Then, re-execute step S300.

Meanwhile, referring to FIG. 5C, in the re-executed step S300, the second bit data In(1) of the input vector In is transmitted to the latch CDL via the data input/output path P1. Then, step S302 is executed: the bit data In(1) of the input vector In is stored from the latch CDL to the corresponding latch L3. Then, step S304 is executed: it is determined whether the count value cnt is equal to the bit width "4" of the input vector In. If the determination result is "no", step S306 is executed to increase the count value cnt to "2", and step S300 is re-executed.

Similarly, in the re-executed steps S300 to S306, the other two bits of data In(2) and In(3) of the input vector In are transmitted to the latch CDL via the input/output path P1 of the bit line BL1, and then stored in the corresponding latches L4 and L5. Referring to FIG. 5D, at this time, the latches L2~L5 have respectively stored the bit data In(0)~In(3) of the input vector In. And the count value cnt has been incremented to "4". Then, execute step S308: reset the count value cnt to "0".

In other examples, bit data In(0)~In(3) of input vector In can be stored in registers L2~L5 according to different orders. For example, bit data In(0) can be stored in register L3, bit data In(1) can be stored in register L2, and so on.

Next, please refer to Figure 4D, which is a flowchart of the VVM operation (i.e., the detailed process of step S114 in Figure 4A). The process of Figure 4D can be explained in conjunction with the schematic diagram of the operation of the page buffer circuit 1001 in Figures 5E to 5H.

First, execute step S400: the control circuit 400 controls the enable state of the logic operation unit 31-34, so that the logic operation unit 31-34 selectively performs logic operations in different operation cycles. In this embodiment, the control circuit 400 can control the enable state of the logic operation unit 31-34 according to a finite-state-machine (FSM), so as to enable the logic operation unit 31, 32, 33, 34 to perform logic operations in operation cycles T1, T2, T3, T4 to generate operation results. For example, as shown in Figure 5E, in operation cycle T1, the logic operation unit 31 is enabled to perform a logic operation (e.g., a logic "and" operation) on the bit data We(0) and the bit data In(0) to generate the operation result In(0)·We(0). At the same time, the weight vector We' of the next page pg(m+1) of the memory array 1500 is read to the page buffer circuit 1001 via the bit line BL1.

Then, execute step S402: store the operation result In(0) and We(0) of the logic operation unit 31 into the latch CDL. At the same time, the decoding circuit 200 decodes the weight vector We’.

Then, execute step S404: output the operation result In(0) and We(0) of the logic operation unit 31 from the latch CDL to the accumulation circuit 1800 to perform the accumulation operation. At the same time, the decoded weight vector We’ is stored in the latch DL.

Then, execute step S406: determine whether the count value cnt is equal to the bit width "4". If the judgment result is "no", execute step S408 to increment the count value cnt. Then re-execute step S400 to step S404 (see Figure 5F): In the next operation cycle T2, the control circuit 400 enables another logic operation unit 32 to perform a logical "and" operation of the bit data We(0) and the bit data In(1) to generate the operation result In(1). We(0). In addition, the operation result In(1). We(0) is transmitted to the latch CDL and then output to the accumulation circuit 1800.

Similarly, if it is determined in step S406 that the count value cnt is still not equal to the bit width "4", then step S400 to step S404 are executed again. As shown in Figure 5G: In operation cycle T3, the logic operation unit 33 performs a logical "and" operation on the bit data We(0) and the bit data In(2) to generate the operation result In(2)·We(0), and transmits it to the latch CDL, and then outputs it to the accumulation circuit 1800 for accumulation operation. Next, as shown in 5H: In operation cycle T4, logic operation unit 34 performs a logical "AND" operation on bit data We(0) and bit data In(3) to generate an operation result In(3)．We(0), and transmits it to latch CDL, and then outputs it to accumulation circuit 1800.

If it is determined in step S406 that the count value cnt has reached the bit width "4", then step S410 is executed: the calculation result of the accumulation circuit 1800 is stored. Then step S412 is executed: the count value cnt is reset to "0".

On the other hand, see FIG. 6, which is a flow chart of another embodiment of the VVM/MAC operation performed by the page buffer unit PB and the accumulation circuit 1800. In the embodiment of FIG. 6, the page buffer circuit 1001 does not set the latch WDL without considering the delay of the reading process of the weight vector We, and executes step S606 after step S604 of FIG. 6: execute the VVM operation of the weight vector We and the input vector In. There is no need to transfer the weight vector We from the latch DL to the latch WDL.

Next, refer to FIG. 7, which is a timing diagram of the operation of the page buffer circuit 1001 of the embodiment of FIGS. 5A to 5H. The timing diagram of FIG. 7 can be explained in conjunction with the flow charts of FIGS. 4B, 4C and 4D. First, during the period of time points t0 to t4, the 4-bit data In(0) to In(3) of the input vector In are sequentially imported into the latch CDL and transmitted to the corresponding latches L2 to L5 (corresponding to steps S300 to S306 of FIG. 4C). For example, during the period T_im_1 from the time point t0 to t1, the bit data In(0) of the input vector In is imported into the latch CDL and transmitted to the latch L2. Then, during the time period T_im_2 from time point t1 to t2, the next bit data In(1) is imported into the latch CDL and transmitted to the latch L3. Then, during the time period T_im_3 from time point t2 to t3, the third bit data In(2) is imported into the latch CDL and transmitted to the latch L4. Then, during the time period T_im_4 from time point t3 to t4, the fourth bit data In(3) is imported into the latch CDL and transmitted to the latch L5. Each of the periods T_im_1 to T_im_4 has the same time length (e.g., 30.72μs), and the total time length of the periods T_im_1 to T_im_4 is 122.88μs (i.e., 4×30.72μs).

The page buffer circuit 1001 disclosed in the present invention is based on a "pipeline" operation mechanism. During the period from time point t0 to time point t3, the corresponding bit data of the weight vector We (e.g., We(0)) can be synchronously read into the latch DL and transmitted to the latch WDL (corresponding to step S200 to step S206 in FIG. 4B). For example, during the period T_rd_1 from time point t0 to t2', the weight vector We is first read into the latch DL. The time length of the period T_rd_1 is, for example, 70μs. Then, during the period T_int_rd_1 from time point t2' to t2", the weight vector We is transmitted to the latch WDL. The time length of the period T_int_rd_1 is, for example, 5μs.

Then, during the period T_op_1 from time point t4 to t4', the logic operation unit 31 performs a logic operation on the bit data We(0) and the bit data In(0) to generate the operation result In(0)．We(0), and stores the operation result In(0)．We(0) in the latch CDL (corresponding to steps S400 and S402 of Figure 4D). The time length of the period T_op_1 is, for example, 5μs.

Then, during the period T_ac_1 between time points t4' and t5, the accumulation circuit 1800 performs an accumulation operation according to the calculation results In(0) and We(0) (corresponding to step S404 in Figure 4D). The time length of the period T_ac_1 is, for example, 30.72μs. The calculation cycle T1 in Figure 5E may include the period T_op_1 and the period T_ac_1. Based on the pipeline operation mechanism, the weight vector We' of the next page pg(m+1) can be synchronously read starting from time point t4.

Next, during the period T_op_2 from time point t5 to t5', the logic operation unit 32 performs a logic operation on the bit data We(0) and the bit data In(1) to generate an operation result In(1)．We(0), and stores the operation result In(1)．We(1) in the latch CDL. Then, during the period T_ac_2 from time point t5' to t6, the accumulation circuit 1800 accumulates the operation result In(1)．We(0) to the operation result In(0)．We(0). The operation cycle T2 of FIG. 5F may include the period T_op_2 and the period T_ac_2. At the time point t6, the weight vector We' of the next page pg(m+1) can be stored in the latch DL. That is, during the time period from t4 to t6, T_rd_2 performs the storage of the weight vector We’ in the latch DL.

Similarly, in the subsequent time period T_op_3 from t6 to t6', the logic operation unit 33 performs a logic operation on the bit data We(0) and the bit data In(2), and stores the operation result in the latch CDL. Then, in the time period T_ac_3 from t6' to t7, the accumulation circuit 1800 performs accumulation. The operation cycle T3 of FIG. 5G may include the period T_op_3 and the period T_ac_3. Furthermore, the operation cycle T4 of Figure 5H may include the period T_op_4 and the period T_ac_4, wherein: the period T_op_4 from time point t7 to t7' is used to perform the logic operation of the bit data We(0) and the bit data In(3), and store the operation result to the latch CDL. Furthermore, the period T_ac_4 from time point t7' to t8 performs the accumulation operation according to the above logic operation result.

Then, during the period T_int_rd_2 from time point t8 to t9, the weight vector We’ of page pg(m+1) is transferred from the latch DL to the latch WDL.

Then, during the period from time point t9 to t9’, T_op_1 is used to perform the logical operation of the bit data We(0) and the bit data In(0) of the weight vector We’ of page pg(m+1), and during the period from time point t9’ to t10, T_ac_1 is used to perform the accumulation operation. Then, during the period from time point t10 to t10’, T_op_2 is used to perform the logical operation of the bit data We(0) and the bit data In(1) of the weight vector We’ of page pg(m+1), and during the period from time point t10’ to t11, T_ac_2 is used to perform the accumulation operation. Furthermore, based on the pipeline operation mechanism, the weight vector We" of the subsequent page pg(m+2) can be stored in the latch DL synchronously during the time period T_rd_3 from t9 to t11.

In one example, the page buffer circuit 1001 performs logical operations based on a bit width of "4" and a dimension of "512", and executes 512 VVM/MAC operations in total. The storage space of the page buffer circuit 1001 is, for example, 16KB (i.e., 16×1024×8=131072 bits). In order to execute operations with a bit width of "4" and a dimension of "512", 2048 memory cells in the memory array 1500 must be used (i.e., 4×512=2048). When executing a total of 512 VVM operations (each operation has a bit width of "4" and a dimension of "512"), it is necessary to read the weight vector We from 8 pages (for example, pages pg(m)~pg(m+7)), and the number of read requests R_rd is "8". Accordingly, the total execution time T_total of the VVM/MAC operation of dimension "512" is 1305.92μs, as shown in equations (1) and (2): T_total=(N×T_im_1)+{R_rd×[N×(T_op_1+T_ac_1)+T_int_rd_1]} (1)

1305.92μs=(4×30.72μs)+{8×[4×(5μs+30.72μs)+5μs]} (2)

Next, refer to FIG. 8, which is a timing diagram of the operation of a vector-vector multiplier-adder of a comparative example. The vector-vector multiplier-adder of the comparative example of FIG. 8 performs VVM/MAC operations according to a cycle-by-cycle mechanism. During the period T_im_1 from time point t0 to t1, the bit data In(0) of the input vector In is imported into a latch (not shown in the figure). During the period T_rd_1 from time point t1 to t2, the weight vector We is read into another latch (not shown in the figure). During the period T_op_1 from time point t2 to t2’, a logical operation is performed on the bit data We(0) and the bit data In(0) to generate the operation result In(0) We(0). During the period T_ac_1 from time point t2’ to t3, the accumulation circuit performs accumulation operation based on the operation result In(0) and We(0). Since the comparison example in Figure 8 is executed according to the cycle-by-cycle mechanism (rather than the pipeline operation mechanism disclosed in the present invention), T_im_1, T_rd_1, T_op_1 and T_ac_1 do not perform other operations synchronously during the period t0 to t3. Until the accumulation operation ends at the time point t3, the next bit data In(1) and bit data We(0) are imported, read and logically operated. For example, during the period T_im_2 from time point t3 to t3’, the next bit data In(1) of the input vector In is imported into the latch. During the period T_op_2 from time point t3’ to t3”, the logical operation of bit data We(0) and bit data In(1) is performed, and during the period T_ac_2 from time point t3” to t4, the accumulation operation is performed.

Similarly, in a cycle-by-cycle mechanism, T_im_3, T_op_3 and T_ac_3 perform the import, logic operation and accumulation operation of the input vector during the period of time points t4 to t5. Then, T_im_4, T_op_4 and T_ac_4 perform the import, logic operation and accumulation operation of the next input vector during the period of time points t5 to t6.

Then, during the time period from t6 to t8, T_im_1, T_rd_2 and T_ac_1 perform the import of the input vector, the reading of the weight vector of the next page, the logical operation and the accumulation operation.

The performance comparison is performed based on the timing diagram of the page buffer circuit 1001 disclosed in FIG. 7 and the timing diagram of the comparison example in FIG. 8. The page buffer circuit 1001 disclosed in the present invention operates according to the pipeline operation mechanism. While the bit data of the input vector In is imported during the period T_im_1~T_im_3, two operations can be executed synchronously: the first operation: during the period T_rd_1, the weight vector We of the current page pg(m) is stored in the latch DL. The second operation: during the period T_int_rd_1, the weight vector We is stored in the latch WDL in the form of internal transmission.

Furthermore, according to the pipeline operation mechanism, while the logical operation of bit data is performed in periods T_op_1 and T_op_2, and the accumulation operation is performed in periods T_ac_1 and T_ac_2, the weight vector We’ of the next page pg(m+1) can be synchronously stored in the latch DL in period T_rd_2.

Therefore, compared to the cycle-by-cycle mechanism of the comparison example in FIG. 8 , the total execution time required for the VVM/MAC operation performed by the page buffer circuit 1001 in cooperation with the accumulation circuit 1800 disclosed herein can be significantly reduced.

Although the present disclosure has been disclosed in detail with preferred embodiments and examples, it is understood that these examples are intended to be illustrative rather than restrictive. It is expected that a person with ordinary knowledge in the relevant technical field can think of various modifications and combinations, and the various modifications and combinations fall within the spirit of the present disclosure and the scope of the attached patent application.

21: Inductive amplifier

31,3(N-2),3(N-1): Logical Operation Unit

100: Lock register unit

200: decoding circuit

300:Logical operation circuit

400: Control circuit

1001b: Page buffer circuit

BL1: bit line

L1, L2, L(N-1), LN: latch

DL, WDL, CDL: lock register

P1: Data input/output path

Claims (20)

A page buffer circuit is adapted for a page reading device, wherein the page reading device includes a memory array having a plurality of pages and a plurality of bit lines, the page buffer circuit includes: a plurality of first latches, for receiving a weight vector from a corresponding one of the pages via the bit lines, and importing an input vector via a data input/output path, wherein the weight vector has a plurality of weight bit data, and the input vector has a plurality of input bit data, the first latches include a primary latch and a weight latch, wherein the primary latch receives one of the weight bit data, and the weight vector is delayed in response to a delay in a reading procedure of the weight vector. The latch receives the corresponding weight bit data from the first latch; a plurality of second latches are used to store the input bit data of the input vector; a plurality of logic operation units are coupled to the first latches to receive the weight bit data, and coupled to the second latches to receive the input bit data, each of the logic operation units The operation unit is used to perform a logic operation on a corresponding one of the input bit data and a corresponding one of the weight bit data to generate a logic operation result, and the logic operation result is transmitted to one of the first latches; and a control circuit is used to selectively enable the logic operation units to perform the logic operation. A page buffer circuit as described in claim 1, wherein the logical operations of the input bit data and the weight bit data together form the logical operations of the input vector and the weight vector. A page buffer circuit as described in claim 1, wherein the page buffer circuit operates in a plurality of operation calculation cycles, and the control circuit selectively enables one of the logic operation units in a corresponding one of the operation calculation cycles. The page buffer circuit as described in claim 1 further includes: a decoding circuit coupled to a corresponding one of the bit lines and used to decode the weight vector to obtain one of the weight bit data. A page buffer circuit as described in claim 4, wherein the first-level latch is coupled to the decoding circuit to receive a corresponding one of the weight bit data. The page buffer circuit as described in claim 5, wherein the weight latch further provides the corresponding weight bit data to the logic operation units. A page buffer circuit as described in claim 1, wherein the first latches include: a final latch coupled to the data input/output path to receive the corresponding input bit data. A page buffer circuit as described in claim 7, wherein the final latch provides the corresponding input bit data to the second latches. The page buffer circuit as described in claim 7, wherein the final latch is further coupled to the logic operation units to receive the logic operation results. A page buffer circuit as described in claim 9, wherein the page buffer circuit is coupled to an accumulation circuit, and the final latch provides the logic operation results to the accumulation circuit via the data input/output path. An operating method of a page buffer circuit adapted for a page read device, wherein the page read device includes a memory array having a plurality of pages and a plurality of bit lines, the operating method comprising: receiving a weight vector from a corresponding one of the pages via the bit lines through a plurality of first latches of the page buffer circuit, and receiving the weight vector via a data input/output The output path imports an input vector to the first latches, wherein the weight vector has a plurality of weight bit data, and the input vector has a plurality of input bit data, wherein one of the weight bit data is received by a first latch among the first latches, and one of the first latches is read in response to a delay in a reading process of the weight vector. The weight lock receives the corresponding weight bit data from the primary lock; the input bit data of the input vector are stored in a plurality of second locks of the page buffer circuit; the weight bit data are received from the first locks and the input bit data are received from the second locks by a plurality of logic operation units of the page buffer circuit; The logic operation unit performs a logic operation on a corresponding one of the input bit data and a corresponding one of the weight bit data to generate a logic operation result; transmits the logic operation result to one of the first latches; and selectively enables the logic operation units to perform the logic operation through a control circuit of the page buffer circuit. The operating method as described in claim 11, wherein the logical operations of the input bit data and the weight bit data together form the logical operations of the input vector and the weight vector. An operating method as described in claim 11, wherein the page buffer circuit operates with a plurality of operation calculation cycles, and the control circuit selectively enables one of the logic operation units in a corresponding one of the operation calculation cycles. The operating method as described in claim 11 further includes: decoding the weight vector by a decoding circuit of the page buffer circuit to obtain one of the weight bit data. The operating method as described in claim 14 further includes: receiving a corresponding one of the weight bit data from the decoding circuit via the first-level latch. The operating method as described in claim 15 further includes: providing the corresponding weight bit data to the logic operation units through the weight latch. The operating method as described in claim 11 further includes: receiving the corresponding input bit data from the data input/output path through a final-stage latch among the first latches. The operating method as described in claim 17 further includes: providing the corresponding input bit data to the second latches through the final latch. The operating method as described in claim 17 further includes: receiving the logical operation results through the final-stage latch. The operating method as described in claim 19, wherein the page buffer circuit is coupled to an accumulation circuit, and the operating method further includes: providing the logic operation results to the accumulation circuit via the data input/output path through the final-stage latch.

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