TWI850651B - Display device and driving method thereof - Google Patents

Abstract

A display device and driving method thereof are provided. The display device includes a display panel, a gate driver and a source driver. The display panel has a plurality of light emitting elements. The gate driver is configured to provide a plurality of gate driving signals to drive the plurality of light emitting elements, respectively. The source driver is configured to provide a plurality of source driving signals to a plurality of source lines. The source driver sequentially detects and stores a detection voltage on the source line according to the gate driving signal, and adjusts a light emitting time of the light emitting element according to the detection voltage.

Description

Display device and driving method thereof

The present invention relates to a display device, and more particularly to a display device and a driving method thereof.

With the advancement of electronic technology, consumer electronic products have become an essential tool in people's lives. In order to provide a good human-machine interface, it has become a trend to configure high-quality display devices on consumer electronic products.

In a conventional display device, when a display panel has process variation or has aged due to long-term use, the current flowing through the light-emitting element may change unexpectedly. In this case, the brightness of the display panel will be unstable, which will affect the quality of the display screen. Therefore, how to effectively reduce the impact of process variation and aging on the display panel to improve the display quality of the display screen will be an important topic for relevant technical personnel in this field.

The present invention provides a display device and a driving method thereof, which can effectively compensate for the brightness uniformity of a display panel and the aging phenomenon of a light-emitting element, thereby improving the display quality of a display screen.

The display device of the present invention includes a display panel, a gate driver and a source driver. The display panel has a plurality of light-emitting elements. The light-emitting elements are respectively coupled between a plurality of gate lines and a plurality of source lines. The gate driver is coupled to the gate line to provide a plurality of gate driving signals to drive the light-emitting elements respectively. The source driver is coupled to the source line to provide a plurality of source driving signals to the source line, wherein the source driver sequentially detects and stores a plurality of detection voltages on the source line according to the gate driving signals, and adjusts the light-emitting time of the light-emitting element according to the detection voltage.

The driving method of the display device of the present invention comprises: providing a display panel having a plurality of light-emitting elements; providing a gate driver, and making the gate driver provide a plurality of gate driving signals to drive the light-emitting elements respectively; providing a source driver, and making the source driver provide a plurality of source driving signals to a plurality of source lines; making the source driver detect and store a plurality of detection voltages on the source lines in sequence according to the gate driving signals; and making the source driver adjust the light-emitting time of the light-emitting elements according to the detection voltages.

Based on the above, the display device and the driving method thereof described in the embodiments of the present invention can detect and calculate multiple detection voltages on the source line through a source driver or an external processor. In addition, the source driver or the processor can adjust the time period of multiple pulse width modulation signals according to the detected multiple detection voltages. In this way, the source driver can control the current state of the corresponding current tank through the source drive signal to control the luminous time of the corresponding light-emitting element, thereby achieving the effect of compensating for the aging phenomenon of the light-emitting element and the brightness uniformity.

The term "coupled (or connected)" used throughout the specification of this case (including the scope of the patent application) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. In addition, wherever possible, elements/components/steps with the same number in the drawings and embodiments represent the same or similar parts. Elements/components/steps with the same number or the same terminology in different embodiments can refer to each other's related descriptions.

FIG1 is a schematic diagram of a display device according to an embodiment of the present invention. Referring to FIG1 , the display device 100 includes a display panel 110, a gate driver 120, a source driver 130, and a clock generator 180. In this embodiment, the display panel 110 includes a plurality of light-emitting elements D11-DNM. The light-emitting elements D11-DNM in the display panel 110 are arranged in a matrix and are disposed at the intersections of a plurality of source lines SL1-SLn and a plurality of gate lines GL1-GLn.

The gate driver 120 is coupled to the gate lines GL1-GLn of the display panel 110. The gate driver 120 can provide a plurality of gate driving signals GS1-GSn enabled in sequence to the display panel 110 through the plurality of gate lines GL1-GLn according to the scan control signal SCS to drive the plurality of light-emitting elements D11-DNM respectively.

On the other hand, the source driver 130 is coupled to the source lines SL1 ˜SLn of the display panel 110 . The source driver 130 can provide source driving signals DS1 ˜DSn to the display panel 110 through the source lines SL1 ˜SLn, respectively.

Generally speaking, the light-emitting elements D11-DNM in the display panel 110 can generate fixed currents (such as current slots I1-In shown in FIG. 1 ) on the corresponding source lines SL1-SLn according to the gate driving signals GS1-GSn and the source driving signals DS1-DSn, respectively, and the source driver 130 can control the current states of these current slots I1-In through the source driving signals DS1-DSn to control the light-emitting time and (or) light-emitting brightness of the light-emitting elements D11-DNM.

The clock generator 180 receives the original data signal DATA. The clock generator 180 can generate a scan control signal SCS to the gate driver 120 according to the original data signal DATA. The clock generator 180 can generate a start signal START, a clock signal Clock_ADC and a clock signal CLKP to the source driver 130 according to the original data signal DATA.

In the embodiment shown in FIG1 , the source driver 130 may include a voltage detection circuit 140, a compensation circuit 150, a pulse width modulation signal generator 160, and a driving circuit 170. It is worth mentioning that in other embodiments, the voltage detection circuit 140 and the compensation circuit 150 may be disposed outside the source driver 130 according to the design requirements of the display device 100, and the present invention is not particularly limited thereto.

Specifically, the voltage detection circuit 140 is coupled to the gate lines GL1 ˜GLn and the source lines SL1 ˜SLn of the display panel 110. The voltage detection circuit 140 can sequentially detect and store a plurality of detection voltages VD1 ˜VDn on the source lines SL1 ˜SLn according to the gate driving signals GS1 ˜GSn.

For example, when the light-emitting elements D11~D1M on the gate line GL1 are lit according to the gate drive signal GS1, and the gate drive signal GS1 at this time is the voltage VDD, the detection voltage VD1 on the source line SL1 is the voltage VDD minus the turn-on voltage VLED11 of the light-emitting element D11 (that is, VD1=VDD-VLED11), and the detection voltage VD2 on the source line SL2 is the voltage VDD minus the turn-on voltage VLED12 of the light-emitting element D12 (that is, VD2=VDD-VLED12), and the remaining detection voltages VD3~VDn can be deduced accordingly.

Similarly, when the light-emitting elements DN1-DNM on the gate line GLn are lit according to the gate drive signal GSn, and the gate drive signal GSn at this time is the voltage VDD, the detection voltage VDn on the source line SLn is the voltage VDD minus the conduction voltage VLEDNM of the light-emitting element DNM (i.e., VDn=VDD-VLEDNM), and the remaining detection voltages VD1-VDn-1 can be deduced in the same way. At this time, the voltage detection circuit 140 can detect and store multiple detection voltages VD1-VDn on the source lines SL1-SLn in sequence according to the gate drive signals GS1-GSn.

It is worth mentioning that in some other embodiments, the voltage detection circuit 140 may also receive the scanning control signal SCS, and sequentially detect and store a plurality of detection voltages VD1-VDn on the source lines SL1-SLn according to the scanning control signal SCS.

Then, after the voltage detection circuit 140 detects the detection voltages VD1-VDn in sequence according to the gate drive signals GS1-GSn, the voltage detection circuit 140 may convert the detection voltages VD1-VDn to generate converted detection voltages VD1'-VDn' and (or) detection voltages VD1"-VDn".

On the other hand, the compensation circuit 150 is coupled to the voltage detection circuit 140. The compensation circuit 150 can determine the operating status of the light-emitting elements D11-DNM in the display panel 110 according to the detection voltages VD1'-VDn' (and the detection voltages VD1"-VDn"), and generate a plurality of compensation control signals CCS1-CCSn according to the determination result.

For example, in some embodiments, the compensation circuit 150 can determine the aging degree of one or more light-emitting elements on the corresponding source lines SL1-SLn according to the detection voltages VD1'-VDn', VD1"-VDn" and a preset reference value. Furthermore, the compensation circuit 150 can generate compensation control signals CCS1-CCSn accordingly according to the multiple determination results.

In other embodiments, the compensation circuit 150 can determine the brightness uniformity of one or more light-emitting elements on the corresponding source lines SL1-SLn according to the detection voltages VD1'-VDn' and a preset reference value. Furthermore, the compensation circuit 150 can generate compensation control signals CCS1-CCSn according to the multiple determination results.

On the other hand, the pulse width modulation signal generator 160 is coupled to the compensation circuit 150 and the clock generator 180. The pulse width modulation signal generator 160 can generate the pulse width modulation signals PWM1-PWMn according to the original data signal DATA, the clock signal CLKP and the compensation control signals CCS1-CCSn. In this embodiment, the pulse width modulation signal generator 160 can adjust the time period of the pulse width modulation signals PWM1-PWMn respectively according to the compensation control signals CCS1-CCSn, so as to adjust the luminous time of the corresponding light-emitting element.

The driving circuit 170 is coupled to the pulse width modulation signal generator 160 and the source lines SL1-SLn. The driving circuit 170 can generate source driving signals DS1-DSn to the source lines SL1-SLn according to the pulse width modulation signals PWM1-PWMn. Thus, the source driver 130 can control the luminous time of the light-emitting elements D11-DNM respectively through the source driving signals DS1-DSn, so as to compensate for the brightness uniformity and aging state of the display panel 110.

It is worth mentioning that under other design requirements (in other embodiments), the gate driver 120 and the source driver 130 shown in FIG. 1 may also be integrated (or disposed) in the same integrated circuit die, and the present invention is not particularly limited thereto.

2A and 2B are schematic circuit diagrams of a voltage detection circuit according to the embodiment of FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 2A simultaneously. In this embodiment, when the display device 100 can compensate for the aging state of the light-emitting elements D11-DNM in the display panel 110, the voltage detection circuit 140 may include a plurality of analog-to-digital converters (ADCs) 141_1-141_n, a multiplexer 142, a voltage storage 143, and a voltage storage 144.

Specifically, the analog-to-digital converters 141_1-141_n are respectively coupled to the source lines SL1-SLn of the display panel 110 to respectively receive the detection voltages VD1-VDn. The analog-to-digital converters 141_1-141_n can respectively convert the detection voltages VD1-VDn in analog form into detection voltages VD1'-VDn' and VD1"-VDn" in digital form according to the clock signal Clock_ADC.

The multiplexer 142 is coupled to the analog-to-digital converters 141_1-141_n to receive the detection voltages VD1’-VDn’ and VD1”-VDn”. The voltage register 143 and the voltage register 144 are coupled to the multiplexer 142 to receive the detection voltages VD1’-VDn’ and VD1”-VDn” respectively. The voltage register 143 and the voltage register 144 are coupled to the gate lines GL1-GLn of the display panel 110 to receive the gate drive signals GS1-GSn.

For details on the implementation of the display device 100 compensating for the aging state of the light-emitting elements D11-DNM in the display panel 110, please refer to FIG. 1, FIG. 2A and FIG. 3A. FIG. 3A and FIG. 3B are flow charts of the operation method of the display device according to the embodiment of FIG. 1 of the present invention for performing aging compensation and brightness uniformity compensation. Specifically, in step S301, the display device 100 can be activated, and in step S302, a start signal START is received to perform related operation actions.

In step S303, the clock generator 180 may generate a scan control signal SCS based on the start signal START and according to the original data signal DATA, and the gate driver 120 may sequentially generate gate drive signals GS1-GSn to the gate lines GL1-GLn of the display panel 110 according to the scan control signal SCS during the first time period.

Next, in step S304, the voltage detection circuit 140 may detect and store a plurality of detection voltages VD1-VDn in the voltage storage 143 during the first time period. Specifically, in the embodiments of FIG. 1 and FIG. 2A , the analog-to-digital converters 141_1-141_n in the voltage detection circuit 140 may receive the detection voltages VD1-VDn from the source lines SL1-SLn during the first time period according to the clock signal Clock_ADC, and convert the detection voltages VD1-VDn into detection voltages VD1'-VDn'.

At this time, the multiplexer 142 can select to transmit the detection voltages VD1'-VDn' to the voltage register 143 according to the clock signal CLKP, and the voltage register 143 can sequentially store the detection voltages VD1'-VDn' according to the start signal START and the gate drive signals GS1-GSn.

Next, in step S305, the source driver 130 may determine whether the voltage storage 143 has stored the voltage states of the detection voltages VD1-VDn on the source lines SL1-SLn when the gate driving signals GS1-GSn are sequentially enabled in the first time period. When it is determined that the voltage storage 143 has completed the storage of all the detection voltages VD1-VDn, the display device 100 may continue to execute the operation of step S306, and when it is determined that the voltage storage 143 has not completed the storage of all the detection voltages VD1-VDn, the display device 100 may return to execute the operation of step S304.

In step S306, the source driver 130 may determine whether the start signal START is received in a second time interval after the first time interval. For example, the source driver 130 may detect whether the start signal START is received again after the display device 100 operates for a preset time interval or the display screen of the display panel 110 passes through a plurality of frames.

When it is determined that the start signal START is received during the second time interval, the display device 100 may continue to execute the operation of step S307, and when it is determined that the start signal START is not received during the second time interval, the display device 100 may repeatedly execute the operation of step S306.

In step S307, the gate driver 120 may sequentially generate gate driving signals GS1-GSn to the gate lines GL1-GLn of the display panel 110 according to the scan control signal SCS during the second time period.

Next, in step S308, the voltage detection circuit 140 may detect and store a plurality of detection voltages VD1-VDn in the voltage storage 144 during the second time period. Specifically, in the embodiments of FIG. 1 and FIG. 2A, the analog-to-digital converters 141_1-141_n in the voltage detection circuit 140 may receive the detection voltages VD1-VDn from the source lines SL1-SLn during the second time period according to the clock signal Clock_ADC, and convert the detection voltages VD1-VDn into detection voltages VD1"-VDn".

At this time, the multiplexer 142 can select to transmit the detection voltages VD1"-VDn" to the voltage register 144 according to the clock signal CLKP, and the voltage register 144 can sequentially store the detection voltages VD1"-VDn" according to the start signal START and the gate drive signals GS1-GSn.

Next, in step S309, the source driver 130 may determine whether the voltage storage 144 has stored the voltage states of the detection voltages VD1-VDn on the source lines SL1-SLn when the gate driving signals GS1-GSn are sequentially enabled during the second time period. When it is determined that the voltage storage 144 has completed the storage of all the detection voltages VD1-VDn, the display device 100 may continue to execute the operation of step S310, and when it is determined that the voltage storage 144 has not completed the storage of all the detection voltages VD1-VDn, the display device 100 may return to execute the operation of step S308.

In step S310, the compensation circuit 150 of the source driver 130 may compare the detection voltages VD1'-VDn' stored in the voltage register 143 and the detection voltages VD1"-VDn" stored in the voltage register 144 to generate a plurality of compensation control signals CCS1-CCSn. Specifically, in this embodiment, after the compensation circuit 150 receives the detection voltages VD1’~VDn’ and the detection voltages VD1”~VDn”, the compensation circuit 150 can calculate the voltage difference VB between the detection voltages VD1”~VDn” stored in the second time period and the detection voltages VD1’~VDn’ stored in the first time period under the same source line, so as to confirm the aging degree of the light-emitting element on the corresponding source line.

For example, if the compensation circuit 150 calculates that the voltage difference VB1 between the detection voltage VD1” and the detection voltage VD1’ is less than a preset reference value, it means that the aging state of one or more light-emitting elements among the light-emitting elements D11~DN1 corresponding to the source line SL1 is not higher than the standard value. At this time, the compensation circuit 150 can generate the compensation control signal CCS1 to the pulse width modulation signal generator 160 according to the calculation result.

In this case, the PWM signal generator 160 can shorten the time period of the PWM signal PWM1 according to the compensation control signal CCS1 (step S311), thereby shortening the luminous time of one or more luminous elements among the luminous elements D11-DN1 on the source line SL1.

In contrast, if the compensation circuit 150 calculates that the voltage difference VB1 between the detection voltage VD1” and the detection voltage VD1’ is greater than the reference value, it indicates that the aging state of one or more of the light-emitting elements D11-DN1 on the source line SL1 is higher than the standard value. At this time, the compensation circuit 150 can generate the compensation control signal CCS1 to the pulse width modulation signal generator 160 according to the calculation result.

In this case, the pulse width modulation signal generator 160 can extend the time period of the pulse width modulation signal PWM1 according to the compensation control signal CCS1 (step S311), thereby extending the luminous time of one or more light-emitting elements among the light-emitting elements D11-DN1 on the source line SL1. The operation details of the compensation circuit 150 comparing the detection voltages VD2'-VDn' stored in the voltage register 143 and the detection voltages VD2''-VDn" stored in the voltage register 144 to generate a plurality of compensation control signals CCS2-CCSn can be deduced accordingly.

Further, in step S311, after the pulse width modulation signal generator 160 generates a plurality of pulse width modulation signals PWM1-PWMn according to the compensation control signals CCS1-CCSn, the driving circuit 170 may generate source drive signals DS1-DSn to the source lines SL1-SLn according to the pulse width modulation signals PWM1-PWMn. In this way, the source driver 130 of the present embodiment may confirm the aging state of one or more light-emitting elements of the display panel 110 according to the indication of the compensation control signals CCS1-CCSn, and adjust the time period of the pulse width modulation signals PWM1-PWMn accordingly. Furthermore, the source driver 130 can control the current states of the corresponding current slots I1-In through the source driving signals DS1-DSn to control the luminous time of the corresponding light-emitting elements, thereby achieving the effect of compensating for the aging phenomenon of the light-emitting elements.

On the other hand, referring to FIG. 1 and FIG. 2B , in another embodiment, when the display device 100 can compensate for the brightness uniformity of the light-emitting elements D11-DNM in the display panel 110, the voltage detection circuit 140 may include a plurality of analog-to-digital converters 141_1-141_n and a voltage storage 143.

Please refer to FIG. 1 , FIG. 2B and FIG. 3B for details of how the display device 100 compensates for the brightness uniformity of the light-emitting elements D11 to DNM in the display panel 110. The operation of steps S320 to S322 in FIG. 3B can be deduced from the relevant description of steps S301 to S303 in FIG. 3A , and thus will not be described in detail.

In step S323, the voltage detection circuit 140 can detect and store a plurality of detection voltages VD1-VDn in the voltage storage 143. Specifically, the voltage storage 143 can store the detection voltages VD1'-VDn' in sequence according to the gate driving signals GS1-GSn.

Next, in step S324, the source driver 130 may determine whether the voltage register 143 has stored the voltage states of the detection voltages VD1-VDn on the source lines SL1-SLn when the gate driving signals GS1-GSn are enabled in sequence. When it is determined that the voltage storage 143 has completed the storage of all the detection voltages VD1-VDn, the display device 100 may continue to execute the operation of step S325, and when it is determined that the voltage storage 143 has not completed the storage of all the detection voltages VD1-VDn, the display device 100 may return to execute the operation of step S323.

In step S325, the compensation circuit 150 of the source driver 130 can calculate the difference percentage between the detection voltage on each source line and the average detection voltage of the multiple detection voltages VD1-VDn on the multiple source lines SL1-SLn according to the detection voltages VD1'-VDn' and the number of source lines SL1-SLn to generate multiple compensation control signals CCS1-CCSn.

Specifically, in this embodiment, the compensation circuit 150 may first sum the detection voltages VD1-VDn on the source lines SL1-SLn to obtain a total detection voltage VDT, and calculate the average detection voltage VDA of the display panel 110 according to the total detection voltage VDT and the number n of the source lines SL1-SLn, as shown in the following formula (1): VDT/n=VDA              （1）

Then, the compensation circuit 150 can calculate the difference percentage PD between the detection voltage on each source line and the average detection voltage VDA, and generate a compensation control signal by comparing the difference percentage PD with a preset reference value.

For example, if the compensation circuit 150 determines that the difference percentage PD1 between the detection voltage VD1 corresponding to one or more light-emitting elements on the source line SL1 and the average detection voltage VDA is less than the reference value, it means that the conduction speed of one or more light-emitting elements D11-DN1 corresponding to the source line SL1 is faster. At this time, the compensation circuit 150 can generate the compensation control signal CCS1 to the pulse width modulation signal generator 160 according to the calculation result.

In this case, the PWM signal generator 160 can shorten the time period of the PWM signal PWM1 according to the compensation control signal CCS1 (step S326), so as to shorten the luminous time of one or more luminous elements among the luminous elements D11-DN1 on the source line SL1.

In contrast, if the compensation circuit 150 determines that the difference percentage PD1 between the detection voltage VD1 corresponding to one or more light-emitting elements on the source line SL1 and the average detection voltage VDA is greater than the reference value, it means that the conduction speed of one or more light-emitting elements among the light-emitting elements D11-DN1 corresponding to the source line SL1 is slower. At this time, the compensation circuit 150 can generate the compensation control signal CCS1 to the pulse width modulation signal generator 160 according to the calculation result.

In this case, the PWM signal generator 160 may extend the time period of the PWM signal PWM1 according to the compensation control signal CCS1 (step S326), thereby extending the luminous time of one or more luminous elements among the luminous elements D11-DN1 on the source line SL1.

Furthermore, in step S326, after the pulse width modulation signal generator 160 generates a plurality of pulse width modulation signals PWM1-PWMn according to CCS1-CCSn, the driving circuit 170 can generate source drive signals DS1-DSn to the source lines SL1-SLn according to the pulse width modulation signals PWM1-PWMn. In this way, the source driver 130 of the present embodiment can confirm the brightness uniformity state of the display panel 110 according to the instructions of the compensation control signals CCS1-CCSn, and adjust the time period of the pulse width modulation signals PWM1-PWMn accordingly. Furthermore, the source driver 130 can control the current state of the corresponding current slots I1-In through the source driving signals DS1-DSn to control the luminous time of the corresponding light-emitting element, thereby achieving the effect of compensating the brightness uniformity of the light-emitting element.

FIG4 is a schematic diagram of a display device according to another embodiment of the present invention. Referring to FIG4 , the display device 200 includes a display panel 210, a gate driver 220, a source driver 230, a clock generator 280, and a processor 290. In the embodiment shown in FIG4 , the source driver 230 may include a voltage detection circuit 240, a transmitter 250, a pulse width modulation signal generator 260, and a driving circuit 270. The display panel 210, gate driver 220, voltage detection circuit 240, pulse width modulation signal generator 260, driving circuit 270 and clock generator 280 shown in FIG. 4 can be inferred by referring to the relevant descriptions of the display panel 110, gate driver 120, voltage detection circuit 140, pulse width modulation signal generator 160, driving circuit 170 and clock generator 180 mentioned in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3A and FIG. 3B , and thus will not be described in detail.

Please refer to FIG. 4 , similar to the display device 100 shown in FIG. 1 , under some design requirements (in some embodiments), when the display device 200 compensates for the aging state of the light-emitting elements D11-DNM in the display panel 210, the voltage detection circuit 240 may include a plurality of analog-to-digital converters 141_1-141_n, a multiplexer 142, a voltage register 143, and a voltage register 144 shown in FIG. 2A .

In this case, the transmitter 250 of the source driver 230 is coupled to the voltage register 143 and the voltage register 144 shown in FIG. 2A to receive the detection voltages VD1’-VDn’ and the detection voltages VD1”-VDn”. The transmitter 250 can generate the detection voltage information DNO according to the detection voltages VD1’-VDn’ and the detection voltages VD1”-VDn”.

Under other design requirements (in other embodiments), when the display device 200 compensates for the brightness uniformity of the light-emitting elements D11-DNM in the display panel 210, the voltage detection circuit 240 may include a plurality of analog-to-digital converters 141_1-141_n and a voltage register 143 as shown in FIG. 2B.

In this case, the transmitter 250 is coupled to the voltage storage 143 shown in FIG2B to receive the detection voltages VD1'-VDn'. The transmitter 250 can generate the detection voltage information DNO according to the detection voltages VD1'-VDn'.

On the other hand, in the display device 200 shown in FIG4 , the processor 290 is coupled to the transmitter 250 and the PWM signal generator 260. The processor 290 can generate a plurality of compensation control signals CCS1-CCSn to the PWM signal generator 260 according to the detection voltage information DNO.

For details of the operation of the display device 200, please refer to FIG. 4 and FIG. 5. FIG. 5 is a timing diagram of the display device according to the embodiment of FIG. 4 of the present invention. Under some design requirements (in some embodiments), the display device 200 can compensate for the aging state of the light-emitting elements D11-DNM in the display panel 210. Regarding the operation of the display device 200 in the detection voltage storage time zone, the relevant descriptions mentioned in FIG. 1, FIG. 2A and FIG. 3A can be referred to by analogy, so it will not be repeated.

Next, when the source driver 230 determines that the voltage register 143 and the voltage register 144 shown in FIG. 2A have completed the storage operation of all the detection voltages VD1-VDn, the transmitter 250 of this embodiment can generate the detection voltage information DNO according to the detection voltages VD1'-VDn' and the detection voltages VD1"-VDn". Furthermore, the transmitter 250 may transmit the detection voltage information DNO to the processor 290 during the detection voltage information reporting time period, so that the processor 290 generates the compensation control signals CCS1-CCSn to the pulse width modulation signal generator 260 according to the detection voltage information DNO.

It is worth mentioning that the processor 290 confirms the aging degree of the light-emitting element on the corresponding source line according to the detection voltage information DNO, and the pulse width modulation signal generator 260 adjusts the time period of the pulse width modulation signals PWM1~PWMn according to the compensation control signals CCS1~CCSn. The operation details can be inferred by referring to the relevant descriptions mentioned in steps S310~S311 of Figures 1, 2A and 3A, so they are not repeated here.

In other words, unlike the compensation circuit 150 of the source driver 130 shown in FIG. 1 , FIG. 2A , and FIG. 3A , in the present embodiment, the display device 200 can calculate the detection voltage information DNO (or the detection voltages VD1’ to VDn’ and the detection voltages VD1” to VDn”) through the processor 290 disposed outside the source driver 230 to determine the aging degree of the light-emitting element on the corresponding source line.

On the other hand, under some design requirements (in some embodiments), the display device 200 can compensate for the brightness uniformity of the display panel 210. The operation of the display device 200 in the detection voltage storage time period can be deduced by referring to the relevant descriptions mentioned in steps S320 to S324 of FIG. 1 , FIG. 2B , and FIG. 3B , so it will not be repeated.

Next, when the source driver 230 determines that the voltage storage 143 shown in FIG. 2B has completed the storage operation of all the detection voltages VD1-VDn, the transmitter 250 of the present embodiment can generate the detection voltage information DNO according to the detection voltages VD1'-VDn'. Furthermore, the transmitter 250 can transmit the detection voltage information DNO to the processor 290 during the detection voltage information reporting time period, so that the processor 290 generates the compensation control signals CCS1-CCSn to the pulse width modulation signal generator 260 according to the detection voltage information DNO.

It is worth mentioning that the processor confirms the brightness uniformity of the display panel 210 according to the detection voltage information DNO, and the pulse width modulation signal generator 260 adjusts the time period of the pulse width modulation signals PWM1~PWMn according to the compensation control signals CCS1~CCSn. The operation details can be inferred by referring to the relevant descriptions mentioned in steps S325~S326 of Figures 1, 2B and 3B, so they are not repeated here.

In other words, different from the embodiments shown in FIG. 1 , FIG. 2B and FIG. 3B , in this embodiment, the display device 200 can calculate the detection voltage information DNO (or the detection voltages VD1′ to VDn′) through the processor 290 disposed outside the source driver 230 to determine the brightness uniformity of the display panel 210.

On the other hand, under other design requirements (in other embodiments), the processor 290 may calculate the maximum detection voltage VDMAX among all the detection voltages VD1-VDn according to the detection voltage information DNO after receiving the detection voltage information DNO (detection voltages VD1'-VDn' (and detection voltages VD1"-VDn")) from the transmitter 250. Among them, the power voltage VSD of the source driver 230 may be provided by an external power supply (not shown). The power supply may provide 1-3 sets of power voltages VSD to the source driver 230 for use by related circuits for processing multiple light-emitting elements. Furthermore, the processor 290 can dynamically adjust the power voltage VSD of the source driver 230 according to the maximum detection voltage VDMAX, thereby effectively achieving power saving effect.

According to the description of the above embodiments, the display device 100 shown in FIG1 can compensate for the aging state and brightness uniformity of the display panel 110 through self-detection and compensation of the source driver 130. In addition, the display device 200 shown in FIG4 can also report the detection voltage information DNO to the external processor 290, so that the display device 100 can compensate for the aging state and brightness uniformity of the display panel 210 through the processor 290, thereby improving the display effect of the display panels 110 and 210.

FIG6 is a flow chart of a driving method of the display device of FIG1 according to an embodiment of the present invention. Please refer to FIG1 and FIG6 simultaneously. In step S610, the display device may provide a display panel having a plurality of light-emitting elements. In step S620, the display device may provide a gate driver, and the gate driver provides a plurality of gate driving signals to drive the plurality of light-emitting elements respectively. In step S630, the display device may provide a source driver, and the source driver provides a plurality of source driving signals to a plurality of source lines.

In step S640, the display device can enable the source driver to sequentially detect and store multiple detection voltages on multiple source lines according to multiple gate driving signals. In step S650, the display device can enable the source driver to adjust the light-emitting time of multiple light-emitting elements according to the multiple detection voltages.

The implementation details of each step are fully described in the aforementioned embodiments and implementation methods, and will not be elaborated here.

In summary, the display device and the driving method thereof described in the embodiments of the present invention can detect and calculate multiple detection voltages on the source line through a source driver or an external processor. In addition, the source driver or the processor can adjust the time period of multiple pulse width modulation signals according to the detected multiple detection voltages. In this way, the source driver can control the current state of the corresponding current tank through the source drive signal to control the luminous time of the corresponding light-emitting element, thereby achieving the effect of compensating for the aging phenomenon of the light-emitting element and the brightness uniformity.

100, 200: display device 110, 210: display panel 120, 220: gate driver 130, 230: source driver 140, 240: voltage detection circuit 141_1~141_n: analog-to-digital converter 142: multiplexer 143, 144: voltage storage 150: compensation circuit 160, 260: pulse width modulation signal generator 170, 270: drive circuit 180, 280: clock generator 250: transmitter 290: processor CCS1~CCSn: compensation control signal CLKP, Clock_ADC: Clock signal DATA: Raw data signal DS1~DSn: Source drive signal D11~DNM: Light-emitting element DNO: Detection voltage information GL1~GLn: Gate line GS1~GSn: Gate drive signal I1~In: Current sink PWM1~PWMn: Pulse width modulation signal SCS: Scan control signal START: Start signal SL1~SLn: Source line S301~S311, S320~S326, S610~S650: Steps VD1~VDn, VD1’~VDn’, VD1”~VDn”: Detection voltage VSD: Power supply voltage

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 2A to FIG. 2B are circuit schematic diagrams of a voltage detection circuit according to the embodiment of FIG. 1 of the present invention. FIG. 3A to FIG. 3B are flow charts of an operation method for performing aging compensation and brightness uniformity compensation in a display device according to the embodiment of FIG. 1 of the present invention, respectively. FIG. 4 is a schematic diagram of a display device according to another embodiment of the present invention. FIG. 5 is a timing diagram of a display device according to the embodiment of FIG. 4 of the present invention. FIG. 6 is a flow chart of a driving method of the display device of FIG. 1 according to an embodiment of the present invention.

100: Display device

110: Display panel

120: Gate driver

130: Source driver

140: Voltage detection circuit

150: Compensation circuit

160: Pulse width modulation signal generator

170:Drive circuit

180: Pulse generator

CCS1~CCSn: compensation control signal

CLKP, Clock_ADC: clock signal

DATA: Raw data signal

DS1~DSn: Source drive signal

D11~DNM: Light-emitting element

GL1~GLn: Gate line

GS1~GSn: Gate drive signal

I1~In: current tank

PWM1~PWMn: pulse width modulation signal

SCS: Scan control signal

START: start signal

SL1~SLn: Source line

VD1~VDn, VD1’~VDn’, VD1”~VDn”: voltage detection

VSD: power supply voltage

Claims (24)

A display device includes: a display panel having a plurality of light-emitting elements, wherein the light-emitting elements are respectively coupled between a plurality of gate lines and a plurality of source lines; a gate driver coupled to the gate lines for providing a plurality of gate driving signals to respectively drive the light-emitting elements; and a source driver coupled to the source lines for providing a plurality of source driving signals to the source lines, wherein the source driver is configured to drive the light-emitting elements according to the gate driving signals. The plurality of detection voltages on the source lines are sequentially detected and stored according to the gate drive signals, and the luminous time of the light-emitting elements is adjusted according to the voltage difference between the detection voltages detected and stored in a first time interval and the detection voltages detected and stored in a second time interval after the first time interval, or according to the detection voltages and the number of the source lines. The display device as claimed in claim 1, wherein the source driver comprises: a voltage detection circuit coupled to the display panel for sequentially detecting the detection voltages on the source lines according to the gate drive signals, wherein the voltage detection circuit comprises: a first voltage storage and a second voltage storage for storing the detection voltages according to the gate drive signals. some detection voltages; and a multiplexer coupled to the source lines, the first voltage storage and the second voltage storage, the multiplexer is used to transmit the detection voltages to the first voltage storage in the first time period according to a clock signal, and transmit the detection voltages to the second voltage storage in the second time period according to the clock signal. The display device as claimed in claim 2, wherein the source driver further comprises: a compensation circuit coupled to the first voltage storage device and the second voltage storage device, for generating a plurality of detection voltages stored in the first voltage storage device and the detection voltages stored in the second voltage storage device according to comparison. compensation control signal; a pulse width modulation signal generator coupled to the compensation circuit for generating a plurality of pulse width modulation signals according to the compensation control signals; and a driving circuit coupled to the pulse width modulation signal generator for generating the source driving signals to the display panel according to the pulse width modulation signals. The display device as described in claim 3, wherein when the compensation circuit determines that the voltage difference between each of the detection voltages stored in the first voltage storage device and each of the detection voltages stored in the second voltage storage device under the same source line is less than a reference value, the pulse width modulation signal generator shortens the pulse width modulation signals according to the compensation control signals. When the compensation circuit determines that the voltage difference between each detection voltage stored in the first voltage storage device and each detection voltage stored in the second voltage storage device under the same source line is greater than the reference value, the pulse width modulation signal generator extends the time cycle of the pulse width modulation signals according to the compensation control signals. A display device as described in claim 1, wherein the source driver comprises: a voltage detection circuit coupled to the display panel for sequentially detecting the detection voltages on the source lines according to the gate drive signals, wherein the voltage detection circuit comprises: a voltage storage for storing the detection voltages according to the gate drive signals. The display device as described in claim 5, wherein the source driver further comprises: a compensation circuit coupled to the voltage storage device for generating a plurality of compensation control signals according to the detection voltages and the number of the source lines; a pulse width modulation signal generator coupled to the compensation circuit for generating a plurality of pulse width modulation signals according to the compensation control signals; and a driving circuit coupled to the pulse width modulation signal generator for generating the source driving signals to the display panel according to the pulse width modulation signals. A display device as described in claim 6, wherein the compensation circuit calculates a difference percentage between the detection voltage on each source line and the average detection voltage of the detection voltages on the source lines based on the detection voltages and the number of the source lines, wherein when the compensation circuit determines that the difference percentage is less than At a reference value, the pulse width modulation signal generator shortens the time cycle of the pulse width modulation signals according to the compensation control signals. When the compensation circuit determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator extends the time cycle of the pulse width modulation signals according to the compensation control signals. The display device as claimed in claim 2, wherein the display device further comprises: a processor coupled to the first voltage register and the second voltage register, for generating a plurality of compensation control signals according to comparison of the detection voltages stored in the first voltage register and the detection voltages stored in the second voltage register , wherein the source driver further includes: a pulse width modulation signal generator coupled to the processor for generating a plurality of pulse width modulation signals according to the compensation control signals; and a driving circuit coupled to the pulse width modulation signal generator for generating the source driving signals to the display panel according to the pulse width modulation signals. The display device as described in claim 8, wherein when the processor determines that the voltage difference between each of the detection voltages stored in the first voltage storage device and each of the detection voltages stored in the second voltage storage device under the same source line is less than a reference value, the pulse width modulation signal generator shortens the pulse width modulation signals according to the compensation control signals. When the processor determines that the voltage difference between each of the detection voltages stored in the first voltage storage and each of the detection voltages stored in the second voltage storage under the same source line is greater than the reference value, the pulse width modulation signal generator extends the time cycle of the pulse width modulation signals according to the compensation control signals. The display device as described in claim 5, wherein the display device further comprises: a processor coupled to the voltage storage device, for generating a plurality of compensation control signals according to the detection voltages and the number of the source lines; wherein the source driver further comprises: a pulse width modulation signal generator coupled to the processor, for generating a plurality of pulse width modulation signals according to the compensation control signals; and a driving circuit coupled to the pulse width modulation signal generator, for generating the source drive signals to the display panel according to the pulse width modulation signals. The display device as claimed in claim 10, wherein the processor calculates a difference percentage between the detection voltage on each source line and the average detection voltage of the detection voltages on the source lines according to the detection voltages and the number of the source lines, wherein when the processor determines that the difference percentage is less than When the processor determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator shortens the time cycle of the pulse width modulation signals according to the compensation control signals. When the processor determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator extends the time cycle of the pulse width modulation signals according to the compensation control signals. A display device as described in claim 1, wherein the gate driver and the source driver are integrated into the same integrated circuit die. A method for driving a display device includes: providing a display panel having a plurality of light-emitting elements; providing a gate driver, and causing the gate driver to provide a plurality of gate driving signals to drive the light-emitting elements respectively; providing a source driver, and causing the source driver to provide a plurality of source driving signals to a plurality of source lines; causing the source driver to detect the light-emitting elements in sequence according to the gate driving signals; and storing a plurality of detection voltages on the source lines; and causing the source driver to adjust the luminous time of the light-emitting elements according to the voltage difference between the detection voltages detected and stored in a first time interval and the detection voltages detected and stored in a second time interval after the first time interval, or according to the detection voltages and the number of the source lines. The driving method as described in claim 13, wherein the step of the source driver sequentially detecting and storing the detection voltages on the source lines according to the gate driving signals comprises: providing a voltage detection circuit, and making the voltage detection circuit sequentially detect the detection voltages on the source lines according to the gate driving signals; providing a first voltage storage device and a second voltage storage device; A memory is provided, and the first voltage memory and the second voltage memory are used to store the detection voltages according to the gate drive signals; and a multiplexer is provided, and the multiplexer is used to transmit the detection voltages to the first voltage memory according to a clock signal in the first time period, and transmit the detection voltages to the second voltage memory according to the clock signal in the second time period. As described in claim 14, the driving method further includes: providing a compensation circuit, and making the compensation circuit generate multiple compensation control signals according to the comparison of the detection voltages stored in the first voltage storage and the detection voltages stored in the second voltage storage; providing a pulse width modulation signal generator, and making the pulse width modulation signal generator generate multiple pulse width modulation signals according to the compensation control signals; and providing a driving circuit, and making the driving circuit generate the source driving signals to the display panel according to the pulse width modulation signals. The driving method as described in claim 15, wherein when the compensation circuit determines that the voltage difference between each of the detection voltages stored in the first voltage storage device and each of the detection voltages stored in the second voltage storage device under the same source line is less than a reference value, the pulse width modulation signal generator is caused to shorten the pulse width modulation signal according to the compensation control signals. When the compensation circuit determines that the voltage difference between each of the detection voltages stored in the first voltage storage and each of the detection voltages stored in the second voltage storage under the same source line is greater than the reference value, the pulse width modulation signal generator is made to extend the time cycle of the pulse width modulation signals according to the compensation control signals. The driving method as described in claim 13, wherein the step of using the source driver to sequentially detect and store the detection voltages on the source lines according to the gate driving signals includes: providing a voltage detection circuit, and making the voltage detection circuit sequentially detect the detection voltages on the source lines according to the gate driving signals; and providing a voltage storage, and making the voltage storage store the detection voltages according to the gate driving signals. As described in claim 17, the driving method further includes: providing a compensation circuit, and making the compensation circuit generate multiple compensation control signals according to the detection voltages and the number of the source lines; providing a pulse width modulation signal generator, and making the pulse width modulation signal generator generate multiple pulse width modulation signals according to the compensation control signals; and providing a driving circuit, and making the driving circuit generate the source driving signals to the display panel according to the pulse width modulation signals. The driving method as described in claim 18 further comprises: The compensation circuit calculates a difference percentage between the detection voltage on each source line and the average detection voltage of the detection voltages on the source lines according to the detection voltages and the number of the source lines; when the compensation circuit determines the difference percentage When the difference percentage is less than a reference value, the pulse width modulation signal generator shortens the time cycle of the pulse width modulation signals according to the compensation control signals; and when the compensation circuit determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator extends the time cycle of the pulse width modulation signals according to the compensation control signals. As described in claim 14, the driving method further includes: providing a processor, and causing the processor to generate a plurality of compensation control signals according to the comparison of the detection voltages stored in the first voltage storage and the detection voltages stored in the second voltage storage; providing a pulse width modulation signal generator, and causing the pulse width modulation signal generator to generate a plurality of pulse width modulation signals according to the compensation control signals; and providing a driving circuit, and causing the driving circuit to generate the source driving signals to the display panel according to the pulse width modulation signals. The driving method as claimed in claim 20, wherein when the processor determines that the voltage difference between each of the detection voltages stored in the first voltage register and each of the detection voltages stored in the second voltage register under the same source line is less than a reference value, the pulse width modulation signal generator is controlled according to the compensation control signals to shorten the pulse width modulation The time cycle of the signal, and when the processor determines that the voltage difference between each of the detection voltages stored in the first voltage storage and each of the detection voltages stored in the second voltage storage under the same source line is greater than the reference value, the pulse width modulation signal generator is made to extend the time cycle of the pulse width modulation signals according to the compensation control signals. As described in claim 17, the driving method further includes: providing a processor, and causing the processor to generate a plurality of compensation control signals according to the detection voltages and the number of the source lines; providing a pulse width modulation signal generator, and causing the pulse width modulation signal generator to generate a plurality of pulse width modulation signals according to the compensation control signals; and providing a driving circuit, and causing the driving circuit to generate the source driving signals to the display panel according to the pulse width modulation signals. The driving method as claimed in claim 22 further comprises: causing the processor to calculate a difference percentage between the detection voltage on each source line and the average detection voltage of the detection voltages on the source lines according to the detection voltages and the number of the source lines; when the processor determines that the difference percentage is less than When the processor determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator is caused to shorten the time cycle of the pulse width modulation signals according to the compensation control signals; and when the processor determines that the difference percentage is greater than the reference value, the pulse width modulation signal generator is caused to extend the time cycle of the pulse width modulation signals according to the compensation control signals. A driving method as described in claim 13, wherein the gate driver and the source driver are integrated into the same integrated circuit die.

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