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TWI850161B - Multilayer piezoelectric device and microelectromechanical speakers applying the same - Google Patents

Multilayer piezoelectric device and microelectromechanical speakers applying the same Download PDF

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TWI850161B
TWI850161B TW112147106A TW112147106A TWI850161B TW I850161 B TWI850161 B TW I850161B TW 112147106 A TW112147106 A TW 112147106A TW 112147106 A TW112147106 A TW 112147106A TW I850161 B TWI850161 B TW I850161B
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piezoelectric
electrode
layer
multilayer
pattern
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TW202525123A (en
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朱聖緣
李承穎
蔡震哲
何翊甄
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國立成功大學
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Abstract

A multilayer piezoelectric device includes a semiconductor substrate, a multilayer piezoelectric structure, a first connecting electrode and a second connecting electrode. The multilayer piezoelectric structure includes a plurality of piezoelectric multilayer films stacked in sequence. Each piezoelectric multilayer film includes a first electrode layer, a first piezoelectric layer, a second electrode layer, and a second piezoelectric layer. The first electrode layer and the second electrode layer respectively include a first connecting pattern and a second connecting pattern, and vertical projections of the first feed pattern and the second feed pattern do not overlap. The multilayer piezoelectric structure includes a first opening and a second opening exposing parts of the first feed pattern and the second feed pattern of each piezoelectric multilayer film, respectively. The first connection electrode and the second connection electrode are respectively in the first opening and the second opening, and connecting the first electrode layer and the second electrode layer.

Description

積層壓電元件及應用其之微機電揚聲器Multilayer piezoelectric element and micro-electromechanical speaker using the same

本揭露涉及壓電材料領域,尤其是一種積層壓電元件及應用其之微機電揚聲器。The present disclosure relates to the field of piezoelectric materials, and in particular to a multilayer piezoelectric element and a micro-electromechanical speaker using the same.

現今技術透過半導體製程,能夠將許多元件微小化。現有以半導體技術製作壓電元件,可以應用在感測器、微機電揚聲器等,可以感測微小的震動,並將震動轉換成電信號。Today's technology can miniaturize many components through semiconductor manufacturing processes. Piezoelectric components are currently made using semiconductor technology and can be used in sensors, micro-electromechanical speakers, etc. They can sense tiny vibrations and convert them into electrical signals.

然而,相較於傳統塊材製作的壓電元件,現有以半導體技術製作壓電元件考量後續的接線,採用階梯狀的結構,已露出部分的正極、負極,但也因此使得整體向上堆疊的厚度受到限制。但也因為受限於厚度,難以增加較大的驅動電壓,在使用上較為受限,尤其在應用在揚聲器時,在聲壓增益,尤其在高頻段的音頻上表現不佳。However, compared to piezoelectric components made of traditional bulk materials, the current piezoelectric components made with semiconductor technology use a stepped structure to expose part of the positive and negative electrodes, but this also limits the thickness of the overall stacking. However, due to the thickness limit, it is difficult to increase the driving voltage, and the use is relatively limited, especially when used in speakers, the sound pressure gain, especially the high-frequency audio performance is poor.

在此,本揭露提供一種積層壓電元件。在一些實施例中,積層壓電元件包含半導體基板、積層壓電結構、第一連接電極、以及第二連接電極。積層壓電結構位於半導體基板上,且包含複數個壓電積層膜。各壓電積層膜依序堆疊,且各壓電積層膜由下至上依序包含第一電極層、第一壓電層、第二電極層及第二壓電層。Here, the present disclosure provides a laminated piezoelectric device. In some embodiments, the laminated piezoelectric device includes a semiconductor substrate, a laminated piezoelectric structure, a first connecting electrode, and a second connecting electrode. The laminated piezoelectric structure is located on the semiconductor substrate and includes a plurality of piezoelectric laminated films. Each piezoelectric laminated film is stacked in sequence, and each piezoelectric laminated film includes a first electrode layer, a first piezoelectric layer, a second electrode layer, and a second piezoelectric layer in sequence from bottom to top.

第一電極層包含第一電極線路圖案及第一連接圖案,第一連接圖案連接第一電極線路圖案。第一壓電層覆蓋第一電極層。第二電極層位在第一壓電層上,且包含第二電極圖案及第二連接圖案,第二連接圖案連接第二電極圖案。第二壓電層覆蓋第二電極層。壓電積層膜最下方的一者,其第一電極層位於半導體基板上,其餘壓電積層膜的第一電極層位於第二壓電層上。壓電積層膜的第一連接圖案的垂直投影彼此重疊、第二連接圖案的垂直投影彼此重疊,第一連接圖案與第二連接圖案的垂直投影完全不重疊。積層壓電結構包含第一開孔及第二開孔,第一開孔及第二開孔分別曝露出各壓電積層膜之第一連接圖案的一部分,以及各壓電積層膜之第二連接圖案的一部分。The first electrode layer includes a first electrode circuit pattern and a first connection pattern, and the first connection pattern is connected to the first electrode circuit pattern. The first piezoelectric layer covers the first electrode layer. The second electrode layer is located on the first piezoelectric layer and includes a second electrode pattern and a second connection pattern, and the second connection pattern is connected to the second electrode pattern. The second piezoelectric layer covers the second electrode layer. The first electrode layer of the lowermost piezoelectric stacked layer film is located on the semiconductor substrate, and the first electrode layers of the remaining piezoelectric stacked layer films are located on the second piezoelectric layer. The vertical projections of the first connection pattern of the piezoelectric laminated film overlap each other, the vertical projections of the second connection pattern overlap each other, and the vertical projections of the first connection pattern and the second connection pattern do not overlap at all. The laminated piezoelectric structure includes a first opening and a second opening, and the first opening and the second opening respectively expose a portion of the first connection pattern of each piezoelectric laminated film and a portion of the second connection pattern of each piezoelectric laminated film.

第一連接電極位於第一開孔中,連接各第一電極層,將各第一電極層並聯。第二連接電極位於第二開孔中,連接各第二電極層,將各第二電極層並聯。The first connecting electrode is located in the first opening, connected to each first electrode layer, and connected to each first electrode layer in parallel. The second connecting electrode is located in the second opening, connected to each second electrode layer, and connected to each second electrode layer in parallel.

在一些實施例中,壓電積層膜的面積相同。In some embodiments, the areas of the piezoelectric layers are the same.

在一些實施例中,壓電積層膜的數量大於五。更較佳地,在一些實施例中,壓電積層膜的數量大於八。In some embodiments, the number of the piezoelectric stacked films is greater than five. More preferably, in some embodiments, the number of the piezoelectric stacked films is greater than eight.

在一些實施例中,第一壓電層與第二壓電層係選自鋯鈦酸鉛(Pb(ZrTi)O 3, PZT)、鈦酸鋇(BaTiO 3)、鈦酸鉛(PbTiO 3)及氮化鋁(AlN)所構成之群組。 In some embodiments, the first piezoelectric layer and the second piezoelectric layer are selected from the group consisting of lead zirconate titanate (Pb(ZrTi)O 3 , PZT), barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ) and aluminum nitride (AlN).

在一些實施例中,半導體基板為矽基板。進一步地,矽基板與積層壓電結構之間更包含二氧化矽層。In some embodiments, the semiconductor substrate is a silicon substrate. Furthermore, a silicon dioxide layer is included between the silicon substrate and the laminated piezoelectric structure.

在一些實施例中,第一電極層及第二電極層為鉑、銅、鋁所構成之群組。In some embodiments, the first electrode layer and the second electrode layer are a group consisting of platinum, copper, and aluminum.

進一步地,壓電積層膜最下方的一者的第一電極層與半導體基板之間,更包含鈦(Ti)層。Furthermore, a titanium (Ti) layer is included between the first electrode layer of the bottom one of the piezoelectric stacked layers and the semiconductor substrate.

在此,還提供在一種微機電壓電揚聲器。一些實施例中,微機電壓電揚聲器包含前述實施例所述之積層壓電元件。Here, a micro-electromechanical piezoelectric loudspeaker is also provided. In some embodiments, the micro-electromechanical piezoelectric loudspeaker includes the multilayer piezoelectric element described in the above embodiments.

如同前述各實施例所示,透過設計第一連接圖案及第二連接圖案於不同側,透過鑽孔技術,在側邊透過第一連接電極將第一連接圖案彼此連接、透過第二連接電極將第二連接圖案彼此連接。如此,不必在積層堆疊時預留電極的開口,能夠達到多層堆疊的效果,而能在作為微機電揚聲器時,在聲壓增益上有更好的表現。As shown in the above embodiments, by designing the first connection pattern and the second connection pattern on different sides, the first connection patterns are connected to each other through the first connection electrode and the second connection patterns are connected to each other through the second connection electrode on the side by drilling technology. In this way, it is not necessary to reserve electrode openings when stacking layers, and the effect of multi-layer stacking can be achieved, and when used as a micro-electromechanical speaker, it can have a better performance in sound pressure gain.

應當理解的是,元件被稱為「設置」於另一元件時,可以表示元件是直接位另一元件上,或者也可以存在中間元件,透過中間元件連接元件與另一元件。相反地,當元件被稱為「直接設置在另一元件上」或「直接設置到另一元件」時,可以理解的是,此時明確定義了不存在中間元件。It should be understood that when an element is referred to as being "disposed" on another element, it can mean that the element is directly located on the other element, or there may be an intermediate element through which the element and the other element are connected. Conversely, when an element is referred to as being "directly disposed on another element" or "directly disposed to another element", it can be understood that it is clearly defined that there are no intermediate elements.

另外,術語「第一」、「第二」、「第三」這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開,而非表示其必然的先後順序。此外,諸如「下」和「上」的相對術語可在本文中用於描述一個元件與另一元件的關係,應當理解,相對術語旨在包括除了圖中所示的方位之外的裝置的不同方位。例如,如果一個附圖中的裝置翻轉,則被描述為在其他元件的「下」側的元件將被定向在其他元件的「上」 側。此僅表示相對的方位關係,而非絕對的方位關係。In addition, the terms "first", "second", and "third" are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part, rather than to indicate a necessary order of precedence. In addition, relative terms such as "lower" and "upper" may be used herein to describe the relationship between one element and another element, and it should be understood that the relative terms are intended to include different orientations of the device in addition to the orientation shown in the figure. For example, if a device in an accompanying figure is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. This only indicates a relative orientation relationship, not an absolute orientation relationship.

圖1為積層壓電元件的爆炸分解圖。圖2為積層壓電元件的局部剖面放大圖。圖3為積層壓電元件的局部剖面圖。依據圖1至圖3的實施例所示,積層壓電元件1包含半導體基板10、積層壓電結構20、第一連接電極40、以及第二連接電極50。積層壓電結構20位於半導體基板10上,且包含複數個壓電積層膜30。各壓電積層膜30依序堆疊,且各壓電積層膜30由下至上依序包含第一電極層31、第一壓電層33、第二電極層35及第二壓電層37。為了更加清楚呈現所欲強調的連接關係,圖2及圖3省略部分的元件。FIG. 1 is an exploded view of a multilayer piezoelectric device. FIG. 2 is an enlarged partial cross-sectional view of a multilayer piezoelectric device. FIG. 3 is a partial cross-sectional view of a multilayer piezoelectric device. According to the embodiments shown in FIG. 1 to FIG. 3 , a multilayer piezoelectric device 1 includes a semiconductor substrate 10, a multilayer piezoelectric structure 20, a first connecting electrode 40, and a second connecting electrode 50. The multilayer piezoelectric structure 20 is located on the semiconductor substrate 10 and includes a plurality of piezoelectric multilayer films 30. Each piezoelectric stacked layer film 30 is stacked in sequence, and each piezoelectric stacked layer film 30 includes, from bottom to top, a first electrode layer 31, a first piezoelectric layer 33, a second electrode layer 35, and a second piezoelectric layer 37. In order to more clearly present the connection relationship to be emphasized, some elements are omitted in FIG. 2 and FIG. 3.

第一電極層31包含第一電極線路圖案311及第一連接圖案313,第一連接圖案313連接第一電極線路圖案311。換言之,第一電極線路圖案311與第一連接圖案313是在顯影、蝕刻階段共同製作。第一壓電層33覆蓋第一電極層31。第二電極層35位在第一壓電層33上,且包含第二電極圖案351及第二連接圖案353,第二連接圖案353連接第二電極圖案351。第二壓電層37覆蓋第二電極層35。在此,第一壓電層33與第二壓電層37阻絕第一電極層31與第二電極層35之間的電氣導通,通常採用的材料是第一壓電層與第二壓電層係選自鋯鈦酸鉛(Pb(ZrTi)O 3, PZT)、鈦酸鋇(BaTiO 3)、鈦酸鉛(PbTiO 3)及氮化鋁(AlN)。 The first electrode layer 31 includes a first electrode circuit pattern 311 and a first connection pattern 313, and the first connection pattern 313 is connected to the first electrode circuit pattern 311. In other words, the first electrode circuit pattern 311 and the first connection pattern 313 are jointly produced in the development and etching stages. The first piezoelectric layer 33 covers the first electrode layer 31. The second electrode layer 35 is located on the first piezoelectric layer 33 and includes a second electrode pattern 351 and a second connection pattern 353, and the second connection pattern 353 is connected to the second electrode pattern 351. The second piezoelectric layer 37 covers the second electrode layer 35. Here, the first piezoelectric layer 33 and the second piezoelectric layer 37 block electrical conduction between the first electrode layer 31 and the second electrode layer 35. The materials generally used are selected from lead zirconate titanate (Pb(ZrTi)O 3 , PZT), barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ) and aluminum nitride (AlN).

壓電積層膜30最下方的一者,其第一電極層31位於半導體基板10上,其餘壓電積層膜30的第一電極層31位於下方之壓電積層膜30第二壓電層37上。在此,壓電積層膜30中的第一連接圖案313的垂直投影彼此重疊、第二連接圖案353的垂直投影彼此重疊,第一連接圖案313與第二連接圖案353的垂直投影完全不重疊。The first electrode layer 31 of the bottommost piezoelectric layer film 30 is located on the semiconductor substrate 10, and the first electrode layer 31 of the remaining piezoelectric layer films 30 is located on the second piezoelectric layer 37 of the bottom piezoelectric layer film 30. Here, the vertical projections of the first connection patterns 313 in the piezoelectric layer film 30 overlap each other, and the vertical projections of the second connection patterns 353 overlap each other, and the vertical projections of the first connection patterns 313 and the second connection patterns 353 do not overlap at all.

積層壓電結構20包含第一開孔21及第二開孔23,由積層壓電結構20的頂部貫穿至底部。第一開孔21及第二開孔23分別曝露出各壓電積層膜30之第一連接圖案313的一部分,以及各壓電積層膜30之第二連接圖案353的一部分。第一連接電極40位於第一開孔21中,連接各第一電極層31的第一連接圖案313,以將各第一電極層31並聯。第二連接電極50位於第二開孔23中,連接各第二電極層35的第二連接圖案353,將各第二電極層35並聯。換言之,透過第一連接圖案313及第二連接圖案353引線到不同側,透過鑽孔技術,在側邊透過第一連接電極40將第一連接圖案313彼此連接、透過第二連接電極50將第二連接圖案353彼此連接。如此,不必在每一個積層壓電結構20預留電極的開口,能夠達到多層堆疊的效果。The laminated piezoelectric structure 20 includes a first opening 21 and a second opening 23, which penetrate from the top to the bottom of the laminated piezoelectric structure 20. The first opening 21 and the second opening 23 respectively expose a portion of the first connection pattern 313 of each piezoelectric laminate film 30 and a portion of the second connection pattern 353 of each piezoelectric laminate film 30. The first connection electrode 40 is located in the first opening 21, connected to the first connection pattern 313 of each first electrode layer 31, so as to connect each first electrode layer 31 in parallel. The second connection electrode 50 is located in the second opening 23, connected to the second connection pattern 353 of each second electrode layer 35, so as to connect each second electrode layer 35 in parallel. In other words, the first connection pattern 313 and the second connection pattern 353 are led to different sides, and the first connection patterns 313 are connected to each other through the first connection electrode 40 and the second connection patterns 353 are connected to each other through the second connection electrode 50 by drilling technology. In this way, it is not necessary to reserve an electrode opening in each laminated piezoelectric structure 20, and the effect of multi-layer stacking can be achieved.

基於上述實施例的結構,各壓電積層膜30的面積相同。如此,在製作的光罩設計可以更加簡便。另外,在一些實施例中,壓電積層膜30的數量大於五,較佳地,壓電積層膜30的數量大於八。如此,對於製作微機電壓電揚聲器可以達到更佳的聲壓增益。Based on the structure of the above embodiment, the area of each piezoelectric layer film 30 is the same. In this way, the mask design in the manufacturing can be more convenient. In addition, in some embodiments, the number of piezoelectric layer films 30 is greater than five, preferably, the number of piezoelectric layer films 30 is greater than eight. In this way, a better sound pressure gain can be achieved for manufacturing a micro-electromechanical piezoelectric loudspeaker.

在此參見圖1及圖2,半導體基板10為矽基板。進一步地,為了晶格的匹配,半導體基板10與積層壓電結構20之間更包含二氧化矽層11。1 and 2 , the semiconductor substrate 10 is a silicon substrate. Furthermore, for lattice matching, a silicon dioxide layer 11 is further included between the semiconductor substrate 10 and the laminated piezoelectric structure 20.

在一些實施例中,第一電極層31及第二電極層35為鉑、銅、或鋁。進一步地,為了晶格匹配,減少缺陷,壓電積層膜30最下方的一者的第一電極層31與半導體基板10之間,更包含鈦層60。In some embodiments, the first electrode layer 31 and the second electrode layer 35 are platinum, copper, or aluminum. Furthermore, in order to achieve lattice matching and reduce defects, a titanium layer 60 is further included between the first electrode layer 31 of the bottom of the piezoelectric stack film 30 and the semiconductor substrate 10.

圖4為應用積層壓電元件之微機電壓電揚聲器與傳統微機電壓電揚聲器在自由音場下的波頻比較圖。圖5為應用積層壓電元件之微機電壓電揚聲器與傳統微機電壓電揚聲器在壓力音場下的波頻比較圖。Figure 4 is a frequency comparison diagram of the MEMS piezoelectric speaker using multilayer piezoelectric elements and the traditional MEMS piezoelectric speaker in a free sound field. Figure 5 is a frequency comparison diagram of the MEMS piezoelectric speaker using multilayer piezoelectric elements and the traditional MEMS piezoelectric speaker in a pressure sound field.

在此,實驗例是在本案圖1所示,堆疊五層壓電積層膜30的結構,作為微機電揚聲器。比較例是傳統的微機電揚聲器。圖4及圖5是在自由音場及壓力音場下,對100 Hz至20kHz的頻率範圍內進行實際的量測,對實驗例所施加的驅動電壓為5 Vrms的交流電壓,而對比較力施加的電壓是15 Vrms的交流電壓。在此,是預期應用積層壓電元件之微機電壓電揚聲器中的積層結構的電極並聯的貢獻,能提供更低的驅動電壓。Here, the experimental example is a structure of stacking five layers of piezoelectric multilayer films 30 as a micro-electromechanical speaker as shown in FIG. 1 of the present case. The comparative example is a conventional micro-electromechanical speaker. FIG. 4 and FIG. 5 are actual measurements in a frequency range of 100 Hz to 20 kHz under a free sound field and a pressure sound field. The driving voltage applied to the experimental example is an AC voltage of 5 Vrms, while the voltage applied to the comparative force is an AC voltage of 15 Vrms. Here, it is expected that the contribution of the parallel connection of the electrodes of the multilayer structure in the micro-electromechanical piezoelectric speaker using the multilayer piezoelectric element can provide a lower driving voltage.

在此,在波頻譜圖中,可見應用積層壓電元件之微機電壓電揚聲器的高頻表現較佳,同時,無論是在自由音場或是壓力音場下,應用積層壓電元件之微機電壓電揚聲器都有較佳的聲學表現。積層結構在自由音場下最高可達69.9 dB,而比較例僅能達到38.7 dB,聲壓增益約30倍。另外,應用積層壓電元件之微機電壓電揚聲器在壓力音場下最高可達91.5 dB,單層結構最高可達72.6 dB,聲壓增益約10倍。Here, in the wave spectrum diagram, it can be seen that the MEMS piezoelectric speaker using multilayer piezoelectric elements has better high-frequency performance. At the same time, whether in a free sound field or a pressure sound field, the MEMS piezoelectric speaker using multilayer piezoelectric elements has better acoustic performance. The multilayer structure can reach a maximum of 69.9 dB in a free sound field, while the comparison example can only reach 38.7 dB, and the sound pressure gain is about 30 times. In addition, the MEMS piezoelectric speaker using multilayer piezoelectric elements can reach a maximum of 91.5 dB in a pressure sound field, and the single-layer structure can reach a maximum of 72.6 dB, and the sound pressure gain is about 10 times.

綜上所述,在一些實施例中,透過設計第一連接圖案313及第二連接圖案353於不同側,透過鑽孔技術,在側邊透過第一連接電極40將第一連接圖案313彼此連接、透過第二連接電極50將第二連接圖案353彼此連接。如此,不必在每一個積層堆疊時預留電極的開口,能夠達到多層堆疊的效果,而能在作為微機電揚聲器時,在聲壓增益上有更好的表現。In summary, in some embodiments, the first connection pattern 313 and the second connection pattern 353 are designed to be on different sides, and the first connection patterns 313 are connected to each other through the first connection electrode 40 and the second connection patterns 353 are connected to each other through the second connection electrode 50 by drilling technology. In this way, it is not necessary to reserve an electrode opening when each layer is stacked, and the effect of multi-layer stacking can be achieved, and when used as a micro-electromechanical speaker, it can have a better performance in sound pressure gain.

雖然本揭露的技術內容已經以較佳實施例揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本揭露之精神所作些許之更動與潤飾,皆應涵蓋於本揭露的範疇內,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。Although the technical contents of the present disclosure have been disclosed as above with the preferred embodiments, they are not used to limit the present disclosure. Any slight changes and modifications made by anyone skilled in the art without departing from the spirit of the present disclosure should be included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the definition of the attached patent application scope.

1:積層壓電元件 10:半導體基板 11:二氧化矽層 20:積層壓電結構 21:第一開孔 23:第二開孔 30:壓電積層膜 31:第一電極層 311:第一電極線路圖案 313:第一連接圖案 33:第一壓電層 35:第二電極層 351:第二電極圖案 353:第二連接圖案 37:第二壓電層 40:第一連接電極 50:第二連接電極 60:鈦層1: Laminated piezoelectric element 10: Semiconductor substrate 11: Silicon dioxide layer 20: Laminated piezoelectric structure 21: First opening 23: Second opening 30: Piezoelectric laminate film 31: First electrode layer 311: First electrode circuit pattern 313: First connection pattern 33: First piezoelectric layer 35: Second electrode layer 351: Second electrode pattern 353: Second connection pattern 37: Second piezoelectric layer 40: First connection electrode 50: Second connection electrode 60: Titanium layer

圖1為積層壓電元件的爆炸分解圖。 圖2為積層壓電元件的局部剖面放大圖。 圖3為積層壓電元件的局部剖面圖。 圖4為應用積層壓電元件之微機電壓電揚聲器與傳統微機電壓電揚聲器在自由音場下的波頻比較圖。 圖5為應用積層壓電元件之微機電壓電揚聲器與傳統微機電壓電揚聲器在壓力音場下的波頻比較圖。 Figure 1 is an exploded view of a multilayer piezoelectric component. Figure 2 is an enlarged partial cross-sectional view of a multilayer piezoelectric component. Figure 3 is a partial cross-sectional view of a multilayer piezoelectric component. Figure 4 is a frequency comparison diagram of a MEMS piezoelectric speaker using a multilayer piezoelectric component and a conventional MEMS piezoelectric speaker in a free sound field. Figure 5 is a frequency comparison diagram of a MEMS piezoelectric speaker using a multilayer piezoelectric component and a conventional MEMS piezoelectric speaker in a pressure sound field.

1:積層壓電元件 1: Multilayer piezoelectric element

10:半導體基板 10: Semiconductor substrate

11:二氧化矽層 11:Silicon dioxide layer

20:積層壓電結構 20: Laminated piezoelectric structure

21:第一開孔 21: First opening

23:第二開孔 23: Second opening

30:壓電積層膜 30: Piezoelectric laminate film

31:第一電極層 31: First electrode layer

311:第一電極線路圖案 311: First electrode circuit pattern

313:第一連接圖案 313: First connection pattern

33:第一壓電層 33: First piezoelectric layer

35:第二電極層 35: Second electrode layer

351:第二電極圖案 351: Second electrode pattern

353:第二連接圖案 353: Second connection pattern

37:第二壓電層 37: Second piezoelectric layer

40:第一連接電極 40: First connecting electrode

50:第二連接電極 50: Second connecting electrode

60:鈦層 60: Titanium layer

Claims (10)

一種積層壓電元件,包含: 一半導體基板; 一積層壓電結構,位於該半導體基板上,包含複數個壓電積層膜,各該壓電積層膜依序堆疊,且各該壓電積層膜由下至上依序包含: 一第一電極層,包含一第一電極線路圖案及一第一連接圖案,該第一連接圖案連接該第一電極線路圖案; 一第一壓電層,覆蓋該第一電極層; 一第二電極層,位在該第一壓電層上,包含一第二電極圖案及一第二連接圖案,該第二連接圖案連接該第二電極圖案;以及 一第二壓電層,覆蓋該第二電極層, 其中該等壓電積層膜最下方的一者,其該第一電極層位於該半導體基板上,其餘之該等壓電積層膜的該第一電極層,位於該第二壓電層上,該等壓電積層膜的該第一連接圖案的垂直投影彼此重疊、該等壓電積層膜的該第二連接圖案的垂直投影彼此重疊,且該第一連接圖案與該第二連接圖案的垂直投影完全不重疊,該積層壓電結構包含一第一開孔及一第二開孔,該第一開孔及該第二開孔分別曝露出各該壓電積層膜之該第一連接圖案的一部分,以及各該壓電積層膜之該第二連接圖案的一部分; 一第一連接電極,位於該第一開孔中,連接各該第一電極層,將各該第一電極層並聯;以及 一第二連接電極,位於該第二開孔中,連接各該第二電極層,將各該第二電極層並聯。 A laminated piezoelectric element comprises: A semiconductor substrate; A laminated piezoelectric structure, located on the semiconductor substrate, comprising a plurality of piezoelectric laminated films, each of which is stacked in sequence, and each of which comprises, from bottom to top, the following: A first electrode layer, comprising a first electrode circuit pattern and a first connection pattern, wherein the first connection pattern is connected to the first electrode circuit pattern; A first piezoelectric layer, covering the first electrode layer; A second electrode layer, located on the first piezoelectric layer, comprising a second electrode pattern and a second connection pattern, wherein the second connection pattern is connected to the second electrode pattern; and A second piezoelectric layer, covering the second electrode layer, The first electrode layer of the bottom one of the piezoelectric stacked films is located on the semiconductor substrate, and the first electrode layers of the remaining piezoelectric stacked films are located on the second piezoelectric layer. The vertical projections of the first connection patterns of the piezoelectric stacked films overlap with each other, and the vertical projections of the second connection patterns of the piezoelectric stacked films overlap with each other, and the vertical projections of the first connection pattern and the second connection pattern do not overlap at all. The stacked piezoelectric structure includes a first opening and a second opening, and the first opening and the second opening respectively expose a portion of the first connection pattern of each piezoelectric stacked film and a portion of the second connection pattern of each piezoelectric stacked film; A first connecting electrode, located in the first opening, connected to each of the first electrode layers, connecting each of the first electrode layers in parallel; and A second connecting electrode, located in the second opening, connected to each of the second electrode layers, connecting each of the second electrode layers in parallel. 如請求項1所述之積層壓電元件,其中該等壓電積層膜的面積相同。A multilayer piezoelectric device as described in claim 1, wherein the areas of the piezoelectric multilayer films are the same. 如請求項1所述之積層壓電元件,其中該等壓電積層膜的數量大於五。A multilayer piezoelectric device as described in claim 1, wherein the number of the piezoelectric multilayer films is greater than five. 如請求項3所述之積層壓電元件,其中該等壓電積層膜的數量大於八。A multilayer piezoelectric device as described in claim 3, wherein the number of the piezoelectric multilayer films is greater than eight. 如請求項1所述之積層壓電元件,其中該第一壓電層與該第二壓電層係選自鋯鈦酸鉛(Pb(ZrTi)O 3, PZT)、鈦酸鋇(BaTiO 3)、鈦酸鉛(PbTiO 3)及氮化鋁(AlN)所構成之群組。 The multilayer piezoelectric element as claimed in claim 1, wherein the first piezoelectric layer and the second piezoelectric layer are selected from the group consisting of lead zirconate titanate (Pb(ZrTi)O 3 , PZT), barium titanate (BaTiO 3 ), lead titanate (PbTiO 3 ) and aluminum nitride (AlN). 如請求項1所述之積層壓電元件,其中該半導體基板為一矽基板。A multilayer piezoelectric device as described in claim 1, wherein the semiconductor substrate is a silicon substrate. 如請求項6所述之積層壓電元件,其中該矽基板與該積層壓電結構之間更包含一二氧化矽層。The multilayer piezoelectric device as described in claim 6, wherein a silicon dioxide layer is further included between the silicon substrate and the multilayer piezoelectric structure. 如請求項6所述之積層壓電元件,其中該第一電極層及該第二電極層係選自鉑、銅、鋁所構成之群組。The multilayer piezoelectric device as described in claim 6, wherein the first electrode layer and the second electrode layer are selected from the group consisting of platinum, copper, and aluminum. 如請求項8所述之積層壓電元件,其中在該等壓電積層膜最下方的一者的該第一電極層與該半導體基板之間,更包含一鈦(Ti)層。The multilayer piezoelectric device as described in claim 8 further comprises a titanium (Ti) layer between the first electrode layer of the bottommost one of the piezoelectric multilayer films and the semiconductor substrate. 一種微機電壓電揚聲器,包含如請求項1至9任一項所述之積層壓電元件。A micro-electromechanical piezoelectric speaker comprises the multilayer piezoelectric element as described in any one of claims 1 to 9.
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