TWI849920B - High electron mobility transistor and fabrication method thereof - Google Patents

Abstract

A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer, and a semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode, and a first via passes through the first dielectric layer and extends downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer, and a second field plate is disposed on the first dielectric layer and in contact with the first field plate.

Description

High electron mobility transistor and method for manufacturing the same

This disclosure relates to the field of semiconductors, and in particular to high electron mobility transistors and methods for manufacturing the same.

In semiconductor technology, III-V compound semiconductors can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are transistors with a two-dimensional electron gas (2DEG), where the 2DEG is adjacent to the junction between two materials with different band gaps (i.e., heterojunctions). Since HEMTs use 2DEG as the carrier channel of the transistor instead of the doped region, they have many attractive properties compared to the conventional metal oxide semiconductor field effect transistor (MOSFET), such as high electron mobility and the ability to transmit signals at high frequencies. Typically, a field plate can be set in a HEMT to regulate the electric field distribution, thereby increasing the breakdown voltage of the HEMT. However, the conventional process steps for manufacturing the field plate of the HEMT are complicated and increase the manufacturing cost.

In view of this, the present disclosure proposes a high electron mobility transistor (HEMT) and a manufacturing method thereof, which uses fewer masks and fewer metal layers to manufacture more field plates, thereby simplifying the HEMT manufacturing process steps and reducing the manufacturing cost, and more field plates are used to redistribute the electric field, thereby increasing the breakdown voltage of the HEMT.

According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including a substrate, a semiconductor channel layer, a semiconductor barrier layer, a source electrode, a drain electrode, a semiconductor cap layer, a first dielectric layer, a first via hole, a gate electrode, a first field plate, and a second field plate. The semiconductor channel layer and the semiconductor barrier layer are sequentially arranged on the substrate, the source electrode and the drain electrode are arranged on the semiconductor channel layer, the semiconductor cap layer is arranged on the semiconductor barrier layer, the first dielectric layer is arranged on the source electrode, the semiconductor cap layer and the drain electrode, the first via hole penetrates the first dielectric layer and extends downward to the semiconductor cap layer, the gate electrode is arranged on the first dielectric layer and contacts the first via hole, the first field plate is arranged in the first dielectric layer, and the second field plate is arranged on the first dielectric layer and contacts the first field plate.

According to an embodiment of the present disclosure, a method for manufacturing a high electron mobility transistor is provided, comprising the following steps: providing a substrate; sequentially forming a semiconductor channel layer and a semiconductor barrier layer on the substrate; forming a semiconductor cap layer on the semiconductor barrier layer; forming a source electrode and a drain electrode on the semiconductor channel layer; forming a first dielectric layer on the source electrode, the semiconductor cap layer and the drain electrode; forming a first opening A first opening is formed in the first dielectric layer; a second opening is formed, which penetrates the first dielectric layer and extends downward to the semiconductor cap layer; a first metal layer is deposited on the first dielectric layer and fills the first opening and the second opening to form a first field plate in the first opening and a first via hole in the second opening respectively; and the first metal layer is patterned to form a gate electrode contacting the first via hole and a second field plate contacting the first field plate.

In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the accompanying drawings.

100: High electron mobility transistor

101: Base

103: Buffer layer

105: Semiconductor channel layer

107: Semiconductor barrier layer

109:Semiconductor capping

110: First dielectric layer

110-1: First sublayer

110-2: Second sublayer

111: First board

112: Second board

113: The third board

114: The fourth board

115: The fifth board

116: The sixth board

120: Second dielectric layer

122: Etch stop layer

124, 126: Opening

125: Source electrode

125P: Part of the source electrode

127: Drain electrode

127P: Part of the drain electrode

129: Gate electrode

130: Third dielectric layer

131: First conductive hole

132: Second conductive hole

133: Third conductive hole

134, 136: Dielectric block

135: First conductor

137: Second wire

140: Protective layer

150, 160, 170: Patterned mask

151: First opening

152: Second opening

153: The third opening

154: The fourth opening

161: First metal layer

θ: angle of intersection

S101, S103, S105, S107, S109, S111, S113, S201, S203, S205, S207: Steps

In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

Figure 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure.

Figure 2 is a schematic cross-sectional view of a HEMT according to another embodiment of the present disclosure.

Figure 3 is a cross-sectional schematic diagram of a HEMT according to another embodiment of the present disclosure.

Figures 4, 5, 6 and 7 are cross-sectional schematic diagrams of some stages of a method for manufacturing a high electron mobility transistor according to an embodiment of the present disclosure.

Figures 8, 9 and 10 are cross-sectional schematic diagrams of the intermediate stages of the method for manufacturing a high electron mobility transistor according to another embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.

In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of semiconductor devices during use and operation. As the orientation of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or section from another element, component, region, layer, and/or section, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or section discussed below can also be referred to as the second element, component, region, layer, or section.

The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

In the present disclosure, "compound semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. The group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the group V element may be nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb). Furthermore, the "compound semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor or a quaternary compound semiconductor, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), their analogs or combinations of the above compounds, but not limited thereto. In addition, depending on the needs, the compound semiconductor may also include dopants to be a compound semiconductor with a specific conductivity type, such as an n-type or p-type compound semiconductor. In the following text, compound semiconductors may also be referred to as III-V semiconductors.

Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.

The present disclosure relates to a high electron mobility transistor (HEMT) including multiple field plates and a manufacturing method thereof. By using three masks and a metal layer, two field plates, a gate electrode, three vias electrically connected to a source electrode, a drain electrode and a semiconductor cap layer, and three wires electrically coupled to the source electrode, the gate electrode and the drain electrode can be manufactured simultaneously. This can reduce the manufacturing steps of the HEMT and reduce the manufacturing cost. In addition, multiple field plates can achieve the effect of redistributing the electric field, thereby increasing the breakdown voltage of the HEMT.

FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) 100 of an embodiment of the present disclosure. The high electron mobility transistor 100 includes a substrate 101. In some embodiments, the material of the substrate 101 may include ceramic, silicon carbide (SiC), aluminum nitride (AlN), sapphire or silicon. When the substrate 101 is a material with high hardness, high thermal conductivity and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. The above-mentioned high hardness, high thermal conductivity and low electrical conductivity are relative to a single crystal silicon substrate, and a high-voltage semiconductor device refers to a semiconductor device with an operating voltage higher than 50V. In some embodiments, the substrate 101 may be a semiconductor on insulator (SOI) substrate. In other embodiments, the substrate 101 may be provided by a composite substrate (also referred to as a QST substrate) in which a core substrate is wrapped by a composite material layer, wherein the core substrate comprises ceramic, silicon carbide, aluminum nitride, sapphire or silicon, and the composite material layer comprises an insulating material layer and a semiconductor material layer, wherein the insulating material layer may be a single layer or multiple layers of silicon oxide, silicon nitride or silicon oxynitride, and the semiconductor material layer may be silicon or polycrystalline silicon, and the composite material layer located on the back side of the core substrate is removed by a thinning process, such as by a grinding or etching process, so that the back side of the core substrate is exposed.

In addition, the high electron mobility transistor 100 further includes a buffer layer 103, a semiconductor channel layer 105, and a semiconductor barrier layer 107 stacked sequentially from bottom to top on the substrate 101, and the buffer layer 103 can be used to reduce the stress or lattice mismatch between the substrate 101 and the semiconductor channel layer 105. In some embodiments, a nucleation layer (not shown) can be disposed between the buffer layer 103 and the substrate 101, and a high resistance layer (or electrical isolation layer) (not shown) can be disposed between the buffer layer 103 and the semiconductor channel layer 105. The materials of the seed layer, buffer layer 103, high resistance layer, semiconductor channel layer 105 and semiconductor barrier layer 107 include compound semiconductors. In some embodiments, the seed layer is, for example, an aluminum nitride (AlN) layer, and the buffer layer 103 may be a superlattice (SL) structure, for example, a plurality of layers of aluminum gallium nitride (AlN) alternately stacked. The semiconductor channel layer 105 is, for example, an undoped gallium nitride (u-GaN) layer. The semiconductor barrier layer 107 is a compound semiconductor layer having a larger energy gap than the semiconductor channel layer 105, such as an aluminum gallium nitride (AlGaN) layer, but is not limited thereto. The composition and structural configuration of the above-mentioned compound semiconductor layers of the high electron mobility transistor 100 can be determined according to various requirements of electronic components.

Still referring to FIG. 1 , the high electron mobility transistor 100 further includes a source electrode 125 and a drain electrode 127 disposed on the semiconductor channel layer 105. In some embodiments, the source electrode 125 and the drain electrode 127 may pass through the semiconductor barrier layer 107 and extend downward into the semiconductor channel layer 105. In other embodiments, as shown in FIG. 1 , the source electrode 125 and the drain electrode 127 may pass through the semiconductor barrier layer 107 and be located on the top surface of the semiconductor channel layer 105. In some other embodiments, the source electrode 125 and the drain electrode 127 may be disposed on the top surface of the semiconductor barrier layer 107. In addition, a semiconductor cap layer 109 may be disposed on the semiconductor barrier layer 107. In one embodiment, the semiconductor cap layer 109 is, for example, a p-type doped gallium nitride (p-GaN) layer. In addition, the first dielectric layer 110 is disposed on the source electrode 125, the semiconductor cap layer 109 and the drain electrode 127. In one embodiment, the first dielectric layer 110 may include multiple layers of dielectric materials, such as a first sublayer 110-1 and a second sublayer 110-2, wherein the first sublayer 110-1 is composed of, for example, silicon oxynitride (SiON), and the second sublayer 110-2 is composed of, for example, silicon oxide (SiO ₂ ), but is not limited thereto. The first dielectric layer 110 may also be a single layer of dielectric material and may include other low dielectric constant dielectric materials. In addition, the second dielectric layer 120 is also disposed on the source electrode 125, the semiconductor cap layer 109 and the drain electrode 127, and is located below the first dielectric layer 110. The second dielectric layer 120 is composed of, for example, silicon oxide (SiO ₂ ). According to some embodiments of the present disclosure, the high electron mobility transistor 100 further includes an etch stop layer (CESL) 122 disposed on the second dielectric layer 120. In one embodiment, the etch stop layer 122 is composed of, for example, silicon nitride (SiNx).

In addition, the high electron mobility transistor 100 further includes a first via 131 that penetrates the first dielectric layer 110, the etch stop layer 122, and the second dielectric layer 120 and extends downward to the semiconductor cap layer 109 to contact the top surface of the semiconductor cap layer 109. The gate electrode 129 is disposed on the first dielectric layer 110 and contacts the first via 131. According to some embodiments of the present disclosure, as shown in FIG. 1 , the bottom surface of the gate electrode 129 is on the same plane as the top surface of the first dielectric layer 110, and the first via 131 is entirely located in the first dielectric layer 110, the etch stop layer 122, the second dielectric layer 120, and other dielectric layers above the semiconductor cap layer 109, and the top surface of the first via 131 is on the same plane as the top surface of the first dielectric layer 110. In addition, the gate electrode 129 and the first via 131 are formed of the same conductive material, so that no interface is generated between the gate electrode 129 and the first via 131. In addition, in one embodiment, the high electron mobility transistor 100 may include a semiconductor cap layer 109, and the gate electrode 129 may apply a voltage to the semiconductor cap layer 109 through the first via 131 to form an enhanced mode HEMT.

According to some embodiments of the present disclosure, the high electron mobility transistor 100 at least includes a first field plate 111 disposed in a first dielectric layer 110, and a second field plate 112 disposed on the first dielectric layer 110, and the second field plate 112 contacts the first field plate 111. As shown in FIG. 1 , the top surface of the first field plate 111 is on the same plane as the top surface of the first dielectric layer 110, and the bottom surface of the first field plate 111 contacts the top surface of the etch stop layer 122, and the bottom surface of the second field plate 112 is on the same plane as the top surface of the first dielectric layer 110. The second field plate 112 is entirely located above the top surface of the first dielectric layer 110, and the first field plate 111 is entirely located below the top surface of the first dielectric layer 110, so that the first field plate 111 and the second field plate 112 have different distances from the semiconductor channel layer 105, thereby having the effect of at least two field plates. In addition, the first field plate 111 and the second field plate 112 are formed of the same conductive material, so there is no interface between the first field plate 111 and the second field plate 112.

In addition, according to some embodiments of the present disclosure, since the first field plate 111 is made by first etching an opening in the first dielectric layer 110 and then filling the opening with a conductive material, the angle between the side wall and the bottom surface of the opening can be controlled to be blunt by adjusting the parameters of the etching process, so that the angle θ between the side wall and the bottom surface of the formed first field plate 111 is greater than 90 degrees, and the cross-sectional area of the first field plate 111 increases from bottom to top. Since the angle between the side wall and the bottom surface of the first field plate 111 is blunt, it can avoid the electric field from being concentrated at the corner of the bottom edge of the first field plate 111, so that the electric field can be dispersed more effectively, thereby achieving the effect of increasing the breakdown voltage of the high electron mobility transistor 100.

Still referring to FIG. 1 , the high electron mobility transistor 100 further includes a second via 132 and a third via 133, both of which penetrate the first dielectric layer 110, the etch stop layer 122 and the second dielectric layer 120, and extend downward to the source electrode 125 and the drain electrode 127, respectively, wherein the second via 132 contacts the top surface of the source electrode 125 to generate an electrical connection, and the third via 133 contacts the top surface of the drain electrode 127 to generate an electrical connection. In addition, the first wire 135 and the second wire 137 are both disposed on the first dielectric layer 110, wherein the first wire 135 is electrically connected to the second via 132, and the second wire 137 is electrically connected to the third via 133. According to some embodiments of the present disclosure, the first wire 135 and the second via 132 are formed of the same conductive material, so no interface is generated between the first wire 135 and the second via 132, and the second wire 137 and the third via 133 are also formed of the same conductive material, so no interface is generated between the second wire 137 and the third via 133. In addition, according to some embodiments of the present disclosure, the first field plate 111, the second field plate 112, the first via 131, the gate electrode 129, the second via 132, the third via 133, the first wire 135, the second wire 137, and the third wire (not shown) connected to the gate electrode 129 of the high electron mobility transistor 100 are all composed of the first metal layer.

In one embodiment, as shown in FIG. 1 , the high electron mobility transistor 100 may further include a third field plate 113 disposed below the second dielectric layer 120 and between the first via 131 and the first field plate 111. The first field plate 111 and the third field plate 113 may partially overlap in the vertical projection direction (e.g., in the XY plane), so that the first field plate 111 has a height step difference. In addition, according to some embodiments of the present disclosure, the source electrode 125, the drain electrode 127 and the third field plate 113 are all formed by the second metal layer. In addition, the high electron mobility transistor 100 may further include a third dielectric layer 130 disposed on the semiconductor barrier layer 107, and the third dielectric layer 130 has an opening exposing the semiconductor cap layer 109, so that the first via 131 can pass through the opening of the third dielectric layer 130, contact and electrically connect to the semiconductor cap layer 109. In some embodiments, a portion 125P of the source electrode 125 and a portion 127P of the drain electrode 127 each extend to the top surface of the third dielectric layer 130, so that a portion 125P of the source electrode 125 and a portion 127P of the drain electrode 127 also have a field plate effect.

In addition, a passivation layer 140 may be formed to cover the second field plate 112, the gate electrode 129, the first conductive line 135, and the second conductive line 137 to protect the high electron mobility transistor 100. The passivation layer 140 may be made of, for example, silicon nitride, silicon oxynitride, other dielectric materials, insulating polymers (such as epoxy resins), or other insulating materials. In addition, according to an embodiment of the present disclosure, the first field plate 111, the second field plate 112 and the third field plate 113 can be electrically connected to the source electrode 125 through other vias (not shown) and/or other wires (not shown), and the source electrode 125 can be electrically coupled to the ground terminal to further reduce the maximum electric field strength, thereby increasing the breakdown voltage of the HEMT.

FIG. 2 is a cross-sectional schematic diagram of a high electron mobility transistor 100 according to another embodiment of the present disclosure. The high electron mobility transistor 100 in FIG. 2 further includes a dielectric block 134 disposed on the third dielectric layer 130, between the semiconductor cap layer 109 and the drain electrode 127, and the dielectric block 134 is laterally separated from the semiconductor cap layer 109 and the drain electrode 127. The dielectric block 134 may extend from a position between the semiconductor cap layer 109 and the first field plate 111 toward the drain electrode 127. In one embodiment, the dielectric block 134 may extend to be aligned with the right edge of the first field plate 111 (as shown in FIG. 2). In another embodiment, the dielectric block 134 may extend to be adjacent to the drain electrode 127, and a portion 127P of the drain electrode 127 may further extend laterally to the top surface of the dielectric block 134, so that the portion 127P of the drain electrode 127 has a height difference and has the effect of two field plates. In some embodiments, the dielectric block 134 may be formed of a high dielectric constant material having a dielectric constant higher than that of the second dielectric layer 120 and the third dielectric layer 130. For example, the dielectric constant of the dielectric block 134 may be higher than the dielectric constant of silicon dioxide, which is 3.9. The composition of the dielectric block 134 may be, for example, silicon nitride (Si ₃ N ₄ ), yttrium oxide (Y ₂ O ₃ ), yttrium titanium oxide (Y ₂ TiO ₅ ), yttrium oxide (Yb ₂ O ₃ ), helium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), silicon oxynitride (SiO _x N _y ) or other high dielectric constant materials. In some other embodiments, the dielectric constant of the dielectric block 134 may be slightly higher than or equal to the dielectric constants of the second dielectric layer 120 and the third dielectric layer 130. For example, the dielectric constant of the dielectric block 134 may be slightly higher than or equal to the dielectric constant of silicon dioxide, which is 3.9. The dielectric block 134 may be made of silicon dioxide or silicon oxynitride.

In addition, the high electron mobility transistor 100 of FIG. 2 further includes a third field plate 113 adjacent to a side surface (e.g., the left side surface) of the dielectric block 134, and a fourth field plate 114 located on the top surface of the dielectric block 134. The third field plate 113 and the fourth field plate 114 are connected to each other and extend continuously from the left side surface of the dielectric block 134 to the top surface of the dielectric block 134. In one embodiment, from a cross-sectional view, the fourth field plate 114 and the dielectric block 134 may form a stepped shape, so that the bottom surface of the first field plate 111 formed directly above the fourth field plate 114 and the dielectric block 134 also has a height difference, thereby allowing the first field plate 111 to have the effect of two field plates. In addition, according to some embodiments of the present disclosure, the source electrode 125, the drain electrode 127, the third field plate 113 and the fourth field plate 114 are all formed by the second metal layer, thereby reducing the process steps and the manufacturing cost. The other component features of the high electron mobility transistor 100 in FIG. 2 can refer to the description of the high electron mobility transistor 100 in FIG. 1 above, and will not be repeated here.

FIG. 3 is a cross-sectional schematic diagram of a high electron mobility transistor 100 according to yet another embodiment of the present disclosure. In the high electron mobility transistor 100 in FIG. 3 , the dielectric block 134 can extend to the middle position of the first field plate 111, and the first field plate 111 partially overlaps with the fourth field plate 114 and the dielectric block 134 in the vertical projection direction (e.g., XY plane), so that the bottom surface of the first field plate 111 formed directly above the fourth field plate 114 and the dielectric block 134 has two height differences, thereby allowing the first field plate 111 to have the effect of three field plates. In addition, the high electron mobility transistor 100 of FIG. 3 further includes another dielectric block 136 disposed on the third dielectric layer 130 and located between the first field plate 111 and the drain electrode 127. In one embodiment, the dielectric block 136 may be laterally separated from both the first field plate 111 and the drain electrode 127. In addition, the high electron mobility transistor 100 of FIG. 3 further includes a fifth field plate 115 adjacent to a side (e.g., left side) of the dielectric block 136, and a sixth field plate 116 located on the top surface of the dielectric block 136. The fifth field plate 115 and the sixth field plate 116 are connected to each other and extend continuously from the left side of the dielectric block 136 to the top surface of the dielectric block 136. According to some embodiments of the present disclosure, the source electrode 125, the drain electrode 127, the third field plate 113, the fourth field plate 114, the fifth field plate 115, and the sixth field plate 116 are all formed by the second metal layer. In addition, in one embodiment, the dielectric block 134 and the dielectric block 136 may have the same composition and may be formed simultaneously by depositing and patterning the same dielectric material layer, thereby reducing the number of process steps and the manufacturing cost. The composition of the dielectric block 134 and the dielectric block 136 can be found in the description of FIG. 2 above, which will not be repeated here.

In one embodiment, the dielectric block 136 may also extend laterally to the adjacent drain electrode 127, and a portion 127P of the drain electrode 127 may further extend laterally to the top surface of the dielectric block 136, so that a portion 127P of the drain electrode 127 has a height difference and has the effect of two field plates. In another embodiment, the dielectric block 136 may also extend laterally to directly below the first field plate 111 and be laterally separated from the dielectric block 134, so that a height step difference is generated on the right bottom surface of the first field plate 111, thereby having the effect of two field plates to adjust the electric field distribution. In this embodiment (not shown), the sixth field plate 116 may be adjacent to a side surface (e.g., the right side surface) of the dielectric block 136, and the fifth field plate 115 may be located on the top surface of the dielectric block 136. The fifth field plate 115 and the sixth field plate 116 are connected to each other and extend continuously from the right side surface of the dielectric block 136 to the top surface of the dielectric block 136. For other component features of the high electron mobility transistor 100 in FIG. 3, please refer to the description of the high electron mobility transistor 100 in FIG. 1, which will not be repeated here. According to some embodiments of the present disclosure, the configuration of the dielectric block and the metal layer can produce the effect of multiple field plates, and the positions of the dielectric block and the field plate can be adjusted according to the electrical requirements of the high electron mobility transistor 100, so that the electric field is redistributed to meet the various electrical requirements of the high electron mobility transistor 100.

FIG. 4, FIG. 5, FIG. 6 and FIG. 7 are cross-sectional schematic diagrams of some stages of a method for manufacturing a high electron mobility transistor according to an embodiment of the present disclosure. Referring to FIG. 4, in step S101, a substrate 101 is first provided, and then a buffer layer 103, a semiconductor channel layer 105 and a semiconductor barrier layer 107 are sequentially formed on the substrate 101. Then, a semiconductor cap layer 109 can be formed on the semiconductor barrier layer 107 through deposition and patterning processes. Thereafter, a third dielectric layer 130 is deposited to cover the semiconductor cap layer 109 and the semiconductor barrier layer 107. The composition of some components and/or material layers mentioned in Figures 4, 5, 6 and 7 can be found in the description of Figure 1 and will not be repeated here.

Next, still referring to FIG. 4 , in step S103, an etching process may be used to form an opening 124 for a source electrode and an opening 126 for a drain electrode in the third dielectric layer 130, the semiconductor barrier layer 107, and the semiconductor channel layer 105. In some embodiments, by controlling the etching depth, the bottom surfaces of the openings 124 and 126 may be located on the top surface of the semiconductor barrier layer 107, or on the top surface of the semiconductor channel layer 105, or at a depth position in the semiconductor channel layer 105. Then, a second metal layer is deposited on the third dielectric layer 130, and the second metal layer fills the openings 124 and 126. In some embodiments, the second metal layer is composed of, for example, titanium (Ti), aluminum (Al), nickel (Ni), molybdenum (Mo), gold (Au), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) or a multi-layer stacked structure of the aforementioned metal layers. Then, the second metal layer is patterned by photolithography and etching processes to simultaneously form a source electrode 125, a drain electrode 127 and a third field plate 113, wherein the source electrode 125 is located in the opening 124 and is formed on the semiconductor channel layer 105, a portion 125P of the source electrode 125 can extend to the top surface of the third dielectric layer 130, and the drain electrode 127 is located in the opening 124. 26 and formed on the semiconductor channel layer 105, a portion 127P of the drain electrode 127 may also extend to the top surface of the third dielectric layer 130, and the third field plate 113 is formed on the top surface of the third dielectric layer 130, and the third field plate 113 is laterally separated from the semiconductor cap layer 109 and the drain electrode 127 and is located between the semiconductor cap layer 109 and the drain electrode 127. Then, the second dielectric layer 120 and the etch stop layer 122 are sequentially deposited conformally on the third dielectric layer 130, and cover the source electrode 125, the semiconductor cap layer 109, the third field plate 113 and the drain electrode 127.

Next, referring to FIG. 5, in step S105, the first sublayer 110-1 and the second sublayer 110-2 of the first dielectric layer 110 are sequentially deposited on the etch stop layer 122, and the second sublayer 110-2 is subjected to a chemical mechanical planarization (CMP) process, so that the first dielectric layer 110 has a flat surface. The first dielectric layer 110 covers the source electrode 125, the semiconductor cap layer 109, the third field plate 113 and the drain electrode 127.

Still referring to FIG. 5 , in step S107, a first photomask (not shown) is used, and deposition, photolithography and etching processes are used to form a patterned mask 150 on the flat surface of the first dielectric layer 110. Then, a first opening 151 is formed in the first dielectric layer 110 through the opening of the patterned mask 150 and the first etching process. According to some embodiments of the present disclosure, the first etching process stops on the etching stop layer 122, so that the bottom surface of the first opening 151 is located on the etching stop layer 122, and by adjusting the parameters of the first etching process, the angle θ between the sidewall and the bottom surface of the first opening 151 can be greater than 90 degrees to generate a blunt angle. In addition, by adjusting the opening position of the patterned mask 150, the first opening 151 can overlap with part of the third field plate 113 in the vertical projection direction, so that the bottom surface of the first opening 151 has a height difference. Afterwards, the patterned mask 150 can be removed by a stripping process, such as an ashing or immersion process.

Next, referring to FIG. 6 , in step S109 , after removing the patterned mask 150 , another patterned mask 160 is formed on the flat surface of the first dielectric layer 110 using a second mask (not shown) and deposition, photolithography and etching processes. Then, through the multiple openings of the patterned mask 160 and the second etching process, the first dielectric layer 110, the etch stop layer 122, the second dielectric layer 120 and the third dielectric layer 130 are etched to form a second opening 152, a third opening 153 and a fourth opening 154, wherein the second opening 152 exposes the semiconductor cap layer 109, the third opening 153 exposes the source electrode 125, and the fourth opening 154 exposes the drain electrode 127. Afterwards, the patterned mask 160 can be removed through a stripping process.

Still referring to Figure 6, in step S111, after removing the patterned mask 160, a first metal layer 161 is deposited on the first dielectric layer 110, and the first metal layer 161 also fills the first opening 151, the second opening 152, the third opening 153 and the fourth opening 154 to respectively form a first field plate 111 in the first opening 151, a first conductive hole 131 in the second opening 152, a second conductive hole 132 in the third opening 153, and a third conductive hole 133 in the fourth opening 154. Among them, the bottom surface of the first field plate 111 formed in the first opening 151 has a height difference, the first conductive hole 131 is formed on the semiconductor cap layer 109 to serve as a gate contact, the second conductive hole 132 is formed on the source electrode 125 to serve as a source contact, and the third conductive hole 133 is formed on the drain electrode 127 to serve as a drain contact. In some embodiments, the first metal layer 161 is composed of, for example, metal, polysilicon, or metal silicide, wherein the metal is, for example, nickel (Ni), gold (Au), platinum (Pt), tungsten (W), titanium (Ti), aluminum (Al), molybdenum (Mo), or a multi-layer stacked structure of the aforementioned metal layers, and the metal silicide is, for example, the silicide of the aforementioned metals.

Then, referring to FIG. 7 , in step S113, a third photomask (not shown) is used, and deposition, photolithography and etching processes are used to form another patterned mask 170 on the surface of the first metal layer 161. Through the multiple openings of the patterned mask 170 and the third etching process, the first metal layer 161 is patterned to form the second field plate 112, the gate electrode 129, the first wire 135 and the second wire 137. At the same time, the patterning of the first metal layer 161 also forms a third wire (not shown) connected to the gate electrode 129. The second field plate 112 contacts the first field plate 111 and is entirely located above the first field plate 111. The gate electrode 129 contacts and is electrically connected to the first via 131 and is located directly above the semiconductor cap layer 109. The first wire 135 is electrically connected to the second via 132 so that the first wire 135 is electrically coupled to the source electrode 125. The second wire 137 is electrically connected to the third via 133 so that the second wire 137 is electrically coupled to the drain electrode 127. Afterwards, the patterned mask 170 can be removed by a stripping process. Then, a protective layer 140 is formed by a deposition process to cover the second field plate 112, the gate electrode 129, the first wire 135, the second wire 137 and the first dielectric layer 110 to complete the high electron mobility transistor 100 of FIG. 1.

FIG. 8, FIG. 9 and FIG. 10 are cross-sectional schematic diagrams of the intermediate stages of the manufacturing method of the high electron mobility transistor of another embodiment of the present disclosure. First, referring to the description of step S101 of FIG. 4, after step S101 of FIG. 4 is completed, then referring to FIG. 8, in step S201, a fourth mask (not shown) is used to form a dielectric block 134 on the third dielectric layer 130 by deposition, photolithography and etching processes. The dielectric block 134 is laterally separated from the semiconductor cap layer 109 and is located on the semiconductor barrier layer 107.

Still referring to FIG. 8 , in step S203, an etching process may be used to form an opening 124 for a source electrode and an opening 126 for a drain electrode in the third dielectric layer 130 and the semiconductor barrier layer 107. For related details, please refer to the description of step S103 in FIG. 4 . Then, a second metal layer is deposited on the semiconductor channel layer 105, the third dielectric layer 130 and the dielectric block 134, and the second metal layer is filled in the openings 124 and 126. Thereafter, a fifth photomask (not shown) is used to pattern the second metal layer by photolithography and etching processes to simultaneously form a source electrode 125, a drain electrode 127, a third field plate 113, and a fourth field plate 114, wherein the source electrode 125 is filled in the opening 124 and formed on the semiconductor channel layer 105, a portion 125P of the source electrode 125 may extend to the top surface of the third dielectric layer 130, and the drain electrode 127 is filled in the opening 126 and formed on the semiconductor channel layer 105. A portion 127P of the drain electrode 127 may also extend to the top surface of the third dielectric layer 130, the third field plate 113 is adjacent to the side surface of the dielectric block 134, the fourth field plate 114 is formed on the top surface of the dielectric block 134, and the third field plate 113 and the fourth field plate 114 are connected to each other, extending continuously from the side surface of the dielectric block 134 to the top surface of the dielectric block 134, the third field plate 113 is laterally separated from the semiconductor cap layer 109, and the fourth field plate 114 is laterally separated from the drain electrode 127.

In other embodiments, in step S201 of FIG. 8, another dielectric block, such as the dielectric block 136 shown in FIG. 3, can be formed simultaneously, and in step S203 of FIG. 8, other field plates, such as the fifth field plate 115 and the sixth field plate 116 shown in FIG. 3, can be formed simultaneously. According to some embodiments of the present disclosure, the source electrode 125, the drain electrode 127, and multiple dielectric blocks and multiple field plates between the semiconductor cap layer 109 and the drain electrode 127 can be manufactured simultaneously using two photomasks and a metal layer.

Next, referring to FIG. 9, in step S205, the second dielectric layer 120, the etch stop layer 122, the first sublayer 110-1 and the second sublayer 110-2 of the first dielectric layer 110 are sequentially deposited on the source electrode 125, the drain electrode 127, the semiconductor cap layer 109, the third dielectric layer 130, the third field plate 113, the fourth field plate 114 and the dielectric block 134. As shown in FIG. 9, after the deposition process is completed, the second sublayer 110-2 of the first dielectric layer 110 has an undulating surface profile.

Then, referring to FIG. 10, in step S207, a chemical mechanical planarization (CMP) process is performed on the second sub-layer 110-2 of the first dielectric layer 110, so that the first dielectric layer 110 has a flat surface. Next, referring to the description of step S107 in FIG. 5, a patterned mask 150 is formed on the flat surface of the first dielectric layer 110, and a first opening 151 is formed in the first dielectric layer 110 through the opening of the patterned mask 150 and the first etching process. According to some embodiments of the present disclosure, the first etching process stops on the etching stop layer 122, and the angle θ between the sidewall and the bottom surface of the first opening 151 can be greater than 90 degrees to generate a blunt angle. Afterwards, refer to the description of step S109 and step S111 in FIG. 6 and step S113 in FIG. 7, and continue with the subsequent process steps to complete the high electron mobility transistor 100 in FIG. 2 and FIG. 3.

According to some embodiments of the present disclosure, three masks and a metal layer are used to simultaneously manufacture the first field plate, the second field plate, the gate contact, the gate electrode, the gate wire, the source contact, the source wire, the drain contact and the drain wire, thereby reducing the process steps and manufacturing costs of the high electron mobility transistor (HEMT). In addition, since the first field plate is formed in the first opening of the first dielectric layer, the angle θ between the side wall and the bottom surface of the first field plate can be greater than 90 degrees to generate a blunt angle, thereby avoiding the electric field from being concentrated at the corner of the bottom edge of the first field plate, so as to more effectively disperse the electric field and thereby increase the breakdown voltage of the HEMT.

In addition, in some embodiments of the present disclosure, a dielectric block formed on a semiconductor barrier layer and located between a semiconductor cap layer and a drain electrode can be used to simultaneously manufacture a source electrode, a drain electrode, and two field plates extending continuously from the side of the dielectric block to its top surface using a photomask and a metal layer, so as to further reduce the process steps of the HEMT and reduce the manufacturing cost.

In addition, according to some embodiments of the present disclosure, a first field plate is provided between the gate electrode and the drain electrode of the HEMT, and the first field plate can be electrically coupled to the source electrode or the ground terminal, so that the first field plate has a shielding effect on the capacitance between the gate electrode and the drain electrode, thereby reducing the gate-drain capacitance (Cgd) and the reverse transfer capacitance (Crss) by about 2%, while the gate-source capacitance (Cgs) and the input power capacitance (Ciss) are substantially unaffected, and the output power capacitance (Coss) is maintained unchanged. Therefore, the HEMT of some embodiments disclosed herein can avoid Miller turn-on, thereby reducing switch loss and shortening switching time, thereby improving the electrical performance and reliability of the HEMT. In addition, some embodiments disclosed herein can maintain the electric field distribution characteristics required by the HEMT under the high voltage operating condition of about 100V to about 800V applied to the drain electrode, which means that the HEMT disclosed herein can be applied to high voltage applications.

The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: High electron mobility transistor

101: Base

103: Buffer layer

105: Semiconductor channel layer

107: Semiconductor barrier layer

109:Semiconductor capping

110: First dielectric layer

110-1: First sublayer

110-2: Second sublayer

111: First board

112: Second board

113: The third board

120: Second dielectric layer

122: Etch stop layer

125: Source electrode

125P: Part of the source electrode

127: Drain electrode

127P: Part of the drain electrode

129: Gate electrode

130: Third dielectric layer

131: First conductive hole

132: Second conductive hole

133: Third conductive hole

135: First conductor

137: Second wire

140: Protective layer

θ: angle of intersection

Claims (20)

A high electron mobility transistor comprises: a semiconductor channel layer and a semiconductor barrier layer, which are sequentially arranged on a substrate; a source electrode and a drain electrode, which are arranged on the semiconductor channel layer; a semiconductor cap layer, which is arranged on the semiconductor barrier layer; a first dielectric layer, which is arranged on the source electrode, the semiconductor cap layer and the drain electrode; a first conductive layer; A hole penetrates the first dielectric layer and extends downward to the semiconductor cap layer; a gate electrode is disposed on the first dielectric layer and contacts the first via hole; a first field plate is disposed in the first dielectric layer, wherein the bottom surface of the first via hole is lower than the bottom surface of the first field plate; and a second field plate is disposed on the first dielectric layer and contacts the first field plate. A high electron mobility transistor as described in claim 1, wherein the first via, the gate electrode, the first field plate and the second field plate are all formed by a first metal layer. A high electron mobility transistor as described in claim 1, wherein the angle between the side wall and the bottom surface of the first field plate is greater than 90 degrees. The high electron mobility transistor as described in claim 1 further comprises: a second dielectric layer disposed on the source electrode, the semiconductor cap layer and the drain electrode and located below the first dielectric layer; and an etch stop layer disposed on the second dielectric layer, wherein the bottom surface of the first field plate contacts the etch stop layer. A high electron mobility transistor as described in claim 4, wherein the first via also penetrates the etch stop layer and the second dielectric layer. The high electron mobility transistor as described in claim 4 further includes: a second via hole penetrating the first dielectric layer, the etch stop layer and the second dielectric layer, and extending downward to the source electrode; a first conductive line disposed on the first dielectric layer and contacting the second via hole; a third via hole penetrating the first dielectric layer, the etch stop layer and the second dielectric layer, and extending downward to the drain electrode; and a second conductive line disposed on the first dielectric layer and contacting the third via hole. A high electron mobility transistor as described in claim 6, wherein the second via, the third via, the first wire, the second wire, the first via, the gate electrode, the first field plate and the second field plate are all formed by a first metal layer. The high electron mobility transistor as described in claim 4 further includes a third field plate disposed below the second dielectric layer and between the first via and the first field plate, wherein the source electrode, the drain electrode and the third field plate are all formed by a second metal layer. A high electron mobility transistor as described in claim 8, wherein the first field plate and the third field plate partially overlap in the vertical projection direction, and the first field plate has a height difference. The high electron mobility transistor as described in claim 1 further includes a third dielectric layer disposed on the semiconductor barrier layer, wherein a portion of the source electrode and a portion of the drain electrode each extend to the top surface of the third dielectric layer. The high electron mobility transistor as described in claim 1 further comprises: a dielectric block located between the semiconductor cap layer and the drain electrode and laterally separated from the semiconductor cap layer and the drain electrode; a third field plate adjacent to a side surface of the dielectric block; and a fourth field plate located on a top surface of the dielectric block, wherein the third field plate and the fourth field plate are connected to each other and extend continuously from the side surface of the dielectric block to the top surface of the dielectric block. A high electron mobility transistor as described in claim 11, wherein the source electrode, the drain electrode, the third field plate and the fourth field plate are all formed by a second metal layer. A high electron mobility transistor as described in claim 11, wherein the first field plate, the fourth field plate and the dielectric block partially overlap in the vertical projection direction, and the first field plate has two height differences. A method for manufacturing a high electron mobility transistor includes: providing a substrate; sequentially forming a semiconductor channel layer and a semiconductor barrier layer on the substrate; forming a semiconductor cap layer on the semiconductor barrier layer; forming a source electrode and a drain electrode on the semiconductor channel layer; forming a first dielectric layer on the source electrode, the semiconductor cap layer and the drain electrode; forming a first opening in the first dielectric layer; forming a second opening through the first dielectric layer; A first dielectric layer is formed on the first dielectric layer and extends downward to the semiconductor cap layer; a first metal layer is deposited on the first dielectric layer and fills the first opening and the second opening to form a first field plate in the first opening and a first via hole in the second opening, respectively, wherein the bottom surface of the first via hole is lower than the bottom surface of the first field plate; and the first metal layer is patterned to form a gate electrode contacting the first via hole and a second field plate contacting the first field plate. The manufacturing method of the high electron mobility transistor as described in claim 14, before forming the first dielectric layer, further includes: depositing a second dielectric layer to cover the source electrode, the semiconductor cap layer and the drain electrode; and depositing an etch stop layer on the second dielectric layer, wherein a first etching process for forming the first opening stops on the etch stop layer, and the angle between the side wall and the bottom surface of the first opening is greater than 90 degrees. A method for manufacturing a high electron mobility transistor as described in claim 15, wherein a second etching process for forming the second opening also etches through the etch stop layer and the second dielectric layer, and the second etching process also simultaneously forms a third opening to expose the source electrode, and a fourth opening to expose the drain electrode. A method for manufacturing a high electron mobility transistor as described in claim 16, wherein the first metal layer also fills the third opening and the fourth opening simultaneously to form a second conductive hole on the source electrode and a third conductive hole on the drain electrode, respectively, and the patterning of the first metal layer also simultaneously forms a first conductive wire electrically connected to the second conductive hole and a second conductive wire electrically connected to the third conductive hole. A method for manufacturing a high electron mobility transistor as described in claim 17, wherein a first mask is used to form the first opening, a second mask is used to form the second opening, the third opening and the fourth opening, and a third mask is used to form the second field plate, the gate electrode, the first conductive line and the second conductive line. The method for manufacturing a high electron mobility transistor as described in claim 14 further includes: depositing a second metal layer on the semiconductor barrier layer; and patterning the second metal layer to simultaneously form the source electrode, the drain electrode and a third field plate, wherein the first field plate and the third field plate partially overlap in the vertical projection direction, and the first field plate has a height step difference. The method for manufacturing a high electron mobility transistor as described in claim 14 further includes: forming a dielectric block on the semiconductor barrier layer; depositing a second metal layer on the dielectric block and the semiconductor channel layer; and patterning the second metal layer to simultaneously form the source electrode, the drain electrode, a third field plate and a fourth field plate, wherein the third field plate is adjacent to a side surface of the dielectric block, the fourth field plate is formed on a top surface of the dielectric block, and the third field plate and the fourth field plate are connected to each other and extend continuously from the side surface of the dielectric block to the top surface.

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