TWI849732B - Hyperdimension computing device - Google Patents

Abstract

A hyper-dimensional computation device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receive at least one of the data vectors, and generates a bundled data vector according to the at least one of the data vectors.

Description

Ultra-high dimensional computing device

The present invention relates to an ultra-high dimensional computing device, and in particular to an ultra-high dimensional computing device implemented by using a non-volatile memory.

Ultra-high dimensional computing refers to the operations performed when the dimensions are in the thousands. When performing data conversion operations, ultra-high dimensional computing can perform operations such as addition, multiplication, and shifting on the data. Among them, in ultra-high dimensional computing, the addition of data can be performed through the majority decision mechanism, the multiplication of data is performed through the exclusive operation of data, and the shift of data is to perform a certain number of bit shifts on the data. Ultra-high dimensional computing is performed on ultra-high dimensional data vectors, which can be classified and stored in associative memory after training. In cognitive technology, ultra-high dimensional computing can be performed through a large number of logic circuits. Such ultra-high-dimensional calculators often require complex circuit architectures and consume a lot of power during operation.

The present invention provides an ultra-high dimensional computing device implemented by using a flash memory.

The ultra-high dimensional computing device of the present invention includes a memory cell array and a first operation circuit. The memory cell array is coupled to a plurality of first word lines. The memory cell array has a plurality of memory cell groups, a plurality of first memory cells in each memory cell group are coupled to the same first word line, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit is coupled to a plurality of first bit lines of the memory cell array, receives at least one of the data vectors through the bit lines, and generates a data vector set according to at least one of the received data vectors.

Based on the above, in the ultra-high dimensional computing device of the present invention, multiple data vectors are stored through multiple memory cell groups of a non-volatile memory cell array. And by providing at least one of the multiple data vectors to the computing circuit, a corresponding data vector set is generated. The ultra-high dimensional computing device of the present invention performs ultra-high dimensional computing and generates a data vector set through the mechanism of in-memory computing and in-memory searching, which can effectively reduce the demand for circuit components, reduce power consumption, and improve the performance of ultra-high dimensional computing.

Please refer to FIG. 1 , which shows a schematic diagram of an ultra-high dimensional computing device of an embodiment of the present invention. The ultra-high dimensional computing device 100 includes a non-volatile memory cell array 110 and an operation circuit 120. The non-volatile memory cell array 110 and the operation circuit 120 are coupled to each other. The non-volatile memory cell array 110 is coupled to a plurality of word lines WL1 to WLN and a plurality of bit lines BL1 to BLM. The non-volatile memory cell array 110 has a plurality of memory cell groups 111 to 11N. The memory cell groups 111 to 11N are respectively coupled to the word lines WL1 to WLN. Each of the memory cell groups 111 to 11N may have a plurality of memory cells. Each of the memory cell groups 111 - 11N can store a data vector.

The operation circuit 120 is coupled to a plurality of bit lines BL1-BLM of the non-volatile memory cell array 110. The operation circuit 120 receives a data vector provided by at least one of the memory cell groups 111-11N via the bit lines BL1-BLM. The operation circuit 120 can generate a bundled vector BHV by integrating one or more received data vectors.

In the present embodiment, the data vector stored in each of the memory cell groups 111~11N can be a multi-n-gram vector. The multiple data vectors respectively recorded by the memory cell groups 111~11N can form all possible permutations and combinations of multiple characters. Specifically, taking each data vector having three English alphabet characters as an example, the multiple data vectors respectively recorded by the memory cell groups 111~11N can be: aaa, aab, aac, ..., zzz, etc. 26 cubed. Of course, in other embodiments of the present invention, each data vector may include not only English alphabet characters, but also special characters (such as spaces, underscores, punctuation marks) and/or numeric characters, etc. There is no specific limitation. The number of characters recorded in each data vector can be determined by the user and is not limited to 3.

In other embodiments of the present invention, the multiple data vectors respectively recorded by the memory cell groups 111-11N may also be multiple data and multiple positions respectively corresponding to the data. These data and the positions respectively corresponding to the data are used to form an image. The data may be used to indicate the grayscale information of the pixel at the position corresponding to the data in the image.

Incidentally, in this embodiment, when generating a data vector set BHV, at least one of the multiple word lines WL1-WLN may be selected. The ultra-high dimensional computing device 100 may enable the selected word lines one by one, or enable them all at once. In this way, the operation circuit 120 may generate a data vector set BHV according to at least one data vector provided by the memory cell group corresponding to the selected word line.

Incidentally, in the present embodiment, the memory cells in the memory cell groups 111-11N are all non-volatile memory cells, such as flash memory cells, ferroelectric RAM (FeRAM) memory cells, resistive memory cells, phase change memory (PCM) memory cells or conductive-bridging RAM (CBRAM) memory cells. The flash memory cells can be floating gate, SONOS or floating dot flash memory cells without any specific limitation. In addition, the non-volatile memory cell array 110 can be a two-dimensional or three-dimensional stacked memory cell array, and there is no specific limitation.

Please refer to FIG. 2 below, which is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. The ultra-high dimensional computing device 200 includes a non-volatile memory cell array 210 and an operation circuit 220. The non-volatile memory cell array 210 and the operation circuit 220 are coupled to each other. The non-volatile memory cell array 210 is coupled to a plurality of word lines WL1~WLN and a plurality of bit lines BL1~BLM. The non-volatile memory cell array 210 has a plurality of memory cell groups 211-1~21N-2. Different from the embodiment of FIG. 1, in this embodiment, the memory cell row corresponding to a word line can be divided into a plurality of memory cell groups. For example, the memory cell rows corresponding to the word line WL1 can be divided into memory cell groups 211-1 and 211-2; the memory cell rows corresponding to the word line WL2 can be divided into memory cell groups 212-1 and 212-2; ...; the memory cell rows corresponding to the word line WLN can be divided into memory cell groups 21N-1 and 21N-2. Each of the memory cell groups 211-1 to 21N-2 can store a data vector.

The operation circuit 220 is coupled to the memory cell groups 211-1 to 21N-1 through the bit lines BL1 to BLA, and is also coupled to the memory cell groups 211-2 to 21N-2 through the bit lines BLA+1 to BLM. The operation circuit 220 can receive a data vector recorded by at least one of the memory cell groups 211-1 to 21N-1 through the bit lines BL1 to BLA, and receive a data vector recorded by at least one of the memory cell groups 211-2 to 21N-2 through the bit lines BLA+1 to BLM, and thereby generate a data vector set BHV.

Please refer to FIG3 , which is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. The ultra-high dimensional computing device 300 includes a non-volatile memory cell array 310, an operation circuit 320, and an encoder 330. The non-volatile memory cell array 310 is coupled to a plurality of word lines WL1 to WLN, and is coupled to the operation circuit 320. The non-volatile memory cell array 310 corresponds to the word lines WL1 to WLN, and includes a plurality of memory cell groups 311 to 31N, wherein each memory cell group 311 to 31N includes a plurality of NAND flash memory cells, and is used to store a data vector.

The operation circuit 320 is coupled to the non-volatile memory cell array 310 through a plurality of bit lines. The operation circuit 320 receives at least one of the data vectors through the bit lines, and generates a data vector set BHV according to at least one of the received data vectors.

In an embodiment of the present invention, in an application related to string processing, the encoder 330 can be used to generate a plurality of multi-element syntax vectors, and store the generated multi-element syntax vectors in memory cell groups 311-31N respectively. The encoder 330 can generate all possible combinations of multi-element syntax vectors corresponding to a plurality of characters according to the arrangement and combination method, and store all possible combinations in memory cell groups 311-31N respectively.

In another embodiment of the present invention, in an application related to image processing, the encoder 330 can analyze multiple positions of an image, and store all possible component information corresponding to all positions in the image and the corresponding position information in the memory cell groups 311-31N respectively. The above-mentioned possible component information can be the grayscale information of the pixel at the position in the image. Among them, a single possible component information and the corresponding position information can be recorded in the same memory cell group 311-31N.

Please refer to FIG4 , which is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. The ultra-high dimensional computing device 400 includes a non-volatile memory cell array 410, an operation circuit 420, and an encoder 430. The non-volatile memory cell array 410 is coupled to a plurality of word lines WL1 to WLN, and is coupled to the operation circuit 420. The non-volatile memory cell array 410 corresponds to the word lines WL1 to WLN, and includes a plurality of memory cell groups 411 to 41N. Compared to the embodiment of FIG. 3 , in the ultra-high dimensional computing device 400 , each memory cell group 411 ˜ 41N of the non-volatile memory cell array 410 includes a plurality of NOR flash memory cells and is used to store a data vector.

In this embodiment, the encoder 430 can be used to perform the same operations as the encoder 330, which will not be described in detail here.

Please refer to Figures 5A to 5C below, which are schematic diagrams of the operation of the ultra-high dimensional computing device of an embodiment of the present invention. In Figure 5A, the ultra-high dimensional computing device 500 includes a non-volatile memory cell array 510 and an operation circuit 520. The non-volatile memory cell array 510 includes memory cell groups 511 to 51N corresponding to a plurality of word lines WL1 to WLN, respectively. The memory cell groups 511 to 51N respectively record a plurality of trigram vectors, such as: aaa, aab, aac, ... zzz. The trigram vectors respectively recorded by the memory cell groups 511 to 51N include all permutations and combinations that can be generated by the English letters and spaces of three characters.

In FIG. 5B , the ultra-high dimensional computing device 500 further includes a word line driver 540, and the operation circuit 520 can be implemented using a counter 520′. When the ultra-high dimensional computing device 500 is to generate a data vector set BHV, the word driver 540 can generate one or more selected word lines according to an input data, and enable at least one of the memory cell groups 511-51N to provide the recorded data vector to the counter 520′ by activating the selected word line. The counter 520′ can also generate the data vector set BHV according to at least one received data vector.

For example, assuming that the input data is a string of eleven (k=11) characters such as "how are you", the character driver 540 can generate multiple selected word lines according to the input data, wherein the number of selected word lines can be greater than k/2. Then, the character driver 540 can sequentially activate the selected word lines one by one, for example, first activate the word line WLA as the selected word line, and make the corresponding memory cell group 51A output a data vector equal to "how" to the counter 520'. The counter 520' can also correspondingly increase the count value by 1 (the initial value of the count value can be equal to 0). Then, the word driver 540 may activate the next word line WLB activated as the selected word line, and make the corresponding memory cell group 51B output a data vector equal to "ow" to the counter 520', and the counter 520' may correspondingly make the count value equal to 2. Similarly, the word driver 540 may sequentially activate at least 5 selected word lines, and the counter 520' may establish a data vector set BHV corresponding to the input data according to the sequentially received data vectors and the corresponding count values.

Incidentally, in this embodiment, a space (" ") is also a character in a data vector. Therefore, the memory cell groups 511-51N can respectively record 27 cubed data vectors.

In FIG. 5C , in another embodiment of the present invention, the operation circuit 520 may be implemented using a sense amplifier 520″. When the ultra-high dimensional computing device 500 is to generate a data vector set BHV, the word driver 540 may generate one or more selected word lines according to the input data, and by simultaneously activating all the selected word lines, the memory cell group corresponding to the selected word line provides at least one recorded data vector to the sense amplifier 520″. The sense amplifier 520″ may also generate a data vector set BHV according to at least one received data vector.

Continuing with the above embodiment, assuming that the input data is a string of eleven (k=11) characters such as "how are you", the character driver 540 can generate a plurality of selected word lines, such as word lines WL1, WL3, WLA and WLC, according to the input data. The character driver 540 can also activate the word lines WL1, WL3, WLA and WLC at the same time. Among them, the data vector recorded by the memory cell group 511 corresponding to the word line WL1 is "are"; the data vector recorded by the memory cell group 513 corresponding to the word line WL3 is "e y" (there is a space between e and y); the data vector recorded by the memory cell group 51A corresponding to the word line WLA is "how"; and the data vector recorded by the memory cell group 51C corresponding to the word line WLC is "you".

Correspondingly, the sense amplifier 520'' can set the current threshold TH according to the k value, wherein the current threshold TH = k/2 multiplied by the read current generated by the memory cell storage data for logic 1. The sense amplifier 520'' also compares the current threshold TH with the total value of the current generated by the memory cell groups 511, 513, 51A and 51C corresponding to the selected word lines (word lines WL1, WL3, WLA and WLC), and thereby generates a data vector set BHV.

Please refer to Figures 6A to 6C below, which are schematic diagrams of the actions of another embodiment of the ultra-high dimensional computing device of the present invention. In this embodiment, the ultra-high dimensional computing device 600 can perform operations on the image 602 as shown in Figure 6A. The image 602 can be divided into 35 partitions, namely 5 rows C1~C5 and 7 columns R1~R7. Each of the partitions has corresponding position information. And according to the content of the image 602, each partition has corresponding component information. In this embodiment, the component information can be the grayscale information of the corresponding partition.

In FIG6B , the ultra-high dimensional computing device 600 includes a non-volatile memory cell array 610 and an operation circuit 620. The non-volatile memory cell array 610 includes memory cell groups 611-61N corresponding to a plurality of word lines WL1-WLN, respectively. The memory cell groups 611-61N can be used to record the position information of all partitions in the corresponding image 602 and all the corresponding possible component information. Taking a monochrome image as an example, the grayscale information of all partitions in the image 602 can be 1 and 0. Therefore, in this embodiment, the memory cell group 611 can record the position information R1C1 and the corresponding possible component information 0; the memory cell group 612 can record the position information R1C1 and the corresponding possible component information 1; the memory cell group 613 can record the position information R2C1 and the corresponding possible component information 0; the memory cell group 614 can record the position information R2C1 and the corresponding possible component information 1; ...; the memory cell group 61N can record the position information RyCx and the corresponding possible component information 1. The contents recorded by the remaining memory cell groups can be deduced in the same way.

Then, in FIG6C , when executing a computation, the word line driver in the ultra-high dimensional computing device 600 can set a plurality of selected word lines according to the input data 601, and provide position information and corresponding possible component information to the computation circuit 620 by activating the selected word lines. In this embodiment, the input data 601 can be an image of the English character "A". Corresponding to different position information R1C1~R7C5, the component information can be 0 or 1.

Taking the position information R1C1 as an example, the component information corresponding to the position information R1C1 in the input data 601 is 1, so the word line WL2 can be set as the selected word line. Taking the position information R2C1 as another example, the component information corresponding to the position information R2C1 in the input data 601 is 1. Therefore, the word line WL4 can be set as the selected word line. The setting method of the remaining selected word lines can be deduced in this way, and will not be explained one by one.

By activating the selected word line, the operation circuit 620 can receive a plurality of component information corresponding to each position information R1C1~R7C5. The operation circuit 620 combines the received plurality of component information corresponding to each position information R1C1~R7C5 to generate a data vector set BHV1. The operation circuit 620 can determine whether to perform a shift operation for each position information R1C1~R7C5 according to whether the component information is 1. For example, if the component information is 0, it means that the corresponding position information does not need to be shifted, and if the component information is 1, it means that the corresponding position information needs to be shifted.

In this embodiment, in order to improve the accuracy of the operation, a majority decision mechanism can be added to the operation circuit 620, and by comparing the operation results of the data vector set BHV1 multiple times, the data vector set BHV1 that occurs the most times is taken out as the final output data vector set BHV, which can effectively improve the accuracy of the operation.

Please refer to FIG. 7, which shows a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. The ultra-high dimensional computing device 700 includes a non-volatile memory cell array 710, operation circuits 720, 740, and an associative memory cell array 730. The non-volatile memory cell array 710 and the operation circuit 720 are coupled to each other. The implementation details of the non-volatile memory cell array 710 and the operation circuit 720 have been described in detail in the aforementioned multiple embodiments and implementation methods, and will not be repeated here.

The operation circuit 740 and the associative memory cell array 730 are coupled to each other. The associative memory cell array 730 has a plurality of memory cell groups 731-73M. Each memory cell group 731-73M has a plurality of memory cells, and each memory cell group 731-73M is used to record classification information. The associative memory cell array 730 is used to receive the data vector set BHV generated by the non-volatile memory cell array 710 and the operation circuit 720 and to perform an in-memory search (IMS) action according to the data vector set BHV to generate the best similarity result CSA.

For the implementation details of the associative memory cell array 730, reference may be made to FIG. 8A and FIG. 8B , which are schematic diagrams of the implementation of the associative memory cell array in the ultra-high dimensional computing device of the embodiment of the present invention. In FIG. 8A , the associative memory cell array 810 is coupled to the operation circuit 820. The associative memory cell array 810 has a plurality of memory cell groups 811 to 81M. Each memory cell group 811 to 81M has a plurality of memory cells, and the memory cells in the same memory cell group are coupled to the same bit line. The memory cell groups 811 to 81M are coupled to the bit lines BL1 to BLM, respectively. In addition, a plurality of memory cells in the same memory cell group 811 ˜ 81M are respectively coupled to a plurality of different word lines WL1 ˜WLP. In this embodiment, the memory cells in the memory cell group 811 ˜ 81M are NAND flash memory cells.

7 , the associative memory cell array 810 compares the data vector set BHV generated by the operation circuit 720 with the classification information in each memory cell group 811-81M to perform an in-memory search operation. The operation circuit 820 can generate the best similarity result CSA closest to the data vector set BHV according to the in-memory search operation.

In FIG8B , the associative memory cell array 830 is coupled to the operation circuit 840. The associative memory cell array 830 has a plurality of memory cell groups 831 to 83M. Each memory cell group 831 to 83M has a plurality of memory cells, and the memory cells in the same memory cell group are commonly coupled to the same bit line. The memory cell groups 831 to 83M are respectively coupled to the bit lines BL1 to BLM. In addition, the plurality of memory cells in the same memory cell group 831 to 83M are respectively coupled to a plurality of different word lines WL1 to WLP. In this embodiment, the memory cells in the memory cell groups 831 to 83M are NOR flash cells.

The associative memory cell array 840 compares the data vector set BHV generated by the operation circuit 720 with the classification information in each memory cell group 831-83M to perform an in-memory search operation. The operation circuit 840 can generate the best similarity result CSA closest to the data vector set BHV according to the in-memory search operation.

Regarding the details of the memory search action in the above-mentioned embodiment, the memory search action known to those skilled in the art can be applied to implement without any specific limitation.

In summary, the ultra-high dimensional computing device of the present invention uses a non-volatile memory cell array to store all possible data vectors in the computing process. By opening the required word lines, the computing circuit generates a data vector set by combining one or more data vectors. This can effectively simplify the circuit complexity of the ultra-high dimensional computing device, increase the working speed of the ultra-high dimensional computing device, and effectively improve the performance of the system.

100, 200, 300, 400, 500, 600, 700: Ultra-high dimensional computing devices 110, 210, 310, 410, 510, 610, 710: Non-volatile memory cell arrays 111~11N, 211-1~21N-2, 311~31N, 411~41N, 511~51N, 611~61N, 811~81M: Memory cell groups 120, 220, 320, 420, 520, 520', 620, 720, 740, 820: Computing circuits 330, 430: Encoders 520'': Sense amplifiers 540: Character drivers 602: Images 601: Input data 730, 810: Associative memory cell array 731~73M: Memory cell group BHV, BHV1: Data vector set BL1~BLM: Bit line C1~C5: Row CSA: Best similarity result R1~R7: Column R1C1~R7C5, RyCx: Position information WL1~WLN, WLA, WLA+1, WLB, WLC, WLP: Word line

FIG1 is a schematic diagram of an ultra-high dimensional computing device of one embodiment of the present invention. FIG2 is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. FIG3 is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. FIG4 is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. FIG5A to FIG5C are schematic diagrams of the ultra-high dimensional computing device of an embodiment of the present invention. FIG6A to FIG6C are schematic diagrams of the ultra-high dimensional computing device of another embodiment of the present invention. FIG7 is a schematic diagram of an ultra-high dimensional computing device of another embodiment of the present invention. FIG8A and FIG8B are schematic diagrams of an implementation of an associative memory cell array in an ultra-high dimensional computing device of an embodiment of the present invention.

100: Ultra-high dimensional computing device

110: Non-volatile memory cell array

111~11N: memory cell group

120: Operational circuit

BHV: Data Vector Set

BL1~BLM: bit line

WL1~WLN: character line

Claims (16)

An ultra-high dimensional computing device includes: a non-volatile memory cell array coupled to a plurality of first word lines, the memory cell array having a plurality of first memory cell groups, a plurality of first memory cells in each of the first memory cell groups coupled to the same first word line, the first memory cell groups storing a plurality of data vectors respectively; a first operation circuit coupled to a plurality of first bit lines of the non-volatile memory cell array, receiving at least one of the data vectors through the bit lines, and performing a first operation circuit on the first memory cell group according to the received first word lines; At least one of the data vectors is used to generate a data vector set; and an associative memory cell array coupled to the operation circuit for storing multiple classification vectors, the associative memory cell array having multiple second memory cell groups, multiple second memory cells of each second memory cell group are respectively coupled to multiple second word lines, and the second memory cell groups are respectively coupled to multiple second bit lines, wherein the associative memory cell array receives the data vector set and performs an in-memory search action according to the data vector set. An ultra-high dimensional computing device as described in claim 1, wherein each of the data vectors is a multi-element grammatical vector. An ultra-high dimensional computing device as described in claim 2, wherein the data vectors include all permutations and combinations of multiple characters. The ultra-high dimensional computing device as described in claim 3 further includes an encoder that generates the multi-element grammatical vectors and stores the multi-element grammatical vectors in the first memory cell groups respectively. The ultra-high dimensional computing device as described in claim 1 further includes: a word line driver for activating a plurality of selected word lines among the first word lines according to an input data. An ultra-high dimensional computing device as described in claim 5, wherein the word line driver activates each selected word line one by one. An ultra-high dimensional computing device as described in claim 6, wherein the computing circuit is a counter. An ultra-high dimensional computing device as described in claim 5, wherein the word line driver synchronously activates the selected word lines. An ultra-high dimensional computing device as described in claim 8, wherein the computing circuit is a sensing amplifier. As described in claim 1, the ultra-high dimensional computing device, wherein corresponding to an image, the data vectors respectively include multiple possible component information and multiple corresponding position information. The ultra-high dimensional computing device as described in claim 10, wherein the computing circuit generates the data vector set based on multiple selected component information and the corresponding position information. The ultra-high dimensional computing device as described in claim 1 further includes: A second operation circuit coupled to the associative memory cell array to generate a best similarity result based on the search action in the memory. The ultra-high dimensional computing device as described in claim 12, wherein the second computing circuit generates the best similarity result according to the current value of each second word line. An ultra-high dimensional computing device as described in claim 13, wherein the second computing circuit generates the best similarity result based on the second word line having the largest current value. An ultra-high dimensional computing device as described in claim 12, wherein the associative memory cell array is an anti-AND flash memory or an anti-OR flash memory. An ultra-high dimensional computing device as described in claim 1, wherein the non-volatile memory cell array is an anti-AND flash memory or an anti-OR flash memory.

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