TWI847524B - Method of fabricating void-free conductive feature of semiconductor device - Google Patents

Abstract

The present application provides a method of fabricating a conductive feature. The method of fabricating the conductive feature includes steps of depositing an insulative layer on a substrate, forming a trench in the insulative layer, performing a cyclic process comprising a sequence of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step has been performed is equal to a first preset number of times and a number of the times the removal step has been performed is equal to a second preset number of times, and filling the trench with the conductive material after the cyclic process.

Description

Method for fabricating void-free conductive features of semiconductor devices

This application claims priority to U.S. Patent Application Nos. 17/837,048 and 17/837,705 (i.e., priority date is "June 10, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a void-free trench filler.

Semiconductor devices are widely used in various systems. Device manufacturing usually involves a series of process steps, including depositing material layers on semiconductor wafers, patterning and etching one or more material layers, doping selected layers, and cleaning the wafer.

The semiconductor manufacturing industry is constantly looking for new ways to improve the performance, reduce costs, and increase the capacitance of semiconductor components. Improvements in capacitance and cost can be achieved by reducing the size of components. For example, in a dynamic random access memory (DRAM) chip, if the size of the memory cell components (such as capacitors and transistors) is reduced, more memory cells can be set on the chip, and the reduction in size leads to a larger memory capacitance of the chip. Cost reduction can be achieved through economies of scale, but unfortunately, when the size of the component components is reduced, performance will be affected. Therefore, a major challenge in the industry is to balance performance improvements with other manufacturing constraints.

The above "prior art" description is only to provide background technology, and does not admit that the above "prior art" description discloses the subject matter of this disclosure, and does not constitute the prior art of this disclosure. Moreover, any description of the above "prior art" should not be regarded as any part of the "prior art" of this case, and does not constitute the prior art of this disclosure.

One aspect of the present disclosure provides a method for manufacturing a conductive feature, the method comprising the following steps: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step is performed a number of times equal to a first preset number of times and the removal step is performed a number of times equal to a second preset number of times; and filling the trench with the conductive material after the cyclic process.

In some embodiments, the deposition step of the cyclic process is stopped before an upper end of the trench is sealed.

In some embodiments, the deposition step of the cyclic process is performed until a thickness of the conductive material deposited on the upper end of the trench is equal to one quarter of a width of the trench.

In some embodiments, the removing step is performed to remove at least a portion of the conductive material accumulated at the upper end of the trench.

In some embodiments, the removing step removes the conductive material isotropically from the trench.

In some embodiments, the trench has an aspect ratio that is substantially greater than or equal to 5.

In some embodiments, the aspect ratio is in a range between 6 and 8.

In some embodiments, the manufacturing method further includes performing a planarization process to remove the conductive material above the insulating layer after the conductive material completely fills the trench.

One aspect of the present disclosure provides a method for manufacturing a conductive feature, the method comprising the following steps: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until a height of the conductive material in the trench is greater than a predetermined height; and filling the trench with the conductive material after the cyclic process.

In some embodiments, the deposition step of the cyclic process is stopped before an upper end of the trench is sealed.

In some embodiments, the deposition step of the cyclic process is performed until a thickness of the conductive material deposited on the upper end of the trench is equal to one quarter of a width of the trench.

In some embodiments, the removing step is performed to remove at least a portion of the conductive material accumulated at the upper end of the trench.

In some embodiments, the predetermined height is equal to half of a height of the groove.

In some embodiments, the trench has an aspect ratio that is substantially greater than or equal to 5.

In some embodiments, the aspect ratio is in a range between 6 and 8.

In some embodiments, the manufacturing method further includes performing a planarization process to remove the conductive material above the insulating layer after the conductive material completely fills the trench.

One aspect of the present disclosure provides a method for manufacturing a conductive feature, the method comprising the following steps: forming a transistor in a substrate; depositing an insulating layer on the substrate; forming a first trench penetrating the insulating layer to expose a portion of a first impurity region of the transistor; performing a first cycle process including a first series of a first deposition step and a first removal step to deposit a conductive material in the first trench until a height of the conductive material in the first trench exceeds a predetermined height; filling the first trench with the conductive material after the first cycle process; forming a storage capacitor contacting the first conductive feature; depositing an isolation layer to cover the insulating layer and the storage capacitor; forming a second trench penetrating the isolation layer and the insulating layer to expose a portion of a second impurity region of the transistor; performing a second cycle process including a second series of a second deposition step and a second removal step to deposit the conductive material in the second trench until the second deposition step is performed a number of times equal to a third preset number of times and the second removal step is performed a number of times equal to a fourth preset number of times; filling the second trench with the conductive material after the second cycle process to form a second conductive feature; and forming a bit line connected to the second conductive feature.

In some embodiments, the first deposition step of the first cycle process is stopped before an upper end of the first trench is sealed, or the second deposition step of the second cycle process is stopped before an upper end of the second trench is sealed.

In some embodiments, during the formation of the first conductive feature, the first deposition step is performed until a first thickness of the conductive material deposited at the upper end of the first trench is equal to one quarter of a width of the first trench, or during the formation of the second conductive feature, the second deposition step is performed until a second thickness of the conductive material deposited at the upper end of the second trench is equal to one quarter of a width of the second trench.

In some embodiments, the first removal step is performed to remove at least a portion of the conductive material accumulated at the upper end of the first trench, or the second removal step is performed to remove at least a portion of the conductive material accumulated at the upper end of the second trench.

In some embodiments, the first removing step removes the conductive material isotropically from the first trench, and the second removing step removes the conductive material isotropically from the second trench.

In some embodiments, the first trench and the second trench each have an aspect ratio that is substantially greater than or equal to 5.

In some embodiments, the aspect ratio is in a range between 6 and 8.

In some embodiments, the manufacturing method further includes performing a planarization process to remove the conductive material overflowing the first trench after the conductive material completely fills the first trench and to remove the conductive material above the insulating layer after the second trench is filled with the conductive material.

In some embodiments, the predetermined height is equal to half of a height of the first groove.

In some embodiments, the formation of the transistor includes the following steps: forming at least one groove in the substrate; depositing a gate insulator conforming to the groove; forming a word line surrounded by the gate insulator; depositing a capping layer in the groove to cover the word line; and introducing a plurality of dopants into the substrate to form the first impurity region and the second impurity region.

In some embodiments, the substrate includes an isolation feature defining a plurality of active regions, wherein the groove extends across the active regions.

In some embodiments, the formation of the storage capacitor includes the steps of: forming a storage node contacting the first conductive feature; depositing a capacitor insulator to seal the storage node; and depositing a top electrode on the capacitor insulator.

In some embodiments, the storage node is in a U-shaped configuration.

By means of the above-mentioned cyclic process including a series of deposition steps and removal steps, the protrusions at the upper ends of the first trench and the second trench are trimmed before the top openings of the first trench and the second trench are sealed; thus, the first conductive feature and the second conductive feature can be manufactured in a void-free manner.

The above has been a fairly broad overview of the features and technical advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other features and advantages that constitute the subject matter of the patent application scope of the present disclosure are described below. Those with ordinary knowledge in the art to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the purpose of the present disclosure. Those with ordinary knowledge in the art to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit or scope of the present disclosure as defined by the attached patent application scope.

10: Semiconductor components

100: Substrate

102: Groove

104: Upper surface

110: Wafer

112: Notch

120: Isolation characteristics

122: Dielectric materials

130: Active zone

200: Access transistor

210: Gate dielectric material

212: Gate insulator

220: Gate material

222: Character line

230: Covering

240: The first impurity zone

250: Second impurity zone

310: Insulation layer

312: First groove

314: Top

316: Side wall

320: Conductive materials

322: Protrusion

324: First conductive feature

325: Porosity

326: Second conductive feature

330: Isolation layer

340: Second groove

342: Top

350: Bit line

410: First pattern mask

412:Window

420: Second pattern mask

422:Window

500: Storage capacitor

510: Storage node

520: Capacitor insulator

530: Top electrode

600: Manufacturing method

3120: Upper corner

A: Area

H: Height

H1: Height

H2: Height

T1:Thickness

T3:Thickness

W1: Width

W2: Width

The present disclosure can be understood more completely by referring to the embodiments and the scope of the patent application, and the present disclosure should also be understood in conjunction with the numbers in the drawings, which represent similar components in all embodiments.

FIG1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

FIG. 2 is a plan view of a substrate of some embodiments of the present disclosure.

Figure 3A is an enlarged view of area A in Figure 1.

FIG3B is a cross-sectional view of a first conductive feature having a void.

FIG4 is a flow chart illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

Figures 5 to 21 illustrate cross-sectional views of some embodiments of the present disclosure at intermediate stages of forming semiconductor devices.

Specific language will be used below to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments and any further application of the principles described in this document are considered commonplace to those of ordinary skill in the art to which the present disclosure relates. Reference numerals may be reused in all embodiments, however, sharing the same reference numeral does not necessarily mean that features of one embodiment are applicable to another embodiment.

It should be understood that although the terms first, second, third, etc. may be used here to describe various components, parts, regions, layers or parts, these components, parts, regions, layers or parts are not limited by these terms, but these terms are only used to distinguish one component, part, region, layer or part from another region, layer or part. Therefore, the first component, part, region, layer or part discussed below can also be referred to as the second component, part, region, layer or part without departing from the teaching of the concept of the present invention.

The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to limit the concepts of the present invention. Unless otherwise expressly specified in the context, the singular forms "a", "an" and "the" used herein are also intended to include the plural forms. It should be understood that the term "including" used in the specification refers to the existence of the described features, complete entities, steps, operations, components or parts, but does not exclude the existence or addition of one or more other features, complete entities, steps, operations, components, parts or groups thereof.

FIG. 1 is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments of the present disclosure. Referring to FIG. 1 , the semiconductor device 10 may be a semiconductor memory device, such as a dynamic random access memory (DRAM), which includes one or more access transistors 200 and one or more storage capacitors 500, wherein the access transistors 200 are turned on in response to a voltage conducted across them, which couples the storage capacitors 500 to the associated bit lines 350. The access transistors 200 shown in FIG. 1 are in the form of recessed access devices (RAD) transistors, however, in some embodiments, the access transistors 200 may be planar access devices (PAD) transistors. Each access transistor 200 acts as a switch for the corresponding storage capacitor 500, that is, the access transistor 200 controls when charge is applied to the storage capacitor 500 and when charge is removed from the storage capacitor 500.

The access transistor 200 is formed in a substrate 100 having a plurality of isolation features 120 defining an active region 130, which may be an elongated island region, as shown in FIG2. For example, the active region 130 may have an elliptical shape as shown in the plan view of FIG2. In addition, the active region 130 may be arranged such that the long axis (along the longitudinal direction) of the active region 130 is neither parallel to the x-axis nor to the y-axis of an orthogonal coordinate system, wherein the x-axis is perpendicular to the y-axis.

The access transistor 200 in the active region 130 includes a plurality of word lines 222 buried in the substrate 100 and covered by a capping layer 230, a plurality of gate insulators 212 disposed between the substrate 100 and the word lines 222, and a plurality of first impurity regions 240 and a second impurity region 250 disposed between the sides of the word lines 222. The word line 222 extending longitudinally along the y-axis and crossing the active region 130 serves as a gate in the access transistor 200 through which it passes, and the bit line 350 extending longitudinally along the x-axis serves as a signal for the source of the access transistor 200 electrically coupled thereto.

The first impurity region 240 and the second impurity region 250 serve as the drain region and the source region of the access transistor 200. The first impurity region 240 of the access transistor 200 is electrically coupled to the storage capacitor 500 via a plurality of first conductive features 324, and the second impurity region 250 of the access transistor 200 is electrically coupled to the bit line 350 via a second conductive feature 326. The semiconductor device 10 further includes an isolation layer 330 covering the storage capacitor 500. The second conductive feature 326 passes through the isolation layer 330 and the insulating layer 310 to electrically couple the bit line 350 on the isolation layer 330 to the access transistor 200.

According to a comparative design of the prior art, the first conductive feature 324 is formed by depositing a conductive material in a trench defined in the insulating layer 310 in a single-step deposition process, and the formation of the second conductive feature 326 is performed in a single deposition process, wherein the conductive material is deposited in the trench defined in the insulating layer 310 and the isolation layer 330. During the single-step deposition process and the single deposition process, the conductive material is continuously deposited until a predetermined time has passed or a predetermined amount of the conductive material has been deposited.

It is generally desirable that all first conductive features 324 and second conductive features 326 are filled with conductive material in a void-free manner, as shown in FIG3A. However, as device geometry shrinks, the aspect ratio of the trenches used to form first conductive features 324 and second conductive features 326 increases. If a single-step deposition process is still used to deposit conductive material in the trenches with a high aspect ratio, undesirable voids 325 may be formed in the first conductive features 324 and second conductive features 326, as shown in FIG3B. The pores 325 increase the resistance of the first conductive feature 324 and the second conductive feature 326, thereby reducing the effect of the first conductive feature 324 and the second conductive feature 326 in providing electrical connectivity and inhibiting the performance of the semiconductor device 10. For this reason, a single-step deposition process is no longer suitable for depositing conductive materials in trenches with a high aspect ratio. A new method for manufacturing the semiconductor device 10 is provided as follows, which includes forming the first conductive feature 324 and the second conductive feature 326 in a pore-free manner.

FIG. 4 is a flow chart illustrating a method 600 for manufacturing a semiconductor device 10 according to some embodiments of the present disclosure. FIG. 5 to FIG. 21 are schematic diagrams illustrating various manufacturing stages constructed according to the method 600 for manufacturing a semiconductor device 10 according to some embodiments of the present disclosure. The stages shown in FIG. 5 to FIG. 21 are also schematically illustrated in the flow chart of FIG. 4. In the subsequent discussion, the manufacturing stages shown in FIG. 5 to FIG. 21 are discussed with reference to the process steps shown in FIG. 4.

Referring to FIG. 5 and FIG. 6 , one or more access transistors 200 are formed in a substrate 100 according to step S602 in FIG. 4 . The substrate 100 includes a wafer 110 and one or more isolation features 120 formed in the wafer 110 to define an active region 130 for forming the access transistor 200. The wafer 110 may be a semiconductor block, a semiconductor on insulator (SOI) substrate, a multi-layer or gradient substrate, or a similar substrate.

The formation of the isolation feature 120 includes (1) using suitable lithography and etching processes to form one or more recesses 112 in the wafer 110 to separate the multiple active regions 130 from each other, (2) using a high-density plasma chemical vapor deposition (CVD) process to deposit a dielectric material 122 (e.g., silicon oxide) in the recess 112, for example, until the dielectric material 122 completely fills the recess 112, and (3) performing a planarization process to remove excess dielectric material 122 above the wafer 110. The planarization of the dielectric material 122 above the recess 112 can be completed by, for example, a chemical mechanical polishing (CMP) process.

Thereafter, some portions of the substrate 100 are etched to form a plurality of grooves 102 spanning a plurality of active regions 130, and the grooves 102 may be formed parallel to the y-axis of the orthogonal coordinate system. In addition, each active region 130 may be divided into three regions by a pair of grooves 102 intersecting the active region 130. In some embodiments, the bottom of the groove 102 may be rounded to reduce defect density and reduce electric field concentration during operation of the semiconductor device 10.

After forming the recess 102, a gate dielectric material 210 and a gate material 220 are sequentially deposited in the recess 102, and then a planarization process is performed to remove portions of the gate dielectric material 210 and the gate material 220 located above an upper surface 104 of the semiconductor wafer 100. The gate dielectric material 210 including oxide, nitride, oxynitride or high-k material covers an exposed portion of the substrate 100 but does not completely fill the recess 102. The gate dielectric material 210 may be deposited with a substantially uniform thickness using a CVD process, an atomic layer deposition (ALD) process or a similar process. A gate material 220 including polysilicon is deposited on the gate dielectric material 210 using a CVD process, a physical vapor deposition (PVD) process, an ALD process, or other suitable process until the groove 102 is completely filled. In some embodiments, the polysilicon is undoped. The gate dielectric material 210 and the portion of the gate material 220 that overflows the groove 102 may be removed using an etching process and/or a grinding process.

Next, the gate material 220 is sunken below the upper surface 104 of the substrate 100, as shown in FIG. 6, thereby forming a plurality of word lines 222. In some embodiments, the gate dielectric material 210 can be selectively sunken below the upper surface 104 of the substrate 100 to form a gate insulator 212.

After forming the gate insulator 212 and the word line 222, a capping layer 230 is deposited in the groove 102 to cover the gate insulator 212 and the word line 222. For example, the capping layer 230 may include silicon oxide, silicon nitride, silicon oxynitride, zirconia or zirconium dioxide. Thereafter, dopants are introduced into the substrate 100 to form a plurality of first impurity regions 240 and second impurity regions 250 between the sides of the word line 222, thereby completely forming the (recessed) access transistor 200.

7 , according to step S604 in FIG. 4 , an insulating layer 310 is deposited to cover the access transistor 200. The insulating layer 310 may be formed by uniformly depositing a dielectric material using a CVD process to cover the upper surface 104 of the substrate 100 and the access transistor 200. Alternatively, the insulating layer 310 may be formed on the substrate 100 and on the access transistor 200 using a spin coating process. The insulating layer 310 may be planarized using, for example, a CMP process to produce an acceptable flat profile. As described below, the flat profile allows the first trench to be patterned using a lithography apparatus with a reduced depth of field. The insulating layer 310 may include oxide, tetraethoxysilane (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), TONEN silazane (TOSZ), or a combination thereof.

Thereafter, a first pattern mask 410 including a plurality of windows 412 is formed by the following steps, including (1) conformingly coating a photosensitive material on the insulating layer 310, (2) exposing portions of the photosensitive material to radiation (not shown), and (3) developing the photosensitive material to form windows 412 defining a pattern etched through the insulating layer 310.

Referring to FIG. 8 , according to step S606 in FIG. 4 , an etching process is performed to remove the portion of the insulating layer 310 that is not protected by the pattern mask 410 , thereby forming a plurality of first trenches 312 . After the etching process, some portions of the first impurity region 240 are exposed. For example, the insulating layer 310 is etched using a reactive ion etching (RIE) process.

The first trench 312 passing through the insulating layer 310 has a width W1 and a height H1. In addition, the first trench 312 has an aspect ratio of about 5 or more (i.e., height H1 divided by width W1). In some embodiments, the aspect ratio of each first trench 312 is in a range between 6 and 8. After forming the first trench 312, the pattern mask 410 is removed using an ashing process or a wet stripping process, wherein the wet stripping process can chemically change the pattern mask 410 so that it is no longer attached to the insulating layer 310.

Thereafter, a series of alternating deposition steps and removal steps are performed to deposit a conductive material 320 in the first trench 312. A deposition step is performed to deposit the conductive material 320 in the first trench 312, for example, using a low-pressure CVD process, and a removal step is performed to remove some portions of the previously deposited conductive material 320 from areas where deposition is not required but cannot be avoided. In some embodiments, doped polysilicon is used as the conductive material 320.

The cyclic process is illustrated starting from FIG9 . Referring to FIG9 , according to step S608 in FIG4 , before the top opening of the first trench 312 is sealed, the conductive material 320 is deposited in the first trench 312. Generally, the conductive material 320 is deposited on the insulating layer 310 and the surface where the first impurity region 240 is exposed. However, since the maximum reaching angle of the conductive material 320 is at the upper corner 3120 of the insulating layer 310, before the conductive material 320 completely fills the first trench 312, an excessive protrusion 322 is formed at an upper end 314 of each first trench 312. The protrusion 322 is shown as a portion of a layer of conductive material 320 located at the upper end 314 of the first trench 312. Since the deposited amount at the upper end 314 of the first trench 312 is larger, it is thicker than other portions of the layer of conductive material 320. As the protrusion continues to accumulate material, the top opening of the first trench 312 becomes narrower, and the upper end 314 of the first trench 312 may be sealed before the filling from the bottom up is completed, thereby leaving a void in the finished product, as shown in FIG. 3B.

To prevent voids from appearing in the finished product, the deposition step is stopped when a thickness T1 (e.g., the upper or maximum thickness) of one of the protrusions 322 reaches one-quarter of the width W1 of the first trench 312 (the width W1 is shown in FIG. 8 ). The thickness T1 of the protrusions 322 may be monitored using a thickness monitor (not shown) disposed near or within the chamber where the deposition of the conductive material 320 is performed. In some embodiments, the thickness monitor may dynamically monitor the thickness T1 of the protrusions 322 and is configured to stop the deposition of the conductive material 320 if the thickness T1 of one of the protrusions 322 is equal to one-quarter of the width W1 of the first trench 312. In some embodiments, the thickness monitor may use optical monitoring techniques to detect the time evolution of light transmitted, scattered and/or reflected from the layer of conductive material 320 to measure the thickness T1 of the protrusion 322.

10 , a removal step is subsequently performed according to step S610 in FIG. 4 to trim the protrusion 322, and the protrusion 322 is trimmed to reduce its shrinkage at the upper end 314 of the first trench 312. It should be noted that during the removal step, not only the portion of the conductive material 320 at the upper end 314 of the first trench 312 is removed, but also the portion of the conductive material 320 in the lower portion of the first trench 312 is removed during the removal step. In some embodiments, after the removal step is completed, the portion of the conductive material 320 coated on the sidewall 316 of the insulating layer 310, where the sidewall 316 of the insulating layer 310 is joined to the first trench 312, may have a substantially uniform thickness. In addition, the conductive material 320 on the bottom of the first trench 312 may have a relatively flat profile. The removal step is, for example, a wet ashing process, a wet etching process, or a similar process.

After the removal step is completed, the method 600 proceeds to step S612 to determine whether the height H of the conductive material 320 in the first trench 312 is greater than a predetermined height. The predetermined height can be calculated or simulated from a parameterized mathematical model, or can be determined using a trial-and-error test to ensure that the top opening of the first trench 312 is not sealed before the bottom-up filling is completed. In some embodiments, the predetermined height is, for example, equal to half of the height H1 of the first trench 312 (the height H1 is shown in FIG. 8 ). The height H of the conductive material 320 in the first trench 312 can be measured using a thickness monitor disposed near or inside a chamber where the conductive material 320 is deposited. Alternatively, the height H of the conductive material 320 can be measured non-in-situ, outside of the deposition of the conductive material 320.

In step S612, if the height H of the conductive material 320 in the first trench 312 is less than or equal to the predetermined height, the method 600 repeats step S608 to deposit the conductive material 320 and step S610 to remove part of the conductive material 320. During the deposition step, the conductive material 320 is conformally deposited on the insulating layer 310 and in the first trench 312, as shown in FIG. 11, so the thickness T1 of the protrusion 322 and the height H of the conductive material 320 in the first trench 312 are increased. When the thickness T1 of the protrusion 322 is equal to one-fourth of the width W1 of the first trench 312 (the width W1 is shown in FIG. 8), the deposition step is stopped.

Referring to FIG. 12 , during the removal step, the previously deposited conductive material 320 is processed, for example, under isotropic conditions. That is, the removal step removes the conductive material 320 isotropically from the first trench 312, so that the first trench 312 is widened, thereby reducing the aspect ratio of the partially filled first trench 312, which is beneficial for further filling the first trench 312 by subsequent deposition.

In step S612, if the height H of the conductive material 320 in the first trench 312 is greater than the predetermined height, the method 600 proceeds to step S613 to perform the final deposition process to fill the first trench 312 with the conductive material 320, as shown in FIG. 13.

According to step S614, after the last deposition process, a grinding process is performed to remove a portion of the conductive material 320 overflowing the first trench 312, as shown in FIG. 14, thereby forming a plurality of first conductive features 324 in a void-free manner. The grinding process may include a CMP process and/or a wet etching process.

Referring to FIG. 15 , according to step S616 in FIG. 14 , a plurality of storage capacitors 500 are formed on the insulating layer 310 and the first conductive feature 324. The manufacturing of the storage capacitor 500 includes sequentially forming a plurality of storage nodes 510 located on the insulating layer 310 and contacting the first conductive feature 324, depositing a capacitor insulator 520 to cover the insulating layer 310 and the storage nodes 510, and depositing a top electrode 530 on the capacitor insulator 520. In some embodiments, a portion of the top electrode 530 above the second impurity region 250 is removed to form a second conductive feature, as described below.

The storage node 510 has a U-shaped configuration and serves as the lower electrode of the storage capacitor 500. The storage node 510 may be formed of doped polysilicon or metal, such as titanium nitride (TiN) or ruthenium (Ru). The profile of the capacitor insulator 520 may conform to the profile of the storage node 510 and the insulating layer 310. The capacitor insulator 520 may include silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or a high-k material, such as zirconium oxide (Zr ₂ O ₂ ), helium oxide (HfO ₂ ), titanium oxide (TiO ₂ ) or aluminum oxide (Al ₂ O ₂ ). In some embodiments, the capacitor insulator 520 may be formed of a double layer of nitride/oxide film or a triple layer of oxide/nitride/oxide. The top electrode 530 may be a substantially conformal layer and may be formed by a CVD process. The top electrode 530 may be formed of a low resistivity material such as titanium nitride or a combination of titanium nitride, tantalum nitride (TaN), tungsten nitride (WN), ruthenium, iridium (Ir), and platinum (Pt).

Referring to FIG. 16 , according to step S618 in FIG. 4 , an isolation layer 330 is deposited to cover the storage capacitor 500. A dielectric material may be uniformly deposited using a CVD process or a spin-on process to form the isolation layer 330, and the isolation layer 330 may be planarized using, for example, a CMP process to produce an acceptable flat profile. In some embodiments, the isolation layer 330 for protecting the storage capacitor 500 may include a dielectric material, such as TEOS.

Afterwards, a photoresist layer is applied to the entire isolation layer 330 by a spin coating process, and then dried using a soft baking process. The photoresist layer containing a photosensitive material is exposed and developed to form a second pattern mask 420 including at least one window 422, and a portion of the isolation layer 330 above the second impurity region 250 is exposed from the window 422.

17 , according to step S620 in FIG4 , at least one etching process is performed to remove the isolation layer 330, the capacitor insulator 520 and the portion of the insulating layer 310 not protected by the second pattern mask 420. In this way, at least one second trench 340 is formed and a portion of the second impurity region 250 is exposed. An etching process using a variety of etchants selected based on the materials of the insulating layer 310, the isolation layer 330, and the capacitor insulator 520 can be used to sequentially etch the isolation layer 330, the capacitor insulator 520, and the insulating layer 310 until the second impurity region 250 is exposed, thereby forming a second trench 340 passing through the insulating layer 310, the isolation layer 330, and the capacitor insulator 520.

The second trench 340 has a width W2 and a height H2. In addition, the second trench 340 has an aspect ratio of about 5 or more (i.e., height H2 divided by width W2). In some embodiments, the aspect ratio of the second trench 340 is in a range between 6 and 8. It can be observed that the aspect ratio of the first trench 312 (as shown in FIG. 8) is smaller than the aspect ratio of the second trench 340. After forming the second trench 340, the second pattern mask 420 is removed using an ashing process or a wet stripping process.

The method then proceeds to step S622, where a conductive material 320 is deposited in the second trench 340 before a top opening of the second trench 340 is sealed. Specifically, the conductive material is deposited on the isolation layer 330 and in the second trench 340 using low-pressure CVD until a thickness T3 of an overhang 322 at an upper end 342 of the second trench 340 reaches a quarter of a width W2 of the second trench 340 (the width W2 is shown in FIG. 17 ).

Next, the method proceeds to step S624, removing some portions of the previously deposited conductive material 320 from areas where deposition is not required but cannot be avoided, as shown in FIG. 19, thereby preventing the upper end 342 of the second trench 340 from being sealed and avoiding leaving voids in the finished product.

After the removal step is completed, the method 600 proceeds to step S626 to determine whether the number of times the cyclic process is performed is equal to a preset number of times. In step S626, it is determined not only whether the number of times the deposition step is performed is equal to the first preset number of times, but also whether the number of times the removal step is performed is equal to the second preset number of times. A trial and error test can be used to determine the first preset number of times and the second preset number of times to ensure that the top opening of the second trench 340 is not sealed before the bottom-up filling is completed. In step S626, if the deposition step is performed less than the first preset number of times or the removal step is performed less than the second preset number of times, the method 600 repeats the deposition step S622 and the step S624 of removing a portion of the conductive material 320. On the other hand, if the deposition step has been performed for the first preset number of times and the removal step has been performed for the second preset number of times, the method 600 proceeds to step S627 to perform the final deposition process to completely fill the second trench 340 with the conductive material 320, as shown in FIG. 20.

Referring to FIG. 21 , according to step S628 , a planarization process is performed to remove some portions of the conductive material 320 above the isolation layer 330 , thereby forming at least one second conductive feature 326 . The planarization process may include a CMP process and/or a wet etching process.

Next, in step S630, a bit line 350 is formed on the second conductive feature 326 and the isolation layer 330, and the bit line 350 is connected to the second conductive feature 326, thereby completely forming the semiconductor device 10 shown in FIG. 1.

In summary, by a cyclic process including a series of deposition steps and removal steps, before sealing the top openings of the first trench 312 and the second trench 340, the protrusion 322 located at the upper end 314 of the first trench 312 and the upper end 342 of the second trench 340 are trimmed, so that the first conductive feature 324 and the second conductive feature 326 can be manufactured in a void-free manner.

One aspect of the present disclosure provides a method for manufacturing a conductive feature, the method comprising the following steps: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step is performed a number of times equal to a first preset number of times and the removal step is performed a number of times equal to a second preset number of times; and filling the trench with the conductive material after the cyclic process.

One aspect of the present disclosure provides a method for manufacturing a conductive feature, the method comprising the following steps: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until a height of the conductive material in the trench is greater than a predetermined height; and filling the trench with the conductive material after the cyclic process.

One aspect of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising the following steps: forming a transistor in a substrate; depositing an insulating layer on the substrate; forming a first trench penetrating the insulating layer to expose a portion of a first impurity region of the transistor; performing a first cycle process including a first series of a first deposition step and a first removal step to deposit a conductive material in the first trench until a height of the conductive material in the first trench exceeds a predetermined height; filling the first trench with the conductive material after the first cycle process to form a first conductive feature; forming a first conductive feature contacting the first conductive feature; A storage capacitor is formed; an isolation layer is deposited to cover the insulating layer and the storage capacitor; a second trench is formed through the isolation layer and the insulating layer to expose a second impurity region of the transistor; a second cycle process including a second series of a second deposition step and a second removal step is performed to deposit the conductive material in the second trench until the second deposition step is performed a number of times equal to a third preset number of times and the second removal step is performed a number of times equal to a fourth preset number of times; after the second cycle process, the second trench is filled with the conductive material to form a second conductive feature; and a bit line connected to the second conductive feature is formed.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes discussed above may be implemented in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing, material compositions, means, methods and steps described in the specification. A person with ordinary knowledge in the relevant technical field can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10: semiconductor element 100: substrate 110: wafer 120: isolation feature 130: active region 200: access transistor 212: gate insulator 222: word line 230: capping layer 240: first impurity region 250: second impurity region 310: insulating layer 324: first conductive feature 326: second conductive feature 330: isolation layer 350: bit line 500: storage capacitor 510: storage node 520: capacitor insulator 530: top electrode A: region

Claims (15)

A method for manufacturing a conductive feature, comprising: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until the deposition step is performed a number of times equal to a first preset number of times and the removal step is performed a number of times equal to a second preset number of times; and filling the trench with the conductive material after the cyclic process; wherein the removal step removes the conductive material from the trench isotropically. A manufacturing method as described in claim 1, wherein the deposition step of the cyclic process is stopped before an upper end of the trench is sealed. The manufacturing method as described in claim 2, wherein the deposition step of the cyclic process is performed until a thickness of the conductive material deposited on the upper end of the trench is equal to one quarter of a width of the trench. The manufacturing method as described in claim 2, wherein the removal step is to remove at least a portion of the conductive material accumulated on the upper end of the trench. A manufacturing method as described in claim 1, wherein the trench has an aspect ratio substantially greater than or equal to 5. A manufacturing method as described in claim 5, wherein the aspect ratio is in a range between 6 and 8. The manufacturing method as described in claim 1 further includes performing a planarization process to remove the conductive material above the insulating layer after the conductive material completely fills the trench. A method for manufacturing a conductive feature, comprising: depositing an insulating layer on a substrate; forming a trench in the insulating layer; performing a cyclic process including a series of a deposition step and a removal step to deposit a conductive material in the trench until a height of the conductive material in the trench is greater than a predetermined height; and filling the trench with the conductive material after the cyclic process. A manufacturing method as described in claim 8, wherein the deposition step of the cyclic process is stopped before an upper end of the trench is sealed. The manufacturing method as described in claim 9, wherein the deposition step of the cyclic process is performed until a thickness of the conductive material deposited on the upper end of the trench reaches one quarter of a width of the trench. A manufacturing method as described in claim 9, wherein the removing step removes at least a portion of the conductive material located at the upper end of the trench. A manufacturing method as described in claim 8, wherein the predetermined height is equal to half of a height of the groove. A manufacturing method as described in claim 8, wherein the trench has an aspect ratio substantially greater than or equal to 5. A manufacturing method as described in claim 13, wherein the aspect ratio is in a range between 6 and 8. The manufacturing method as described in claim 8 further includes performing a planarization process to remove the conductive material above the insulating layer after the conductive material completely fills the trench.