TWI844800B - Circuit substrate - Google Patents

Abstract

A circuit substrate includes a substrate, a first conductive layer, an insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The insulating layer is disposed on the first conductive layer and the substrate, and has a groove, wherein an orthogonal projection of the groove on the substrate is not overlapped with an orthogonal projection of the first conductive layer on the substrate. The second conductive layer is disposed on the insulating layer, and at least a portion of the second conductive layer is disposed in the groove.

Description

Circuit board

The present invention relates to a circuit substrate.

As component sizes become smaller, the line width design of the traces is also getting smaller (for example, as small as 4μm). However, due to the small attachment area, the adhesion force of the extremely fine traces is small, so they are easily peeled off by external forces during the subsequent water washing or air knife process, resulting in broken traces and affecting the product yield.

The present invention provides a circuit substrate with improved product yield.

An embodiment of the present invention provides a circuit substrate, comprising: a substrate; a first conductive layer located on the substrate; an insulating layer located on the first conductive layer and the substrate and having a groove, wherein the orthographic projection of the groove on the substrate is located outside the orthographic projection of the first conductive layer on the substrate; and a second conductive layer located on the insulating layer, and at least a portion of the second conductive layer is located in the groove.

In one embodiment of the present invention, the above-mentioned groove penetrates the insulating layer.

In one embodiment of the present invention, the above-mentioned groove does not penetrate the insulating layer.

In one embodiment of the present invention, the second conductive layer includes a first conductive segment, and the first conductive segment is completely located in the groove.

In one embodiment of the present invention, the line width of the first conductor segment is less than or equal to 4μm.

In one embodiment of the present invention, the bottom surface of the first conductor segment and the bottom surface of the first conductive layer are located on the same horizontal plane.

In one embodiment of the present invention, the groove width of the above-mentioned groove is less than or equal to 8μm.

In one embodiment of the present invention, the groove length of the above-mentioned groove is less than or equal to 300μm.

In one embodiment of the present invention, the thickness of the above-mentioned insulating layer is between 2,000Å and 10,000Å.

In one embodiment of the present invention, the material of the above-mentioned insulating layer includes inorganic material or organic material.

In one embodiment of the present invention, the second conductive layer includes a second conductive segment, and the first portion of the second conductive segment is located in the groove, and the second portion of the second conductive segment is located outside the groove.

In one embodiment of the present invention, the second conductive layer further includes a third conductive segment, which is separated from the second conductive segment and overlaps the first conductive layer.

In order to make the above features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments with the accompanying drawings.

10, 20, 30: Circuit board

110: Substrate

120: First conductive layer

121, 122, 123, 124: Conductor wire

130: Insulation layer

140, 340: Second conductive layer

141, 142, 341, 342: Conductor

A-A’: section line

B-B’: section line

BF: Buffer layer

D1: First direction

D2: Second direction

G1, G2, G3: Spacing

GV1, GV2, GV3: Grooves

Lg: Groove length

P1: Part 1

P2: Part 2

P3: Part 3

S1, S2, S3: conductor segments

Ti:Thickness

VA:Through hole

Wg: slot width

Ww: Line width

FIG. 1A is a partial top view of a circuit substrate 10 according to an embodiment of the present invention.

Figure 1B is a schematic cross-sectional view taken along the section line A-A’ of Figure 1A.

FIG2 is a schematic cross-sectional view of a circuit substrate 20 according to an embodiment of the present invention.

FIG3A is a partial top view schematic diagram of a circuit substrate 30 according to an embodiment of the present invention.

Figure 3B is a schematic cross-sectional view taken along the section line B-B’ of Figure 3A.

In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Throughout the specification, the same figure reference numerals represent the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element may also exist. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, "electrical connection" or "coupling" may be the presence of other elements between two elements.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first "element", "component", "region", "layer" or "part" discussed below can be referred to as the second element, component, region, layer or part without departing from the teachings of this article.

Additionally, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, the elements described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one figure is flipped, the elements described as being "lower" or "below" the other elements will be oriented as being "above" the other elements. Thus, the exemplary term "lower" or "below" can include both "upper" and "lower" orientations.

Taking into account the measurement in question and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system), "about", "approximately", or "substantially" as used herein includes the stated value and the average value within an acceptable deviation range of the specific value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately", or "substantially" as used herein can select a more acceptable deviation range or standard deviation based on the optical properties, etching properties, or other properties, and can not apply to all properties without a single standard deviation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly so defined herein.

FIG1A is a partial top view schematic diagram of a circuit substrate 10 according to an embodiment of the present invention. FIG1B is a cross-sectional schematic diagram taken along the section line A-A' of FIG1A. Referring to FIG1A to FIG1B, the circuit substrate 10 includes: a substrate 110; a first conductive layer 120, located on the substrate 110; an insulating layer 130, located on the first conductive layer 120 and the substrate 110, and having a groove GV1, wherein the orthographic projection of the groove GV1 on the substrate 110 is located outside the orthographic projection of the first conductive layer 120 on the substrate 110; and a second conductive layer 140, located in the groove GV1.

In the circuit substrate 10 of an embodiment of the present invention, by placing the second conductive layer 140 in the groove GV1, the second conductive layer 140 can be prevented from being peeled off by external force during subsequent processes (such as water washing process and air knife process), thereby improving the product yield.

Below, with reference to FIG. 1A to FIG. 1B , the implementation of each component of the circuit substrate 10 will be further described, but the present invention is not limited thereto.

Please refer to FIG. 1A , the substrate 110 of the circuit substrate 10 can carry film layers such as the first conductive layer 120 , the insulating layer 130 , and the second conductive layer 140 . Here, the possible arrangement of each film layer is only schematically shown, and the detailed layout of each film layer can be determined according to the design requirements.

In this embodiment, the material of the substrate 110 may be glass, but is not limited thereto. In some embodiments, the material of the substrate 110 may also be quartz, organic polymer, or opaque/reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.

In this embodiment, the first conductive layer 120 may include a wire 121 and a wire 122, wherein the wire 121 extends along a first direction D1, and the wire 122 extends along a second direction D2, and the second direction D2 is different from the first direction D1. For example, the wire 121 may be a common electrode, and the wire 122 may be a scanning line. In some embodiments, the first conductive layer 120 may also include a wire 123 and a wire 124, wherein the wire 123 extends parallel to the wire 121, and the wire 124 extends parallel to the wire 122. For example, the wire 123 and the wire 124 may both be a common electrode electrically connected to the wire 121.

Based on the consideration of conductivity, the material of the first conductive layer 120 may include metals, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or alloys of any combination of the above metals. The first conductive layer 120 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

In this embodiment, the insulating layer 130 may cover the first conductive layer 120 and the substrate 110, and the first conductive layer 120 may be sandwiched between the insulating layer 130 and the substrate 110. The groove GV1 of the insulating layer 130 is recessed from the upper surface of the insulating layer 130 into the insulating layer 130, that is, the level of the bottom surface of the groove GV1 is lower than the level of the upper surface of the insulating layer 130, but not lower than the level of the lower surface of the insulating layer 130, and the groove GV1 can be arranged in at least a part of the area where the second conductive layer 140 is to be formed later, so that the level of the lower surface of at least a part of the second conductive layer 140 can be partially lower than the level of the upper surface of the insulating layer 130.

In this embodiment, the groove GV1 may penetrate the insulating layer 130, but is not limited thereto. Specifically, when the groove GV1 penetrates the insulating layer 130, the bottom surface of the groove GV1 may be at the same level as the bottom surface of the insulating layer 130, and the bottom surface of the groove GV1 may be the upper surface of the substrate 110. In order to avoid unnecessary electrical connection between the first conductive layer 120 and the second conductive layer 140 through the groove GV1, the groove GV1 is not disposed at the overlapped first conductive layer 120. In other words, the orthographic projection of the groove GV1 on the substrate 110 may be outside the orthographic projection of the first conductive layer 120 on the substrate 110.

In the present embodiment, the thickness Ti of the insulating layer 130 may be greater than or equal to 2,000Å, such as 2,500Å or 3,500Å, but not limited thereto. In some embodiments, the thickness Ti of the insulating layer 130 may be less than or equal to 10,000Å, such as 8,000Å or 4,000Å, but not limited thereto.

In order to avoid overlapping the first conductive layer 120, in some embodiments, the groove GV1 may have a groove width Wg, and the groove width Wg may be less than or equal to 8μm, such as 7μm or 5μm, but not limited thereto. In some embodiments, the groove GV1 may have a groove length Lg, and the groove length Lg may be less than or equal to 300μm, such as about 250μm or 180μm, but not limited thereto.

In some embodiments, the insulating layer 130 may also have multiple vias VA as needed, and the insulating layer 130 may be provided with vias VA where the second conductive layer 140 needs to be electrically connected to the first conductive layer 120, that is, the second conductive layer 140 may be electrically connected to the first conductive layer 120 through the vias VA.

The material of the insulating layer 130 may include inorganic materials, organic materials or a combination thereof. Examples of inorganic materials include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), or a stack of at least two of the above materials. Examples of organic materials include, but are not limited to, polymer materials such as polyimide resins, epoxy resins or acrylic resins. In this embodiment, the insulating layer 130 may be a single film layer, but is not limited to this. In other embodiments, the insulating layer 130 may also be formed by stacking multiple film layers.

In this embodiment, the second conductive layer 140 may include a wire 141 and a wire 142 extending along the first direction D1, and the wire 141 and the wire 142 may be substantially parallel to each other and separated. In some embodiments, the wire 141 is, for example, a data line, and the wire 142 is, for example, a bridge line. In some embodiments, the wire 142 may overlap the wire 121, and the wire 142 may be electrically connected to the wire 121 through the via VA. Referring to FIG. 1B , the insulating layer 130 may physically contact the wire 121 of the first conductive layer 120 and the wire 142 of the second conductive layer 140. Based on the consideration of conductivity, the material of the second conductive layer 140 may include metals, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), silver (Ag), chromium (Cr), or neodymium (Nd), or alloys of any combination of the above metals. The second conductive layer 140 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

In the present embodiment, the conductive line 141 may be partially located in the groove GV1. For example, the conductive line 141 may include a conductive line segment S1, and the line width Ww of the conductive line segment S1 may be smaller than the groove width Wg of the groove GV1, so that the conductive line segment S1 may be completely located in the groove GV1. Since the groove GV1 penetrates the insulating layer 130, the bottom surface of the conductive line segment S1 may be located at the same horizontal plane as the bottom surface of the conductive line 121 of the first conductive layer 120, so that the minimum distance between the conductive line segment S1 and the substrate 110 is substantially equal to the maximum distance between the first conductive layer 120 and the substrate 110. In some embodiments, the line width Ww of the conductive line segment S1 may be less than or equal to 4 μm, for example, 3 μm or 2 μm. Since the wire segment S1 is located in the groove GV1, when performing treatments such as water washing or air knife treatment, external forces are not easily applied to the groove GV1. Therefore, external forces can be prevented from directly acting on the interface between the wire segment S1 and the underlying film layer (such as the substrate 110), thereby reducing or substantially completely eliminating the situation where the wire segment S1 is peeled off by external forces.

Below, other embodiments of the present invention are described using FIGS. 2 to 3B , and the component numbers and related contents of the embodiments of FIGS. 1A to 1B are used, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the embodiments of FIGS. 1A to 1B , which will not be repeated in the following description.

FIG2 is a schematic cross-sectional view of a circuit substrate 20 according to an embodiment of the present invention. The circuit substrate 20 includes a substrate 110, a first conductive layer 120, an insulating layer 130, and a second conductive layer 140. The second conductive layer 140 includes conductive wires 141 and 142, and the conductive wire segment S1 of the conductive wire 141 is located in the groove GV2 of the insulating layer 130.

Compared with the circuit substrate 10 shown in FIGS. 1A to 1B , the circuit substrate 20 shown in FIG. 2 is different in that the groove GV2 of the insulating layer 130 of the circuit substrate 20 does not penetrate the insulating layer 130 .

In this embodiment, since the groove GV2 does not penetrate the insulating layer 130, the bottom surface of the wire segment S1 and the bottom surface of the first conductive layer 120 are not located at the same horizontal plane, but the horizontal height of the bottom surface of the wire segment S1 is still lower than the horizontal height of the upper surface of the insulating layer 130. In this way, when performing treatments such as water washing or air knife, it is possible to prevent external forces from directly acting on the interface between the wire segment S1 and the underlying film layer (such as the substrate 110), so that the wire segment S1 is not easily peeled off by external forces. In this case, the minimum distance between the wire segment S1 and the substrate 110 can be greater than the maximum distance between the first conductive layer 120 and the substrate 110, as shown in FIG. 2.

FIG3A is a partial top view schematic diagram of a circuit substrate 30 according to an embodiment of the present invention. FIG3B is a cross-sectional schematic diagram taken along the section line B-B' of FIG3A. Please refer to FIG3A and FIG3B simultaneously. The circuit substrate 30 includes a substrate 110, a first conductive layer 120, an insulating layer 130, and a second conductive layer 340. The insulating layer 130 has a groove GV3, and the second conductive layer 340 includes conductive lines 341 and 342.

Compared with the circuit substrate 10 shown in FIG. 1A to FIG. 1B , the circuit substrate 30 shown in FIG. 3A to FIG. 3B is different in that a portion of the conductor segment S2 of the conductor 341 is located in the groove GV3 of the insulating layer 130 , and another portion of the conductor segment S2 is located outside the groove GV3 of the insulating layer 130 .

For example, please refer to FIG. 3B . In this embodiment, the wire segment S2 may include a first portion P1, a second portion P2, and a third portion P3, wherein the second portion P2 and the third portion P3 are located at opposite sides of the first portion P1, respectively, and the first portion P1 is located in the groove GV3, and the second portion P2 and the third portion P3 are located outside the groove GV3, so that the distance G2 between the second portion P2 and the substrate 110 is greater than the distance G1 between the first portion P1 and the substrate 110. Since the bottom surface of the first portion P1 is attached to the groove GV3, after water washing and air knife treatment, it can be observed that the wire 341 is not peeled off by external force.

In some embodiments, the circuit substrate 30 may further include a buffer layer BF, and the buffer layer BF may be located between the substrate 110 and the first conductive layer 120 to isolate the first conductive layer 120 from the substrate 110.

In this embodiment, the wire 342 of the second conductive layer 340 may include a wire segment S3 overlapping the first conductive layer 120, and the distance G3 between the wire segment S3 and the substrate 110 may be greater than the distance G2 between the second portion P2 of the wire segment S2 and the substrate 110. In some embodiments, the wire segment S3 may also be electrically connected to the first conductive layer 120 through a via VA.

In summary, the circuit substrate of the present invention can significantly reduce or substantially completely eliminate the situation where the wire is stripped or broken by external force during subsequent processing (such as water washing or air knife processing) by placing the wire part with extremely fine wire width in the groove, thereby improving the product yield of the circuit substrate.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

10: Circuit board

110: Substrate

120: First conductive layer

121, 122, 123, 124: Conductor wire

130: Insulation layer

140: Second conductive layer

141, 142: Conductor

A-A’: section line

D1: First direction

D2: Second direction

GV1: Groove

Lg: Groove length

S1: conductor segment

VA:Through hole

Wg: slot width

Claims (11)

A circuit substrate comprises: a substrate; a first conductive layer located on the substrate; an insulating layer located on the first conductive layer and the substrate and having a groove, wherein the orthographic projection of the groove on the substrate is outside the orthographic projection of the first conductive layer on the substrate; and a second conductive layer located on the insulating layer, and at least a portion of the second conductive layer is located in the groove, wherein the insulating layer physically contacts the first conductive layer and the second conductive layer, the second conductive layer comprises a first conductive segment, and the first conductive segment is completely located in the groove, and the minimum distance between the first conductive segment and the substrate is greater than or equal to the maximum distance between the first conductive layer and the substrate. A circuit substrate as described in claim 1, wherein the groove penetrates the insulating layer. A circuit substrate as described in claim 1, wherein the groove does not penetrate the insulating layer. A circuit substrate as described in claim 1, wherein the line width of the first conductor segment is less than or equal to 4μm. A circuit substrate as described in claim 1, wherein the bottom surface of the first conductor segment and the bottom surface of the first conductive layer are located on the same horizontal plane. A circuit substrate as described in claim 1, wherein the groove width is less than or equal to 8μm. A circuit substrate as described in claim 1, wherein the groove length of the groove is less than or equal to 300μm. A circuit substrate as described in claim 1, wherein the thickness of the insulating layer is between 2,000Å and 10,000Å. The circuit substrate as described in claim 1, wherein the material of the insulating layer comprises an inorganic material or an organic material. A circuit substrate as described in claim 1, wherein the second conductive layer includes a second conductor segment, and a first portion of the second conductor segment is located within the groove, and a second portion of the second conductor segment is located outside the groove. A circuit substrate as described in claim 10, wherein the second conductive layer further includes a third conductive segment, the third conductive segment is separated from the second conductive segment, and the third conductive segment overlaps the first conductive layer.