TWI843723B - Methods and apparatus for acoustic noise reduction in a dc-dc converter using variable frequency modulation - Google Patents

Abstract

The present embodiments relate generally to switched-capacitor (SC) based DC-DC converters, and more particularly to modulation schemes of cap dividers that include ceramic capacitors such as MLCCs. According to certain general aspects, the present embodiments increase the switching frequency at light loads using variable frequency modulation schemes to reduce the voltage difference across the MLCCs. In these and other embodiments, the acoustic noise generated from the MLCCs can be reduced while maintaining excellent light load efficiency. According to certain aspects, this can be achieved with minimal impact on system performance, cost and size.

Description

Method and apparatus for acoustic noise reduction in DC-DC converters using variable frequency modulation

This patent application claims priority to U.S. Provisional Patent Application No. 62/656,650 filed on April 12, 2018, the contents of which are incorporated herein by reference in their entirety.

The present embodiments generally relate to switched capacitor (SC) based DC-DC converters, and more particularly to modulation schemes employing a cap divider with a ladder topology and including ceramic capacitors.

A DC-DC converter receives an input voltage from an input source (e.g., mains power, battery, etc.) and uses that voltage to provide an output voltage to a load (e.g., computer, IoT device, etc.). Traditional DC-DC converters often use a topology that includes an inductor and a power switch such as a power MOSFET. Such inductor-based topologies are problematic and/or they present certain design considerations that are often not easily addressed.

An alternative to inductor-based topologies is switched capacitor (SC)-based topologies. SC-based DC-DC converters include flying capacitors that are charged and discharged using switches driven by pulse width modulation (PWM) or pulse frequency modulation (PFM) signals to transfer energy from the input voltage to the output without the use of an inductor. While SC-based DC-DC converters can therefore offer certain benefits over inductor-based topologies, there are still some opportunities for improvement.

The present embodiments generally relate to switched capacitor (SC) based DC-DC converters and more particularly to modulation schemes for cap dividers including ceramic capacitors such as MLCCs. According to certain general aspects, the present embodiments use a variable frequency modulation scheme to increase the switching frequency at light loads to reduce the voltage difference across the MLCCs. In these and other embodiments, acoustic noise generated from the MLCCs can be reduced while maintaining excellent light load efficiency. According to certain aspects, this can be achieved with minimal impact on system performance, cost, and size.

100:SC converter

102: Gate driver

104-1: Switch

104-2: Switch

104-3: Switch

104-4: Switch

106:Cfly

202: Curve

204:Curve

206:Curve

208:Curve

302: Comparator

304: Sensing circuit

306: Sensing circuit

308:Logic

310: Resistor

312:Logic

402:Curve

404:Curve

406: Range

408: Range

410: Load range

412:Curve

414:Curve

416: Range

418: Range

420: Range

500: Modulator

502:Amplifier

504:Amplifier

506: Top window level

508: Bottom window level

510:Amplifier

512: Gate Logic

514: Comparator

516: Comparator

522:Logic

600:Converter

602: Modulator

604: Gate Logic/Driver

606:Logic

608: View data table

610: Sensing resistor

700:Converter

702: Modulator

704: Gate Logic/Driver

706: Current information conversion logic

708: View data table

710: Integrated power MOSFET

712:SENSEFET

800: Modulator

802: Current flow measuring resistor

804: Low voltage current sensing amplifier

806: Sense voltage

808: Voltage-controlled oscillator

810:JK trigger

812:Signal

814:Driver

820: Frequency modulation block

S1002: Step

S1004: Step

S1006: Step

These and other aspects and features of the present invention will be apparent to those skilled in the art by reading the following description of specific embodiments in conjunction with the accompanying drawings, wherein: FIGS. 1A and 1B are block diagrams showing an exemplary hat divider having a trapezoidal topology; FIGS. 2A and 2B are diagrams showing various aspects of an exemplary acoustic noise reduction technique; FIG. 3 is a block diagram showing an exemplary modulator for implementing acoustic noise reduction according to the present embodiment; FIGS. 4A and 4B are diagrams showing an exemplary frequency modulation method that can be implemented in conjunction with the modulator shown in FIG. 3; FIG. 5 is a diagram showing an exemplary method for implementing an acoustic noise reduction technique according to the present embodiment; FIG. 6 is a block diagram showing another exemplary modulator for achieving acoustic noise reduction according to the present embodiment; FIG. 7 is a block diagram showing another exemplary modulator for achieving acoustic noise reduction according to the present embodiment; FIG. 8 is a block diagram showing another exemplary modulator for achieving acoustic noise reduction according to the present embodiment; FIGS. 9A and 9B are diagrams showing exemplary aspects of the benefits achieved by the present embodiment; and FIG. 10 is a flow chart showing an exemplary acoustic noise reduction method according to the present embodiment.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the embodiments to enable those skilled in the art to practice the embodiments and alternatives that are apparent to those skilled in the art. It is worth noting that the following drawings and examples are not meant to limit the scope of the present embodiment to a single embodiment, and other embodiments are also possible by interchanging some or all of the described or illustrated elements. In addition, where certain elements of the present embodiment can be partially or completely implemented using known components, only those portions of the known components necessary for understanding the present embodiment will be described, and detailed descriptions of other portions of the known components will be omitted to avoid obscuring the present embodiment. It will be apparent to those skilled in the art that embodiments described as being implemented in software should not be limited thereto but may include embodiments implemented in hardware, or a combination of software and hardware, and vice versa, unless otherwise stated herein. In this specification, embodiments showing a single component should not be considered limiting; rather, unless otherwise expressly stated herein, the present case is intended to cover other embodiments including multiple identical components, and vice versa. Furthermore, unless expressly stated otherwise, applicants do not intend to give uncommon or special meanings to any term in the specification or claims. Furthermore, the present embodiments include current and future known equivalents of known components mentioned herein by way of illustration.

According to certain aspects, the present embodiments are based on a modified switched capacitor (SC) converter topology, which typically does not include an inductor. More specifically, the present embodiments relate to a modulation scheme for an SC-based converter that includes ceramic capacitors such as MLCCs. According to certain general aspects, the present embodiments increase the switching frequency of the SC-based converter at light loads using a variable frequency modulation scheme to reduce the voltage difference across the MLCCs. In these and other embodiments, acoustic noise generated from the MLCCs can be reduced while maintaining excellent light load efficiency. According to certain aspects, this can be achieved with minimal impact on system performance, cost, and size.

FIG. 1A is a block diagram showing an exemplary cap divider topology for an SC converter 100. As shown in this example, an input voltage Vin is provided by a 2S battery. An exemplary Vout is shown as being equivalent to a 1S battery (i.e., Vout=Vin/2). A gate driver 102 drives four switches (e.g., NFETs) 104 coupled between Vin, Vout, and ground to charge and discharge a flying capacitor Cfly 106 to transfer energy from the input to the output. As further shown in FIG. 1A, a gate drive signal is sent to the gate driver 102 to drive the NFET 104, as will be described in more detail below. The gate drive signal (e.g., from a modulator, not shown) has a switching frequency Fs, a switching period Ts, and a duty cycle D, which in this case is ideally about 50% due to the ratio of the input voltage Vin and the output voltage Vout in the illustrated embodiment. However, for this and other embodiments, other duty cycles may also achieve certain performance indicators, such as efficiency, ripple, or various types of noise. In addition, although Vin is shown as being provided by a battery in this example, other types of power sources are possible, such as power from an adapter, a power pack, or other power source that provides sufficient DC voltage. Vout can be provided to any type of load, such as CPU voltage regulator, electronic load, battery, portable device, IoT device, etc.

As will be appreciated by those skilled in the art, the switched capacitor converter 100 shown in FIG. 1A employs a trapezoidal topology that can be easily extended to other embodiments where other Vout-Vin ratios are required. For example, as shown in FIG. 1B , by adding two or more switched capacitors (i.e., flying capacitors and associated switches), the circuit in FIG. 1A can be adapted to provide a ratio of Vout=Vin/3 and/or a ratio of Vout=2Vin/3. However, for the sake of clarity of the invention, further details thereof will be omitted here. It should also be noted that the present embodiment is not limited to a trapezoidal topology, other topologies are possible, such as a series-parallel row topology, a multiplication topology, etc., and a person skilled in the art will be able to understand how to implement the present embodiment in such other topologies after being taught by this example.

In addition, the applicant recognizes that multi-layer ceramic capacitors (MLCCs) are widely used with topological structures such as those shown in FIGS. 1A and 1B . More specifically, in conjunction with the example of FIG. 1A , MLCCs are used to implement Cfly 106 and any or all of the output and decoupling capacitors C1 and C2 . Large capacitance with a small size (low profile). MLCCs are popular because they have good parasitic properties, such as very low effective series resistance and inductance, they present low impedance at higher frequencies, they have high reliability over a long period of time, and they are very low cost. Therefore, it is highly desirable to use MLCCs, and there are many disadvantages to using other types of capacitors.

However, the applicant further recognized that when an AC voltage (such as the AC gate drive voltage shown in FIG. 1A ) is applied to the MLCC, the dielectric will experience expansion and contraction due to the electric field. If the voltage fluctuation causes deformation in the frequency range of 20 Hz to 20 kHz, people can hear it and thus produce acoustic noise. Various methods have been tried to reduce acoustic noise, such as adding metal terminals or inserting substrates to suppress the transmission of vibrations, using thicker PCBs to allow sound frequencies to shift due to weight changes, placing components at the edge of the PCB to reduce the sound pressure level, placing capacitors preferably of small size on each side of the PCB to eliminate vibrations, and reducing the voltage amplitude changes at both ends of the capacitor. However, these attempts may increase cost, complexity, or have other undesirable effects.

Therefore, according to certain aspects, although the duty cycle D can be kept substantially constant based on the desired input-output voltage conversion ratio n (e.g., n=1/2), the present embodiment is intended to provide a variable frequency modulation scheme for the switching frequency Fs to reduce or eliminate the acoustic noise caused by the expansion and contraction of the MLCC dielectric.

One possible solution is to simply apply an audio filter that forces the modulator to partially/completely avoid the switching frequency Fs within the audible frequency range. For example, FIG. 2A illustrates this solution in the 2:1 cap divider circuit shown in FIG. 1A . In FIG. 2A , curve 202 represents the conventional operation of the SC converter 100, where the modulator adjusts the switching frequency Fs based on the load condition. It can be seen that based on the load condition requiring Iout to be between approximately 0.001 A and 5 A, the switching frequency Fs varies from approximately 100 Hz to approximately 500 kHz in a substantially uniform manner, which includes the audible range from 20 Hz to approximately 20 kHz (as shown in curve 202 , a switching frequency of 20 kHz in this example corresponds to a load of approximately 0.2 A). Therefore, during typical operation of the converter 100, there will be audible noise from the MLCC at light loads below about 0.2 A.

Meanwhile, curve 204 in FIG. 2A represents the operation of the SC converter 100 in which the modulator includes an audio filter. As shown, in the operation of the converter 100 under heavier loads above about 0.2 A, curve 204 is the same as curve 202. However, at lighter loads, curve 204 differs from curve 202 by maintaining a constant switching frequency Fs of about 20 kHz. Even though the lighter load condition would allow a lower switching frequency to be used, the converter 100 is forced to operate at a switching frequency above the audible range.

Although this approach successfully eliminates acoustic noise caused by the expansion and contraction of the dielectric in the MLCC during operation of the converter 100, it has certain disadvantages. One disadvantage of this approach is illustrated by the diagram of FIG. 2B. In this figure, curve 206 represents the conventional operation of the converter 100, and curve 208 represents the operation of the converter 100 with the audio filter as described in conjunction with FIG. 2A. As can be seen from curve 208, as compared to curve 206, with the audio filter engaged in operation at a light load of less than about 0.2 A, the operating efficiency of the converter 100 with the audio filter is much lower than the efficiency of the converter 100 operated in a conventional manner.

Therefore, according to certain other aspects, embodiments of the present invention provide an acoustic noise reduction technique that does not cause substantial disadvantages of the schemes described above in conjunction with FIGS. 2A and 2B .

A scheme according to the present embodiment can be implemented by an exemplary modulator 300 shown in FIG3. The modulator 300 can be used to generate a gate drive signal for a converter such as the converter 100 shown in FIG1, which is provided to the gate driver 102 and used to drive the switching transistor 104. Generally, in this example, the generation of the gate drive signal is regulated based on the output of the comparator 302. This scheme requires two sense circuits 304, 306, one for Vin and one for Vout, and a comparator 302. Variable frequency modulation is performed by logic 308 based on the results of comparing Vout to the Vin*n-Vin threshold (where n=1/2 for the exemplary converter 100 shown in FIG. 1A).

In general operation, modulator 300 will cause the gate drive signal output by converter 100 to have a substantially constant duty cycle (e.g., D=1/2 in the exemplary converter 100), but with a variable switching frequency Fs based on load conditions, and the switching frequency Fs can therefore generally follow the operation of curve 202 shown in FIG2A. However, as further shown in FIG3, modulator 300 also includes variable threshold logic 312. Logic 312 monitors the switching frequency Fs and will adjust the Vin threshold in a manner that reduces acoustic noise caused by the expansion and contraction of the dielectric in the MLCC. As shown in the example of FIG. 3 , this is achieved by logic 312 causing the resistance provided by resistor 310 to change, thereby causing the Vin threshold to change. This change in the Vin threshold will further cause the switching frequency Fs of the gate drive signal output by gate logic 308 to change. In one exemplary embodiment, resistor 310 is implemented by a variable resistor or an adjustable DAC. In other exemplary embodiments, resistor 310 is implemented by multi-value resistors connected in parallel, where a switch selectively connects one resistor at a time.

An example of how this may be implemented in a 2:1 crossover converter such as converter 100 in FIG1A is illustrated in the graph of FIG4A. In FIG4A, curve 402 represents the operation of modulator 300 without logic 312 and curve 404 represents the operation of modulator 300 with logic 312. By comparing curves 402 and 404, it can be seen that the operation of modulator 300 at higher loads (e.g., greater than about 0.5 A) is the same with or without logic 312. However, with logic 312, the switching frequency is monitored and when it is below about 30kHz, logic 312 causes the Vin threshold to be reduced (e.g., by changing the value of resistor 310). This causes the switching frequency to be increased in lighter loads compared to the higher Vin threshold when operating without logic 312. Acoustic noise in lighter loads is thus reduced. In one non-limiting example of FIG. 4A (e.g., in conjunction with a 2S:1S SC converter), the Vin threshold is reduced from 60mV at higher loads to 30mV at lower loads. When the switching frequency is above 60kHz or below 30kHz, logic 312 can achieve this by selectively connecting one of two different resistors in the path of resistor 310 in Figure 3. It should be noted that logic 312 can impose some hysteresis on the threshold frequency to prevent jumping back and forth between resistors at frequencies close to 60kHz or 30kHz. As can be further seen, the change in the Vin threshold causes the range 406 of operating loads where acoustic noise occurs without logic 312 to be reduced to the range 408 using logic 312. In other words, the operation of logic 312 results in an expansion of the load range 410 for canceling acoustic noise.

Another example of how this may be implemented in a 2:1 crossover converter such as converter 100 in FIG1A is illustrated in the graph of FIG4B. In FIG4B, curve 412 represents the operation of modulator 300 without logic 312 and curve 414 represents the operation of modulator 300 with logic 312. By comparing curves 412 and 414, it can be seen that the operation of modulator 300 at higher loads (e.g., greater than about 0.5 A) is the same with or without logic 312. However, with logic 312, the switching frequency is monitored and when it is below about 20kHz, logic 312 causes the Vin threshold to be reduced (e.g., by changing the value of resistor 310). This causes the switching frequency to be increased at lighter loads compared to the higher Vin threshold when operating without logic 312. In one non-limiting example of FIG. 4B (e.g., in conjunction with a 2S:1S SC converter), the Vin threshold is gradually reduced from 60mV at higher loads to 30mV at lower loads. Logic 312 can achieve this by variably adjusting the resistance value in the path of resistor 310 in FIG. 3 when the switching frequency is above or below 20kHz and the Vin threshold is at either end of 30mV or 60mV, respectively. It should be noted that load current information can also or alternatively be sensed to achieve hysteresis and regulation (e.g., approximately 0.2A and 0.4A in this example). As can be further seen, the change in Vin threshold causes the range 416 of operating loads where acoustic noise occurs without logic 312 to be reduced to a range 418 with logic 312. In other words, the operation of logic 312 results in an expansion of the load range 410 for canceling acoustic noise.

An example of a hysteresis window modulator 500 is shown in FIG5 , which is an alternative to modulator 300 , but can achieve similar results as shown in FIGS. 4A and 4B . In this scheme, as shown in FIG5 , the comparator output of the hysteresis window based on the flying cap Cfly voltage is used to adjust the generation of the gate drive signal. Two operational amplifiers 502 , 504 are used to provide an upper window level 506 and a lower window level 508 based on the input voltage, respectively. The voltage difference on the flying cap voltage is measured by amplifier 510. Based on comparing the flying cap voltage with the hysteresis window using comparators 514 , 516 , variable frequency modulation is performed by gate logic 512 .

As further shown in FIG5 , the modulator 500 according to an embodiment also includes variable window voltage logic 522. Without logic 522, the modulator 500 can provide variable switching frequency modulation, such as shown by curve 202 in FIG2A . However, similar to logic 312 in modulator 300, logic 522 monitors the switching frequency of the gate drive signal and uses the monitored frequency to adjust the upper and lower window voltages (e.g., by adjusting the resistor network around amplifiers 502, 504) to obtain the results shown in FIG4A . The modulator 500 can also or alternatively monitor the load current to achieve hysteresis and stability as shown in FIG4B . In this example (e.g. combined with a 2S:1S SC converter), based on the monitored switching frequency Fs, a smaller hysteresis window (e.g. 60mV) is used at light loads, and a larger hysteresis window (e.g. 120mV) is used at higher loads.

The above exemplary embodiments modulate the switching frequency by directly monitoring when the switching frequency approaches the acoustic range and adjusting the Vin threshold or hysteresis voltage window in response. However, other schemes are possible according to further embodiments.

6 , a modulator 602 for an SC-based converter 600 includes a gate logic/driver 604 and a current information conversion logic 606. As further shown, the current information conversion logic 606 uses a lookup data table 608 to convert the current sensed from a sense resistor 610 into a switching frequency, a duty cycle, and any pulse generation or pulse jump parameters that may be implemented by the gate logic/driver 604. For example, by looking up the data table 608 to store data corresponding to a predetermined current-frequency curve, the current information conversion logic 606 can select and/or determine the appropriate switching frequency from these data based on the sensed current information. Note that the sense resistor 610 can be placed on the input side or other appropriate locations, or replaced by other current sensing techniques.

For example, depending on efficiency/ripple targets, current information can be mapped to various switching frequency options by consulting a data table 608. For example, table 608 can store data corresponding to either or both of curves 404 and 414 in Figures 4A and 4B. Logic 606 can be configured to select among the curves within table 608 (e.g., between curves 404 or 414), such as using pin settings, input signals, or other such mechanisms and algorithms (not shown) at any given time or under certain operating conditions.

FIG7 is a block diagram of another exemplary frequency modulation scheme according to the present embodiment.

As shown in this example, a modulator 702 for an SC-based converter 700 includes a gate logic/driver 704 and a current information conversion logic 706, as well as an integrated power MOSFET 710 and an integrated SENSEFET 712. As further shown, the current information conversion logic 706 uses a lookup data table 708 to convert the current sensed from the SENSEFET 712 into a switching frequency, a duty cycle, and any pulse generation or pulse jump parameters that may be implemented by the gate logic/driver 704. Similar to the previous example, the lookup table 708 stores data corresponding to predetermined current-frequency curves (e.g., data corresponding to curves 404 and 414 in Figures 4A and 4B), and the current information conversion logic 706 can select and/or determine an appropriate switching frequency from the data based on the sensed current information, which will be described in more detail below.

FIG8 is a block diagram of another exemplary frequency modulation scheme according to the present embodiment.

Unlike other examples, this scheme does not include looking up a data table. Instead, in modulator 800, current is used directly to generate a switching frequency. Current sensing is performed using a current sensing resistor 802 and a low voltage current sensing amplifier 804 (e.g., an operational amplifier), which shifts the level to generate a sense voltage 806. The sense voltage 806 is fed to a frequency modulation block 820, which generates an output voltage to a voltage controlled oscillator (VCO) 808. The frequency modulation block 820 includes logic for determining whether the load condition warrants adjusting the switching frequency as described above in conjunction with Figures 4A and 4B, and generates an output voltage to achieve a reduced acoustic noise switching frequency.

VCO 808 generates a fixed duty cycle clock signal output (e.g., 50% duty cycle) whose frequency depends on the voltage output from block 820. This clock signal is provided as a clock input to JK trigger 810 to generate a gate drive signal Q and a complementary gate drive signal QN at its Q and QN output terminals, respectively. These signals 812 are provided to driver 814, which drives (e.g., using a monostable trigger) the gate of the appropriate switch at the switching frequency determined by block 820.

9A and 9B are diagrams showing exemplary operating states of the present embodiment. More specifically, the various switching frequencies shown in FIG. 9A are juxtaposed with the Iout curves 402, 404, and 414 shown in FIGS. 4A and 4B, and FIG. 9B provides corresponding efficiency curves for each of these examples. As can be seen in FIG. 9A, the efficiency of the acoustic noise reduction scheme according to the present embodiment is slightly lower at light load than the efficiency without such a scheme. However, the reduction is only about 1-2% at most, which is a favorable tradeoff for the reduced acoustic noise achieved. Moreover, the reduction in efficiency is much less than that of conventional noise reduction techniques, such as those described in conjunction with FIGS. 2A and 2B.

FIG10 is a flow chart of an exemplary gate signal modulation method according to an embodiment.

As shown in this example, in step S1002, an initial gate drive signal is generated with an appropriate switching frequency, duty cycle, and any other pulse generation or pulse jump parameters. The switching frequency of the gate drive signal can be, for example, a predetermined frequency, but can be adjusted if necessary. As previously mentioned, the duty cycle can be fixed according to the required input-output voltage conversion ratio, but other duty cycles are possible. For example, if the ratio is Vout=Vin/2, the duty cycle can be set to 50%, 45%, 40%, etc.

In step S1004, a parameter of the load condition is sensed. For example, the parameter may be the switching frequency of the gate drive signal, as described above in conjunction with FIGS. 3 and 5. In other embodiments, such as those described in conjunction with FIGS. 6-8, the parameter may be the current drawn by the load. This may be sensed in a variety of ways as described above, such as using a sense resistor at or near an output node or input node, a SENSEFET near a power transistor, etc.

In response to the sensed parameter (e.g., current), in step S1006, the gate signal is modulated to reduce acoustic noise caused by the MLCC when necessary. In some exemplary embodiments, the Vin threshold or hysteresis window voltage is adjusted. In other embodiments, a data table lookup is used to determine the appropriate switching frequency for a given current (i.e., load condition). In other embodiments that do not include a data table lookup, a direct current-frequency conversion operation can be performed, for example, using a VCO.

The above steps can be repeated continuously until no further modulation is required.

Although the embodiments of the present invention have been described in detail with reference to preferred embodiments thereof, it will be apparent to those skilled in the art that changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. The appended claims are intended to cover such changes and modifications.

202: Curve

204:Curve

Claims (14)

A device for converting an input voltage at an input terminal to an output voltage at an output terminal, the device comprising: a capacitor, wherein the capacitor is configured such that charging and discharging of the capacitor transfers energy from the input terminal to the output terminal, wherein the capacitor is a multi-layer ceramic capacitor; a plurality of switches, the switches being configured to control charging and discharging of the capacitor; and a controller, the controller controlling a switching frequency of the switches based on a desired acoustic noise reduction level and in accordance with a sensed parameter. A device as claimed in claim 1, wherein the acoustic noise is caused by the expansion and contraction of the capacitor according to the switching frequency. The device of claim 1, wherein the sensed parameter is a current at the output terminal, the device further comprising a lookup table coupled to the controller, wherein the controller is configured to set the switching frequency based on the current using one or more entries in the lookup table. A device as described in claim 1, wherein the controller includes a voltage threshold modulator, the voltage threshold modulator uses a voltage threshold to adjust the switching frequency, and the voltage threshold is adjusted according to the sensed parameter. The device as claimed in claim 1, wherein the controller includes a hysteresis modulator, the hysteresis modulator uses a window voltage to adjust the switching frequency, and the window voltage is adjusted according to the sensed parameter. The device of claim 1, wherein the switches include FETs, wherein the controller is coupled to provide a gate drive signal to a gate of the FET, the gate drive signal having the switching frequency. A device as described in claim 6, wherein the sensing parameter is a frequency of the gate drive signal. The device as described in claim 1 further includes a decoupling capacitor for charging the capacitor using the input voltage, wherein the decoupling capacitor includes a multi-layer ceramic capacitor. The device as described in claim 1 further includes an output capacitor for storing the output voltage obtained by discharging the capacitor, wherein the output capacitor includes a multi-layer ceramic capacitor. A method for converting an input voltage at an input terminal to an output voltage at an output terminal, the method comprising the steps of: charging and discharging a capacitor to transfer energy from the input terminal to the output terminal, wherein the capacitor is a multi-layer ceramic capacitor; operating a plurality of switches to control the charging and discharging of the capacitor; and controlling a switching frequency of the switches by a controller based on a desired acoustic noise reduction level and according to a sensed parameter. The method of claim 10, wherein the sensed parameter is a current at the output terminal, the method further comprising setting the switching frequency based on the current using one or more entries in a lookup table by the controller. A method as described in claim 10, wherein the control includes using a voltage threshold to adjust the switching frequency, and the voltage threshold is adjusted according to the sensed parameter. A method as described in claim 10, wherein the control includes adjusting the switching frequency using a hysteresis window voltage, the hysteresis window voltage being adjusted based on the sensed parameter. The method as claimed in claim 10, wherein the switches include FETs, and the method further includes providing a gate drive signal to a gate of the FET by the controller, wherein the sensed parameter is a frequency of the gate drive signal.