TWI841490B - Method of fabricating memory device - Google Patents

Abstract

A method of manufacturing a memory device at least includes the following steps. A first interconnect and a first dielectric layer are formed on a substrate. A first chemical mechanical polishing process is performed on the first dielectric layer. A stack structure is formed over the first dielectric layer and a staircase structure is formed in the stack structure. A second dielectric layer is formed on the substrate to cover the stack structure and the staircase structure. A second chemical mechanical polishing process is performed on the second dielectric layer. A depth of second grooves of a second polishing pad used in the second chemical mechanical polishing process is smaller than a depth of first grooves of a first polishing pad used in the first chemical mechanical polishing process. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Description

Method for manufacturing memory element

The present invention relates to a method for manufacturing an integrated circuit, and in particular to a method for manufacturing a memory element.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure. Therefore, they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory. For example, during the chemical mechanical polishing process of the dielectric layer on the step structure, the groove plugging of the polishing pad often occurs, causing the process to be interrupted or even resulting in a reduction in the life of the polishing pad.

The present invention provides a method for manufacturing a memory device, which can reduce the clogging of the grooves of the polishing pad, so as to extend the service life and service life of the polishing pad.

According to an embodiment of the present invention, a method for manufacturing a memory element includes at least the following steps. A first internal connection is formed on a substrate. A first dielectric layer is formed on the first internal connection. A first planarization process is performed by a first chemical mechanical polishing process to planarize the first dielectric layer. A stacking structure is formed above the first dielectric layer. A step structure is formed in the stacking structure. A second dielectric layer is formed on the substrate to cover the stacking structure and the step structure. A second planarization process is performed by a second chemical mechanical polishing process to planarize the second dielectric layer. The depth of the second groove of the second polishing pad used in the second chemical mechanical polishing process is lower than the depth of the first groove of the first polishing pad used in the first chemical mechanical polishing process. The porosity of the second polishing pad is lower than the porosity of the first polishing pad. The hardness of the second polishing pad is higher than that of the first polishing pad. The roughness of the second polishing pad is lower than that of the first polishing pad.

Based on the above, the manufacturing method of the memory device of the embodiment of the present invention adopts a polishing pad with shallow grooves to extend the life of the polishing pad.

The present invention provides a chemical mechanical polishing process that can enable the polishing pad to maintain sufficient groove depth after long-term use, so that the chemical mechanical polishing process can maintain a relatively high removal rate.

The chemical mechanical polishing process of the present invention can be used for planarizing a dielectric layer with large fluctuations, such as a dielectric layer on a step structure of a 3D flash memory. However, the present invention is not limited thereto.

FIG. 1A and FIG. 1B are cross-sectional schematic diagrams of an intermediate stage of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. FIG. 2A and FIG. 2B are top views and partial perspective views of a polishing pad used in a chemical mechanical polishing process according to an embodiment of the present invention. FIG. 3A and FIG. 3B are top views of a dresser used in a chemical mechanical polishing process according to an embodiment of the present invention.

1A , a wafer 200W may include a substrate 200 and a stacking structure SK0. The substrate 200 may be a semiconductor substrate, such as a silicon-containing substrate. The stacking structure SK0 may include a plurality of insulating layers 202 and a plurality of spacer layers 104 stacked alternately. The material of the insulating layer 202 includes silicon oxide, and the material of the spacer layer 204 includes silicon nitride. The stacking structure SK0 has been formed into a plurality of step structures SC0 by a patterning process. In addition, a dielectric layer 203 has been formed on the stacking structure SK0. Since the step structure SC0 has a considerable number of steps, such as more than 100 steps, the height difference thereof is quite large. Therefore, the topology of the surface of the dielectric layer 203 also has quite dramatic ups and downs.

Referring to FIG. 1B and FIG. 2A , the dielectric layer 203 is planarized to remove excess dielectric layer 203. To planarize the dielectric layer 203, the embodiment of the present invention is performed using a chemical mechanical polishing process that is different from other stages. Referring to FIG. 2A and FIG. 2B , the chemical mechanical polishing process of the embodiment of the present invention uses a polishing pad 300 having a higher hardness (i.e., more solid) and a lower roughness. The depth d1 of the groove 302 of the polishing pad 300 is shallow, for example, less than 30 mil. The polishing pad 300 also has a lower porosity, for example, 0 to 30%.

2A, 3A and 3B, the dresser 400 used in the chemical mechanical polishing process may have a circular or donut-shaped profile, as shown in FIG. 3A and FIG. 3B, respectively. The dresser 400 has a high removal rate, such as 300-600 μm/hour. The slurry used in the chemical mechanical polishing process has a low concentration of abrasive particles, such as a concentration of less than 15%. The abrasive particles include silicon oxide, aluminum oxide, barium oxide or a combination thereof.

Figure 4 shows the groove depth of the polishing pad used in the chemical mechanical polishing process according to the present invention after long-time (9 hours) polishing. Figure 5 shows the removal rate of the dielectric layer used in the chemical mechanical polishing process according to an embodiment of the present invention at various radial positions of the wafer as a function of polishing time.

The results in Figure 4 show that after a long period of polishing (9 hours), the grooves on the polishing pad still have sufficient depth.

The results in Figure 5 show that after a long polishing time (9 hours), the CMP process still has a high removal rate for the dielectric layer at various radial locations on the wafer.

The chemical mechanical polishing process of the embodiment of the present invention can efficiently remove the dielectric layer through the design of the polishing pad, the coordination of the material and concentration of the abrasive particles in the slurry, the selection of the shape profile of the dresser, and the regulation of the removal rate. It can also enable the polishing pad to maintain a sufficient groove depth after long-term use, so that the chemical mechanical polishing process can maintain a relatively high removal rate.

Compared to the polishing pads used in other chemical mechanical polishing processes, the chemical mechanical polishing process of the embodiment of the present invention uses a polishing pad with higher hardness, lower roughness, shallower groove depth and lower porosity, a slurry with lower abrasive concentration and a dresser with higher removal rate. This is described in detail below with reference to FIGS. 6A to 6J. FIGS. 6A to 6J are cross-sectional schematic diagrams of a method for manufacturing a three-dimensional memory element according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 10 is provided. The substrate 10 includes a first region R1, a second region R2, and a third region R3. The first region R1, the second region R2, and the third region R3 may also be referred to as a memory array region R1, a step region R2, and a peripheral region R3. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The first region R1 is a schematic cross-sectional view along the Y direction, and the second region R2 and the third region R3 are schematic cross-sectional views along the X direction.

A shallow trench isolation structure 14 is formed in the substrate 10. The shallow trench isolation structure 14 is formed by, for example, forming a plurality of trenches 12 in the substrate 10, and then forming an insulating layer on the substrate 10 and in the trenches 12. A chemical mechanical polishing process (abbreviated as CMP4) is then performed to remove excess insulating layer on the substrate 10.

Next, a device layer 20 is formed on the substrate 10. The device layer 20 may include active devices or passive devices. The active devices are, for example, transistors, diodes, etc. The passive devices are, for example, capacitors, inductors, etc. The transistors may be N-type metal oxide semiconductor (NMOS) transistors, P-type metal oxide semiconductor (PMOS) transistors, or complementary metal oxide semiconductor devices (CMOS).

An interconnect structure 30 is formed on the device layer 20. The interconnect structure 30 may include a plurality of dielectric layers 32 and metal interconnects 33 formed in the plurality of dielectric layers 32. The metal interconnects 33 include a plurality of plugs 34 and a plurality of wires 36. The dielectric layer 32 separates adjacent wires 36. The wires 36 may be connected to each other through the plugs 34, and the wires 36 may be connected to the device layer 20 through the plugs 34. Any layer in the dielectric layer 32 may have a flat surface by a chemical mechanical polishing process (abbreviated as CMP1).

6B , a stacking structure SK1 is formed on the interconnect structure 30. The stacking structure SK1 includes a plurality of insulating layers 92 and a plurality of conductive layers 94 alternately stacked in the Z direction. Since the memory array will be formed directly above the stacking structure SK1 in the first region R1, and the device layer 20, such as a complementary metal oxide semiconductor device (CMOS), is formed below the memory array, this structure can also be referred to as a complementary metal oxide semiconductor device below the memory array (CMOS-Under-Array, CUA) structure.

6C , the stacked structure SK1 is patterned to form a groove, and an insulating material (such as silicon oxide) is filled in the groove. Then, a chemical mechanical planarization process (abbreviated as CMP5) is performed to remove excess insulating material to form an insulating structure 95 .

Please refer to FIG. 6D , and then, a stacking structure SK2 is formed on the substrate 10. The stacking structure SK2 includes a plurality of insulating layers 102 and a plurality of spacer layers 104 stacked alternately. In one embodiment, the material of the insulating layer 102 includes silicon oxide, and the material of the spacer layer 104 includes silicon nitride. The spacer layer 104 can be used as a sacrificial layer, which will be partially or completely removed in a subsequent process. Then, a stop layer 105 is formed on the stacking structure SK2. The material of the stop layer 105 is different from that of the insulating layer 102 and the spacer layer 104, for example, polysilicon. Next, the spacer layer 104 and the insulating layer 102 of the stacking structure SK2 in the second region R2 are patterned to form a step structure SC.

Referring to FIG. 6E , a dielectric layer 103 is formed on the substrate 10 to cover the step structure SC. The material of the dielectric layer 103 is, for example, silicon oxide. The method of forming the dielectric layer 103 is, for example, forming a dielectric material layer to fill and cover the step structure SC. The dielectric layer 103 is, for example, silicon oxide formed by plasma enhanced chemical vapor deposition using tetraethylsiloxane as a precursor. Since the step structure SC has multiple steps with large height differences, the topology of the surface of the dielectric layer 103 has large ups and downs.

Please refer to Figure 6F, then the stop layer 105 is used as the grinding stop layer to perform a planarization process, such as a chemical mechanical grinding process (abbreviated as CMP2), to remove the dielectric layer 103 above the stop layer 105. The chemical mechanical grinding process CMP2 of the embodiment of the present invention uses a grinding pad with higher hardness and lower roughness. In the embodiment of the present invention, the depth of the grooves of the grinding pad is less than 30 mil. The porosity of the grinding pad is 0 to 30%. The dresser (Disk) used in the chemical mechanical grinding process CMP2 can have a circular or donut-shaped profile. The dresser of the chemical mechanical grinding process CMP2 has a higher removal rate, for example, a removal rate of 300-600 microns/hour. The slurry of the chemical mechanical polishing process CMP2 has a lower concentration of abrasive particles, and the concentration of the abrasive particles in the slurry is, for example, less than 15%. The abrasive particles include silicon oxide, aluminum oxide, vanadium oxide or a combination thereof. Afterwards, the stop layer 105 is removed.

Referring to FIG. 6G , an insulating cap layer 115 is formed on the stacked structure SK2. In one embodiment, the material of the insulating cap layer 115 includes silicon oxide. A patterning process is performed to form one or more openings 106 passing through the insulating cap layer 115, the stacked structure SK2, and the stacked structure SK1. In one embodiment, the opening 106 is also referred to as a vertical channel (VC) hole. A charge storage structure 108 is then formed in the opening 106. The charge storage structure 108 contacts the insulating cap layer 115, the insulating layer 102, the spacer layer 104, the insulating layer 92, and the conductive layer 94. In one embodiment, the charge storage structure 108 is an oxide/nitride/oxide (ONO) composite layer. Then, a channel layer 110, an insulating column 112, and a conductive plug 114 are formed on the charge storage structure 108 to form a vertical channel column CP. The material of the channel layer 110 and the conductive plug 114 includes polysilicon. The material of the insulating column 112 includes silicon oxide. The conductive plug 114 contacts the channel layer 110. The charge storage structure 108 surrounds the outer surface of the vertical channel pillar CP.

Continuing with FIG. 6G , the stacked structure SK2 is patterned to form a plurality of trenches 116. The trenches 116 extend in the X direction and pass through the insulating cap layer 115 and the stacked structure SK2 to divide the stacked structure SK2 into a plurality of blocks B (e.g., B1 and B2). The slit trenches 116 expose the side walls of the insulating cap layer 115, the spacer layer 104, and the insulating layer 102.

Referring to FIG. 6H , a replacement process is then performed to replace the spacer layer 104 in the first region R1 and the second region R2 with a conductive layer 126. The conductive layer 126 can be used as a gate layer. The conductive layer 126, for example, includes a barrier layer 122 and a metal layer 124. In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W).

Next, a spacer 117 is formed on the sidewall of the trench 116. The spacer 117 includes a dielectric material different from the insulating layer 102, such as silicon nitride or a silicon oxide/silicon nitride/silicon oxide composite layer. Afterwards, the depth of the trench 116 is deepened, and the middle conductor layer 94 and the insulating layers 92 above and below it are removed, and then the conductor layers 93a, 93b and the conductor pad 96 are formed. The conductor layers 93a and 93b are, for example, doped polysilicon layers. The material of the conductor pad 96 is, for example, tungsten. The conductor layer 93a and the conductor layers 94 above and below it together form a source line 120. The source line 120 can also be called a common source conductor layer 120. The conductive pad 96 and the conductive layer 93 b in the trench 116 together form a source line conductive wall 118 for conducting current from the source line 120 . The source line conductive wall 118 is isolated by the spacer 117 to avoid contact with the conductive layer 126 .

6H , a selective source line cut slit 107 extending in the X direction is formed in a portion of the insulating cap layer 115 and a portion of the stacking structure SK2 of each block B. The selective source line cut slit 107 is an insulating material, such as silicon oxide, to separate the upper conductive layers 126 of the stacking structure SK2 of each block B from each other. The selective source line cutting wall 107 may be formed by forming a trench OP1 in the insulating cap layer 115 and a portion of the stacked structure SK2, and then forming an insulating material on the insulating cap layer 115, and then performing a chemical mechanical polishing process (abbreviated as CMP6) to remove excess insulating material on the insulating cap layer 115. The selective source line cutting wall 107 may be formed at any time, and may also be formed previously, for example, before forming the step structure SC.

Please refer to FIG. 6I . Subsequently, a dielectric layer 128, a stop layer 129 and a dielectric layer 130 are formed on the insulating cap layer 115. The dielectric layers 128 and 130 are, for example, silicon oxide, and the stop layer 129 is, for example, silicon nitride. Thereafter, lithography and etching processes are performed to form contact windows C1, C2 and TAC in the first region R1, the second region R2 and the third region R3, respectively. The contact window C1 lands on the conductive plug 114 of the vertical channel column CP and is electrically connected thereto. The contact window C2 passes through the dielectric layer 103, lands on the surface of the end of the conductive layer 126 of the step structure SC, and is electrically connected to the conductive layer 126. The contact window TAC may also be referred to as a through array contact. The contact window TAC passes through the insulating cap layer 115 and the stacked structures SK2 and SK1 from the dielectric layer 130, lands on the interconnect structure 30, and is electrically connected to the wire 36.

Referring to FIG. 6J , an internal connection structure 40 is formed. The internal connection structure 40 may include a plurality of dielectric layers 42 and a plurality of plugs 44 and a plurality of wires 46 formed in the plurality of dielectric layers 42. The dielectric layer 42 separates adjacent wires 46. The wires 46 may be connected to each other through the plugs 44, and the wires 46 may be electrically connected to the contact windows C1, C2 and TAC, respectively. The wire 46 connected to the contact window C1 may serve as a bit line BL. Any layer in the dielectric layer 42 may have a flat surface by a chemical mechanical polishing process (abbreviated as CMP3).

Afterwards, subsequent related processes are carried out to complete the production of memory devices.

The polishing pad used in the chemical mechanical polishing process CMP2 of the embodiment of the present invention has a higher hardness. The hardness of the polishing pad used in the chemical mechanical polishing process CMP2 is higher than the hardness of the polishing pads used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5 and CMP6.

The polishing pad used in the chemical mechanical polishing process CMP2 has a lower roughness. The roughness of the polishing pad used in the chemical mechanical polishing process CMP2 is lower than the roughness of the polishing pads used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5, and CMP6.

The polishing pad used in the chemical mechanical polishing process CMP2 has a shallower groove depth. The groove depth of the polishing pad used in the chemical mechanical polishing process CMP2 is lower than the groove depths of the polishing pads used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5, and CMP6.

The polishing pad used in the chemical mechanical polishing process CMP2 has a lower porosity. The porosity of the polishing pad used in the chemical mechanical polishing process CMP2 is lower than the porosity of the polishing pad used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5, and CMP6.

The conditioner used in the chemical mechanical polishing process CMP2 has a higher removal rate. The removal rate of the conditioner used in the chemical mechanical polishing process CMP2 is higher than the removal rates of the conditioners used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5, and CMP6.

The slurry used in the chemical mechanical polishing process CMP2 has a lower abrasive concentration. The abrasive concentration of the slurry used in the chemical mechanical polishing process CMP2 is lower than the abrasive concentration of the slurry used in the chemical mechanical polishing processes CMP1, CMP3, CMP4, CMP5, and CMP6.

Since the chemical mechanical polishing process CMP2 of the embodiment of the present invention uses a polishing pad with higher hardness, lower roughness, shallower groove depth and lower porosity, and is used in conjunction with a slurry with lower abrasive concentration and a dresser with higher removal rate, groove clogging can be reduced and the service life and service life of the polishing pad can be extended.

10, 200: substrate 12: trench 14: isolation structure 20: component layer 30, 40: interconnect structure 32, 42, 103, 128, 130, 203: dielectric layer 33: metal interconnect 34, 44: plug 36, 46: wire 92, 102, 202: insulation layer 93, 93a, 93b, 94: conductor layer 95b, 95c: insulation structure 96: conductor pad 98: connection pad 104, 204: spacer layer 105, 129: stop layer 106: opening 107: source line cutting wall selection 108: Charge storage structure 110: Channel layer 111b, 111c: Groove 112: Insulation column 114: Conductor plug 115: Insulation cap layer 116: Trench 117: Spacer 118: Source line conductor wall 120: Source line, common source conductor layer 121, 123: Horizontal opening 122: Barrier layer 124: Metal layer 126: Conductor layer 200W: Wafer 300: Grinding pad 302: Trench 400: Trimmer B, B1, B2: Block BL: Bit line C1, C2, TAC: contact window CP: vertical channel column H1, H2: height OP1: trench R1: first zone R2: second zone R3: third zone SC: step structure SK0, SK1, SK2: stacking structure X, Y, Z: direction

FIG. 1A to FIG. 1B are cross-sectional schematic diagrams of an intermediate stage of a three-dimensional memory device manufacturing method according to an embodiment of the present invention. FIG. 2A and FIG. 2B are a top view and a partial stereoscopic view of a polishing pad used in a chemical mechanical polishing process according to an embodiment of the present invention. FIG. 3A and FIG. 3B are top views of a trimmer used in a chemical mechanical polishing process according to an embodiment of the present invention. FIG. 4 shows the groove depth of the polishing pad used in a chemical mechanical polishing process according to the present invention after long-term polishing. FIG. 5 shows the removal rate of the dielectric layer at each radial position of the wafer during a chemical mechanical polishing process according to an embodiment of the present invention as the polishing pad is used. Figures 6A to 6J are cross-sectional schematic diagrams of a method for manufacturing a three-dimensional memory element according to an embodiment of the present invention.

300: Grinding pad

302: Grooves

d1: depth

Claims (9)

A method for manufacturing a memory element, comprising: forming a first interconnect on a substrate; forming a first dielectric layer on the first interconnect; performing a first chemical mechanical polishing process on the first dielectric layer; forming a stacking structure on the first dielectric layer; forming a step structure in the stacking structure; forming a second dielectric layer on the substrate to cover the stacking structure and the step structure; and performing a second chemical mechanical polishing process on the second dielectric layer, wherein the depth of the second groove of the second polishing pad used in the second chemical mechanical polishing process is lower than the depth of the first groove of the first polishing pad used in the first chemical mechanical polishing process, wherein the porosity of the second polishing pad is lower than the porosity of the first polishing pad, wherein the hardness of the second polishing pad is higher than the hardness of the first polishing pad, Wherein, the roughness of the second polishing pad is lower than the roughness of the first polishing pad. A method for manufacturing a memory device as described in claim 1, wherein the dresser used in the second chemical mechanical polishing process has a circular or donut-shaped profile. The method for manufacturing a memory device as described in claim 2, wherein a removal rate of the trimmer used in the second chemical mechanical polishing process is higher than a removal rate of the trimmer used in the first chemical mechanical polishing process. A method for manufacturing a memory device as described in claim 1, wherein the concentration of abrasive particles in the second slurry used in the second chemical mechanical polishing process is lower than the concentration of abrasive particles in the first slurry used in the first chemical mechanical polishing process. A method for manufacturing a memory device as described in claim 4, wherein the abrasive particles of the second slurry include silicon oxide, aluminum oxide, vanadium oxide or a combination thereof. The method for manufacturing a memory element as described in claim 1 further includes: forming a second interconnection above the second dielectric layer; forming a third dielectric layer on the second interconnection; and performing a third planarization process using a third chemical mechanical polishing process to planarize the third dielectric layer, wherein the depth of the second groove of the second polishing pad used in the second chemical mechanical polishing process is lower than the depth of the third groove of the third polishing pad used in the third chemical mechanical polishing process, wherein the porosity of the second polishing pad is lower than the porosity of the third polishing pad, wherein the hardness of the second polishing pad is higher than the hardness of the third polishing pad. The method for manufacturing a memory device as described in claim 6, wherein a removal rate of a trimmer used in the second chemical mechanical polishing process is higher than a removal rate of a trimmer used in the third chemical mechanical polishing process. A method for manufacturing a memory device as described in claim 6, wherein the concentration of abrasive particles in the second slurry used in the second chemical mechanical polishing process is lower than the concentration of abrasive particles in the third slurry used in the third chemical mechanical polishing process. The manufacturing method of the memory element as described in claim 6 further includes: forming a trench in the substrate; forming an insulating layer in the trench; performing a fourth planarization process by a fourth chemical mechanical polishing process to planarize the insulating layer and form a shallow trench isolation structure, wherein the depth of the second trench of the second polishing pad used in the second chemical mechanical polishing process is lower than the depth of the fourth trench of the fourth polishing pad used in the fourth chemical mechanical polishing process, wherein the porosity of the second polishing pad is lower than the porosity of the fourth polishing pad, wherein the hardness of the second polishing pad is higher than the hardness of the fourth polishing pad, wherein the removal rate of the dresser used in the second chemical mechanical polishing process is higher than the removal rate of the dresser used in the fourth chemical mechanical polishing process, The concentration of abrasive particles in the second slurry used in the second chemical mechanical polishing process is lower than the concentration of abrasive particles in the fourth slurry used in the fourth chemical mechanical polishing process.