TWI841375B - Synchronization system for network clock signal - Google Patents

Abstract

A system is configured for synchronizing network clock signal clock signal. In the system, at least one relay communication device is configured to generate a built-in clock signal, and receive an original master clock signal from a master communication device. When the relay communication device receives the original master clock signal, a synchronization clock signal is generated as a standard system clock signal by synchronizing the built-in clock signal with the original master clock signal; and when interrupting receiving the original master clock signal, the built-in clock signal is served as the standard system clock signal. The relay communication device further transmits the standard system clock signal to at least one downlink communication device to be served as a synchronization standard system clock signal of the downlink communication device.

Description

Network clock signal synchronization system

The present invention relates to a synchronization system, and more particularly to a network clock signal synchronization system.

In network communication systems, many tasks must be performed accurately under a synchronized time system. Especially when performing tasks related to timing, if the time system is not synchronized, it may cause errors in calculation results (such as counting or timing errors) or program logic contradictions and inability to continue to execute tasks. Since data transmission is completed within milliseconds, microseconds or even shorter times, once the clock signal has a slight error, the above problems are more likely to occur.

Generally speaking, network time is mostly transmitted in the form of time pulses. To achieve network time synchronization, a clock signal (such as a crystal clock signal) generated by a built-in clock generating device (such as a quartz crystal oscillator) is usually set in the top layer (service) communication node device at the top of a network architecture (usually a node with a large amount of data access, such as a cloud server or file server) as a master clock signal, and is transmitted from the top layer communication node device to all downstream communication devices (such as switches, gateways, repeaters, routers or terminal working devices) through the downstream communication path, and all downstream communication devices can use the master clock signal as the basis for time synchronization, so that the time of the top layer communication node device and all its downstream communication devices can be synchronized.

However, in practice, once the built-in clock generator of the top-level (service) communication node device fails (including long-term failures caused by damage to the device itself or damage to the connecting line, or temporary failures caused by temporary overload of components), the main clock signal cannot be transmitted to the downstream communication device, causing all downstream communication devices to be unable to maintain time synchronization with each other due to interruption of receiving the main clock signal.

In view of the fact that in the prior art, once the master clock signal cannot be transmitted to the downlink communication device, it will cause the problem that all the downlink communication devices cannot maintain time synchronization. The main purpose of the present invention is to provide a new network clock signal synchronization system, so that when the master clock signal is interrupted from being transmitted to the downlink communication device, at least some of the downlink communication devices can still maintain time synchronization.

One of the necessary technical means adopted by the present invention to solve the problems of the prior art is to provide a network clock signal synchronization system, which includes a main communication device, at least one relay communication device and at least one downlink communication device. The main communication device provides a main clock signal. The relay communication device is connected to the main communication device by uplink communication and includes a built-in clock signal generation module, a physical layer module and a system time generation module.

The built-in clock signal generation module is used to send a built-in clock signal. The port physical layer module is used to receive the main clock signal. The system time generation module is electrically connected to the port physical layer module and the built-in clock signal generation module, and includes a phase-locked loop and a system clock signal sending unit. The phase-locked loop (PLL) is used to synchronize the built-in clock signal with the main clock signal to generate a synchronous clock signal when the port physical layer module receives the main clock signal.

The system clock signal sending unit is used to send out the synchronous clock signal as a system reference clock signal of the relay communication device when the port physical layer module receives the main clock signal, and to send out the built-in clock signal as the system reference clock signal when the port physical layer module stops receiving the main clock signal. The downlink communication device is used for the downlink communication connection of the relay communication device to receive the system reference clock signal as a synchronized system reference clock signal of the downlink communication device.

Preferably, the built-in clock signal generating module may further include a built-in clock signal oscillating unit, a phase-locked compensation signal detecting unit and a built-in clock signal output unit. The built-in clock signal oscillating unit sends out an original oscillating clock signal. The phase-locked compensation signal detecting unit is electrically connected to the built-in clock signal oscillating unit and the phase-locked loop to detect a clock compensation signal superimposed when the original oscillating clock signal is synchronized with the main clock signal. The built-in clock signal output unit is electrically connected to the built-in clock signal oscillation unit, the phase-locked compensation signal detection unit and the port physical layer module, and is used to superimpose the original oscillation clock signal and the clock compensation signal and send them out as the above-mentioned built-in clock signal when the port physical layer module stops receiving the main clock signal.

Preferably, the built-in clock signal oscillator unit may be a quartz crystal oscillator. The relay communication device may be a network switch. The main communication device may be a server. The downlink communication device may be a network switch, a gateway, a repeater, a router or a terminal working device. The system time generation module may further include a media access control (MAC) sublayer time generation unit for generating a media access time according to the system reference clock signal.

In summary, in the network clock signal synchronization system provided by the present invention, even when the relay communication device stops receiving the main clock signal, the built-in clock signal generated by the built-in clock signal generation module can be used as the system reference clock signal, and the system reference clock signal can be transmitted to the downlink communication device as a synchronization system reference clock signal of the downlink communication device, thereby maintaining the time synchronization between the relay communication device and the downlink communication device.

More preferably, the clock compensation signal detected by the phase-locked compensation signal detection unit can be used as the basis for time compensation. By superimposing the original oscillating clock signal and the clock compensation signal, the relay communication device can keep the system reference clock signal or the synchronized system reference clock signal as close to the master clock signal as possible even when the relay communication device stops receiving the master clock signal. Undoubtedly, the present invention can achieve the effect of maintaining system time synchronization (between the relay communication device and the downlink communication device) to the maximum extent even when the relay communication device stops receiving the master clock signal.

Since the network clock signal synchronization system provided by the present invention can be widely used in a variety of network systems, its application is quite broad, so it will not be described one by one here, and only the better embodiments are listed for specific explanation, and this embodiment is only used to conveniently and clearly assist in explaining the purpose and effect of the embodiment of the present invention.

Please refer to the first figure, which is a functional block diagram of the network clock signal synchronization system provided by the preferred embodiment of the present invention. As shown in the first figure, a network clock signal synchronization system 100 includes a main communication device 1, at least one relay communication device (a relay communication device 2 is drawn as a representative in the first figure) and at least one downlink communication device (two downlink communication devices 3a and 3b are drawn as representatives in the first figure).

The master communication device 1 may be a communication device that processes large amounts of data in the network and provides large amounts of services to multiple devices, such as a cloud server, a file server, or a web server. The master communication device 1 may have a built-in master clock signal generating device (such as a quartz crystal oscillator, not shown) to provide a master clock signal MCS.

The relay communication device 2 may be a network switch, and is connected to the main communication device 1 for uplink communication, and includes a built-in clock signal generation module 21, a port physical layer (PHY) module 22, and a system time generation module 23. The so-called uplink communication link refers to a communication link for data transmission toward or close to the communication node of the main communication device 1 that has a large data processing volume and provides a large service volume to multiple devices. The meaning of the downlink communication link is opposite to the uplink communication link, and the uplink communication link and the downlink communication link are relative concepts, which will not be elaborated below.

The built-in clock signal generating module 21 may include a built-in clock signal oscillating unit 211, a phase-locked compensation signal detecting unit 212 and a built-in clock signal outputting unit 213 which are electrically connected to each other, wherein the built-in clock signal oscillating unit 211 may be a quartz crystal oscillator and used to send out an original oscillating clock signal OCCS.

The port physical layer (PHY) module 22 is used to receive the main clock signal MCS. The port physical layer refers to a common abbreviation for the physical layer of the Open System Interconnection Model (OSI model). The port physical layer module 22 can be a device that operates the physical layer of the OSI model. In the Ethernet, the port physical layer (PHY) module 22 can be a chip and is used to send and receive Ethernet data frames, but usually does not have a media access control (MAC) sublayer address (MAC address).

The system time generation module 23 is electrically connected to the port physical layer module 22 and the built-in clock signal generation module 21, and includes a phase-locked loop (PLL) 231, a system clock signal sending unit 232 and a media access control (MAC) sublayer time generation unit 233, and the system clock signal sending unit 232 is electrically connected to the phase-locked loop 231 and the MAC sublayer time generation unit 233 respectively.

When the port physical layer module 22 receives the master clock signal MCS, the built-in clock signal output unit 213 can know that the port physical layer module 22 has received the master clock signal MCS by means of detection or the like. At this time, the built-in clock signal output unit 213 can directly transmit the original oscillation clock signal OCCS generated by the built-in clock signal oscillation unit 211 as a built-in clock signal ICS to the phase-locked loop (PLL) 231, and the phase-locked loop (PLL) 231 can obtain the master clock signal MCS from the port physical layer module 22.

Accordingly, the phase-locked loop (PLL) 231 synchronizes the built-in clock signal ICS with the main clock signal MCS to generate a synchronous clock signal SCS, and the system clock signal sending unit 232 can further send the synchronous clock signal SCS as a system reference clock signal SRCS of the relay communication device. The so-called synchronization refers to adjusting the frequency and/or phase of one of the two signals to make it the same as the frequency and phase of the other.

Preferably, the phase-locked compensation signal detection unit 212 can be used to detect a clock compensation signal CCS superimposed when the original oscillating clock signal OCC used as the built-in clock signal ICS is synchronized with the main clock signal MCS, and convert the clock compensation signal CCS into digital data for storage. The so-called clock compensation signal CCS refers to the compensation signal superimposed on the built-in clock signal ICS by adjusting the frequency and/or phase of the built-in clock signal ICS so that the frequency and phase of the built-in clock signal ICS and the main clock signal MCS are the same.

Better yet, when the port physical layer module 22 stops receiving the main clock signal MCS, the built-in clock signal output unit 213 may request the phase-locked compensation signal detection unit 212 to use an oscillator (not shown) to restore and generate the clock compensation signal CCS based on the above-mentioned digital data, and superimpose the original oscillation clock signal ICS and the clock compensation signal CCS as the built-in clock signal ICS and send it to the system clock signal sending unit 232, and the system clock signal sending unit 232 can send the built-in clock signal ICS as the system reference clock signal SRCS.

From the above description, it can be seen that, due to the superposition compensation of the clock compensation signal CCS, the built-in clock signal ICS will at least maintain the same or the greatest degree of similarity with the main clock signal MCS for a certain period of time. In addition, regardless of whether the port physical layer module 22 receives or stops receiving the main clock signal MCS, the system clock signal sending unit 232 can send out the system reference clock signal SRCS.

The system reference clock signal SRCS sent by the system clock signal sending unit 232 can not only be transmitted to the MAC sublayer time generation unit 233, but can also be transmitted to the downlink communication devices 3a and 3b respectively by connecting to the downlink communication devices 3a and 3b via downlink communication. The MAC sublayer time generation unit 233 can be built into a MAC sublayer element (not shown), and when the MAC sublayer element generates each media access data, it generates a media access time bound to the media access data according to the system reference clock signal SRCS.

Downlink communication devices 3a and 3b may be network switches, gateways, repeaters, routers or terminal (working) devices (such as workstation terminal equipment, industrial computers, personal computers, laptops, tablet computers or smart phones, etc.). At the same time, downlink communication devices 3a and 3b may use the received system reference clock signal SRCS as one of the synchronization system reference clock signals of downlink communication devices 3a and 3b. In this way, when the port physical layer module 22 receives the master clock signal MCS, time synchronization between the main communication device 1, the relay communication device 2 and the downlink communication devices 3a and 3b can be achieved. Even when the port physical layer module 22 stops receiving the master clock signal MCS, time synchronization between the relay communication device 2 and the downlink communication devices 3a and 3b can still be achieved.

The above-mentioned master clock signal MCS, original oscillation clock signal OCCS, clock compensation signal CCS, built-in clock signal ICS, synchronous clock signal SCS, system reference clock signal SRCS and synchronized system reference clock signal are essentially time-related pulse signals, so they are all clock pulse signals.

In the network clock signal synchronization system 100 provided by the present invention, even when the relay communication device 2 stops receiving the master clock signal MCS, the built-in clock signal ICS generated by the built-in clock signal generation module 21 can be used as the system reference clock signal SRCS, and the system reference clock signal SRCS can be transmitted to the downlink communication devices 3a and 3b as the synchronization system reference clock signal of the downlink communication devices 3a and 3b, thereby maintaining the time synchronization between the relay communication device 2 and the downlink communication devices 3a and 3b.

More preferably, the clock compensation signal CCS detected by the phase-locked compensation signal detection unit 212 can be used as the basis for time compensation. By superimposing the original oscillation clock signal OCCS and the clock compensation signal CCS, the relay communication device 2 can keep the system reference clock signal SRCS or the synchronized system reference clock signal as close to the master clock signal MCS as possible even when the relay communication device 2 stops receiving the master clock signal MCS. Undoubtedly, the present invention can achieve the effect of maintaining the system time synchronization (between the relay communication device 2 and the downlink communication devices 3a and 3b) to the maximum extent when the relay communication device 2 stops receiving the master clock signal MCS.

The above detailed description of the preferred specific embodiments is intended to more clearly describe the features and spirit of the present invention, but is not intended to limit the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the purpose is to cover various changes and arrangements with equivalents within the scope of the patent application for the present invention.

100: Network clock signal synchronization system 1: Main communication device 2: Relay communication device 21: Built-in clock signal generation module 211: Built-in clock signal oscillation unit 212: Phase-locked compensation signal detection unit 213: Built-in clock signal output unit 22: Port physical layer module 23: System time generation module 231: Phase-locked loop 232: System clock signal transmission unit 233: MAC sublayer time generation unit 3a~3b: Downlink communication device OCCS: Original oscillation clock signal CCS: Clock compensation signal SCS: Synchronous clock signal MCS: Master clock signal ICS: Built-in clock signal SRCS: System Reference Clock Signal

The first figure is a functional block diagram of the network clock signal synchronization system provided by the preferred embodiment of the present invention.

100: Network clock signal synchronization system

1: Main communication device

2: Relay communication device

21: Built-in clock signal generation module

211: Built-in clock signal oscillator unit

212: Phase-locked compensation signal detection unit

213: Built-in clock signal output unit

22: Port physical layer module

23: System time generation module

231: Phase-locked loop

232: System clock signal sending unit

233: MAC sublayer time generation unit

3a~3b: Downlink communication device

OCCS: Original Oscillating Clock Signal

CCS: Clock Compensation Signal

SCS: Synchronous Clock Signal

MCS: Master Clock Signal

ICS: built-in clock signal

SRCS: System Reference Clock Signal

Claims (7)

A network clock signal synchronization system includes: A main communication device that provides a main clock signal; At least one relay communication device that is connected to the main communication device by uplink communication and includes: A built-in clock signal generation module that is used to send a built-in clock signal; A port physical layer (PHY) module that is used to receive the main clock signal; A system time generation module that is electrically connected to the port physical layer module and the built-in clock signal generation module and includes: A phase-locked loop (PLL) that is used to synchronize the built-in clock signal with the main clock signal to generate a synchronous clock signal when the port physical layer module receives the main clock signal; and A system clock signal sending unit is used to send the synchronous clock signal as a system reference clock signal of the at least one relay communication device when the port physical layer module receives the main clock signal, and to send the built-in clock signal as the system reference clock signal when the port physical layer module stops receiving the main clock signal; and At least one downstream communication device is used for the at least one relay communication device to connect to the downstream communication so as to receive the system reference clock signal as a synchronized system reference clock signal of the at least one downstream communication device. The network clock signal synchronization system as described in claim 1, wherein the built-in clock signal generation module further comprises: A built-in clock signal oscillator unit that sends out an original oscillating clock signal; A phase-locked compensation signal detection unit that is electrically connected to the built-in clock signal oscillator unit and the phase-locked loop to detect a clock compensation signal superimposed when the original oscillating clock signal is synchronized with the main clock signal; and A built-in clock signal output unit is electrically connected to the built-in clock signal oscillation unit, the phase-locked compensation signal detection unit and the port physical layer module, and is used to superimpose the original oscillation clock signal and the clock compensation signal as the built-in clock signal and send it out when the port physical layer module stops receiving the main clock signal. A network clock signal synchronization system as described in claim 2, wherein the built-in clock signal oscillator unit is a quartz crystal oscillator. A network clock signal synchronization system as described in claim 1, wherein the at least one relay communication device is at least one network switch. A network clock signal synchronization system as described in claim 1, wherein the main communication device is a server. A network clock signal synchronization system as described in claim 1, wherein the at least one downstream communication device is at least one network switch, gateway, repeater, router or terminal working device. A network clock signal synchronization system as described in claim 1, wherein the system time generation module further includes a media access control (MAC) sublayer time generation unit for generating a media access time based on the system reference clock signal.

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